[deliverable/linux.git] / sound / soc / tegra / tegra_pcm.c

/*
 * tegra_pcm.c - Tegra PCM driver
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 * Copyright (C) 2010,2012 - NVIDIA, Inc.
 *
 * Based on code copyright/by:
 *
 * Copyright (c) 2009-2010, NVIDIA Corporation.
 * Scott Peterson <speterson@nvidia.com>
 * Vijay Mali <vmali@nvidia.com>
 *
 * Copyright (C) 2010 Google, Inc.
 * Iliyan Malchev <malchev@google.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#include "tegra_pcm.h"

static const struct snd_pcm_hardware tegra_pcm_hardware = {
	.info			= SNDRV_PCM_INFO_MMAP |
				  SNDRV_PCM_INFO_MMAP_VALID |
				  SNDRV_PCM_INFO_PAUSE |
				  SNDRV_PCM_INFO_RESUME |
				  SNDRV_PCM_INFO_INTERLEAVED,
	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
	.channels_min		= 2,
	.channels_max		= 2,
	.period_bytes_min	= 1024,
	.period_bytes_max	= PAGE_SIZE,
	.periods_min		= 2,
	.periods_max		= 8,
	.buffer_bytes_max	= PAGE_SIZE * 8,
	.fifo_size		= 4,
};

#if defined(CONFIG_TEGRA_SYSTEM_DMA)
static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
{
	struct snd_pcm_substream *substream = prtd->substream;
	struct snd_dma_buffer *buf = &substream->dma_buffer;
	struct tegra_dma_req *dma_req;
	unsigned long addr;

	dma_req = &prtd->dma_req[prtd->dma_req_idx];
	prtd->dma_req_idx = 1 - prtd->dma_req_idx;

	addr = buf->addr + prtd->dma_pos;
	prtd->dma_pos += dma_req->size;
	if (prtd->dma_pos >= prtd->dma_pos_end)
		prtd->dma_pos = 0;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_req->source_addr = addr;
	else
		dma_req->dest_addr = addr;

	tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
}

static void dma_complete_callback(struct tegra_dma_req *req)
{
	struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
	struct snd_pcm_substream *substream = prtd->substream;
	struct snd_pcm_runtime *runtime = substream->runtime;

	spin_lock(&prtd->lock);

	if (!prtd->running) {
		spin_unlock(&prtd->lock);
		return;
	}

	if (++prtd->period_index >= runtime->periods)
		prtd->period_index = 0;

	tegra_pcm_queue_dma(prtd);

	spin_unlock(&prtd->lock);

	snd_pcm_period_elapsed(substream);
}

static void setup_dma_tx_request(struct tegra_dma_req *req,
					struct tegra_pcm_dma_params * dmap)
{
	req->complete = dma_complete_callback;
	req->to_memory = false;
	req->dest_addr = dmap->addr;
	req->dest_wrap = dmap->wrap;
	req->source_bus_width = 32;
	req->source_wrap = 0;
	req->dest_bus_width = dmap->width;
	req->req_sel = dmap->req_sel;
}

static void setup_dma_rx_request(struct tegra_dma_req *req,
					struct tegra_pcm_dma_params * dmap)
{
	req->complete = dma_complete_callback;
	req->to_memory = true;
	req->source_addr = dmap->addr;
	req->dest_wrap = 0;
	req->source_bus_width = dmap->width;
	req->source_wrap = dmap->wrap;
	req->dest_bus_width = 32;
	req->req_sel = dmap->req_sel;
}

static int tegra_pcm_open(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct tegra_runtime_data *prtd;
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct tegra_pcm_dma_params * dmap;
	int ret = 0;

	prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
	if (prtd == NULL)
		return -ENOMEM;

	runtime->private_data = prtd;
	prtd->substream = substream;

	spin_lock_init(&prtd->lock);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
		setup_dma_tx_request(&prtd->dma_req[0], dmap);
		setup_dma_tx_request(&prtd->dma_req[1], dmap);
	} else {
		dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
		setup_dma_rx_request(&prtd->dma_req[0], dmap);
		setup_dma_rx_request(&prtd->dma_req[1], dmap);
	}

	prtd->dma_req[0].dev = prtd;
	prtd->dma_req[1].dev = prtd;

	prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
	if (prtd->dma_chan == NULL) {
		ret = -ENOMEM;
		goto err;
	}

	/* Set HW params now that initialization is complete */
	snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);

	/* Ensure that buffer size is a multiple of period size */
	ret = snd_pcm_hw_constraint_integer(runtime,
						SNDRV_PCM_HW_PARAM_PERIODS);
	if (ret < 0)
		goto err;

	return 0;

err:
	if (prtd->dma_chan) {
		tegra_dma_free_channel(prtd->dma_chan);
	}

	kfree(prtd);

	return ret;
}

static int tegra_pcm_close(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct tegra_runtime_data *prtd = runtime->private_data;

	tegra_dma_free_channel(prtd->dma_chan);

	kfree(prtd);

	return 0;
}

static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct tegra_runtime_data *prtd = runtime->private_data;

	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);

	prtd->dma_req[0].size = params_period_bytes(params);
	prtd->dma_req[1].size = prtd->dma_req[0].size;

	return 0;
}

static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
{
	snd_pcm_set_runtime_buffer(substream, NULL);

	return 0;
}

static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct tegra_runtime_data *prtd = runtime->private_data;
	unsigned long flags;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		prtd->dma_pos = 0;
		prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
		prtd->period_index = 0;
		prtd->dma_req_idx = 0;
		/* Fall-through */
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		spin_lock_irqsave(&prtd->lock, flags);
		prtd->running = 1;
		spin_unlock_irqrestore(&prtd->lock, flags);
		tegra_pcm_queue_dma(prtd);
		tegra_pcm_queue_dma(prtd);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		spin_lock_irqsave(&prtd->lock, flags);
		prtd->running = 0;
		spin_unlock_irqrestore(&prtd->lock, flags);
		tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
		tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct tegra_runtime_data *prtd = runtime->private_data;

	return prtd->period_index * runtime->period_size;
}


static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
				struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;

	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
					runtime->dma_area,
					runtime->dma_addr,
					runtime->dma_bytes);
}

static struct snd_pcm_ops tegra_pcm_ops = {
	.open		= tegra_pcm_open,
	.close		= tegra_pcm_close,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= tegra_pcm_hw_params,
	.hw_free	= tegra_pcm_hw_free,
	.trigger	= tegra_pcm_trigger,
	.pointer	= tegra_pcm_pointer,
	.mmap		= tegra_pcm_mmap,
};
#else
static int tegra_pcm_open(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct device *dev = rtd->platform->dev;
	int ret;

	/* Set HW params now that initialization is complete */
	snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);

	ret = snd_dmaengine_pcm_open(substream, NULL, NULL);
	if (ret) {
		dev_err(dev, "dmaengine pcm open failed with err %d\n", ret);
		return ret;
	}

	return 0;
}

static int tegra_pcm_close(struct snd_pcm_substream *substream)
{
	snd_dmaengine_pcm_close(substream);
	return 0;
}

static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct device *dev = rtd->platform->dev;
	struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
	struct tegra_pcm_dma_params *dmap;
	struct dma_slave_config slave_config;
	int ret;

	dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);

	ret = snd_hwparams_to_dma_slave_config(substream, params,
						&slave_config);
	if (ret) {
		dev_err(dev, "hw params config failed with err %d\n", ret);
		return ret;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		slave_config.dst_addr = dmap->addr;
		slave_config.dst_maxburst = 4;
	} else {
		slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		slave_config.src_addr = dmap->addr;
		slave_config.src_maxburst = 4;
	}
	slave_config.slave_id = dmap->req_sel;

	ret = dmaengine_slave_config(chan, &slave_config);
	if (ret < 0) {
		dev_err(dev, "dma slave config failed with err %d\n", ret);
		return ret;
	}

	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	return 0;
}

static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
{
	snd_pcm_set_runtime_buffer(substream, NULL);
	return 0;
}

static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		return snd_dmaengine_pcm_trigger(substream,
					SNDRV_PCM_TRIGGER_START);

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		return snd_dmaengine_pcm_trigger(substream,
					SNDRV_PCM_TRIGGER_STOP);
	default:
		return -EINVAL;
	}
	return 0;
}

static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
				struct vm_area_struct *vma)
{
	struct snd_pcm_runtime *runtime = substream->runtime;

	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
					runtime->dma_area,
					runtime->dma_addr,
					runtime->dma_bytes);
}

static struct snd_pcm_ops tegra_pcm_ops = {
	.open		= tegra_pcm_open,
	.close		= tegra_pcm_close,
	.ioctl		= snd_pcm_lib_ioctl,
	.hw_params	= tegra_pcm_hw_params,
	.hw_free	= tegra_pcm_hw_free,
	.trigger	= tegra_pcm_trigger,
	.pointer	= snd_dmaengine_pcm_pointer,
	.mmap		= tegra_pcm_mmap,
};
#endif

static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
	struct snd_dma_buffer *buf = &substream->dma_buffer;
	size_t size = tegra_pcm_hardware.buffer_bytes_max;

	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
						&buf->addr, GFP_KERNEL);
	if (!buf->area)
		return -ENOMEM;

	buf->dev.type = SNDRV_DMA_TYPE_DEV;
	buf->dev.dev = pcm->card->dev;
	buf->private_data = NULL;
	buf->bytes = size;

	return 0;
}

static void tegra_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
	struct snd_pcm_substream *substream;
	struct snd_dma_buffer *buf;

	substream = pcm->streams[stream].substream;
	if (!substream)
		return;

	buf = &substream->dma_buffer;
	if (!buf->area)
		return;

	dma_free_writecombine(pcm->card->dev, buf->bytes,
				buf->area, buf->addr);
	buf->area = NULL;
}

static u64 tegra_dma_mask = DMA_BIT_MASK(32);

static int tegra_pcm_new(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_card *card = rtd->card->snd_card;
	struct snd_pcm *pcm = rtd->pcm;
	int ret = 0;

	if (!card->dev->dma_mask)
		card->dev->dma_mask = &tegra_dma_mask;
	if (!card->dev->coherent_dma_mask)
		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);

	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
		ret = tegra_pcm_preallocate_dma_buffer(pcm,
						SNDRV_PCM_STREAM_PLAYBACK);
		if (ret)
			goto err;
	}

	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
		ret = tegra_pcm_preallocate_dma_buffer(pcm,
						SNDRV_PCM_STREAM_CAPTURE);
		if (ret)
			goto err_free_play;
	}

	return 0;

err_free_play:
	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
err:
	return ret;
}

static void tegra_pcm_free(struct snd_pcm *pcm)
{
	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE);
	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
}

static struct snd_soc_platform_driver tegra_pcm_platform = {
	.ops		= &tegra_pcm_ops,
	.pcm_new	= tegra_pcm_new,
	.pcm_free	= tegra_pcm_free,
};

int __devinit tegra_pcm_platform_register(struct device *dev)
{
	return snd_soc_register_platform(dev, &tegra_pcm_platform);
}
EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);

void __devexit tegra_pcm_platform_unregister(struct device *dev)
{
	snd_soc_unregister_platform(dev);
}
EXPORT_SYMBOL_GPL(tegra_pcm_platform_unregister);

MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("Tegra PCM ASoC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
7605eb5b SW	1	/*
	2	* tegra_pcm.c - Tegra PCM driver
	3	*
	4	* Author: Stephen Warren <swarren@nvidia.com>
518de86b	5	* Copyright (C) 2010,2012 - NVIDIA, Inc.
7605eb5b SW	6	*
	7	* Based on code copyright/by:
	8	*
	9	* Copyright (c) 2009-2010, NVIDIA Corporation.
	10	* Scott Peterson <speterson@nvidia.com>
	11	* Vijay Mali <vmali@nvidia.com>
	12	*
	13	* Copyright (C) 2010 Google, Inc.
	14	* Iliyan Malchev <malchev@google.com>
	15	*
	16	* This program is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License
	18	* version 2 as published by the Free Software Foundation.
	19	*
	20	* This program is distributed in the hope that it will be useful, but
	21	* WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	23	* General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	28	* 02110-1301 USA
	29	*
	30	*/
	31
7605eb5b	32	#include <linux/dma-mapping.h>
7613c508	33	#include <linux/module.h>
7605eb5b SW	34	#include <linux/slab.h>
	35	#include <sound/core.h>
	36	#include <sound/pcm.h>
	37	#include <sound/pcm_params.h>
	38	#include <sound/soc.h>
df79f55d	39	#include <sound/dmaengine_pcm.h>
7605eb5b SW	40
	41	#include "tegra_pcm.h"
	42
	43	static const struct snd_pcm_hardware tegra_pcm_hardware = {
	44	.info = SNDRV_PCM_INFO_MMAP \|
	45	SNDRV_PCM_INFO_MMAP_VALID \|
	46	SNDRV_PCM_INFO_PAUSE \|
	47	SNDRV_PCM_INFO_RESUME \|
	48	SNDRV_PCM_INFO_INTERLEAVED,
	49	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	50	.channels_min = 2,
	51	.channels_max = 2,
	52	.period_bytes_min = 1024,
	53	.period_bytes_max = PAGE_SIZE,
	54	.periods_min = 2,
	55	.periods_max = 8,
	56	.buffer_bytes_max = PAGE_SIZE * 8,
	57	.fifo_size = 4,
	58	};
	59
df79f55d	60	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
7605eb5b SW	61	static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
	62	{
	63	struct snd_pcm_substream *substream = prtd->substream;
	64	struct snd_dma_buffer *buf = &substream->dma_buffer;
	65	struct tegra_dma_req *dma_req;
	66	unsigned long addr;
	67
	68	dma_req = &prtd->dma_req[prtd->dma_req_idx];
	69	prtd->dma_req_idx = 1 - prtd->dma_req_idx;
	70
	71	addr = buf->addr + prtd->dma_pos;
	72	prtd->dma_pos += dma_req->size;
	73	if (prtd->dma_pos >= prtd->dma_pos_end)
	74	prtd->dma_pos = 0;
	75
	76	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	77	dma_req->source_addr = addr;
	78	else
	79	dma_req->dest_addr = addr;
	80
	81	tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
	82	}
	83
	84	static void dma_complete_callback(struct tegra_dma_req *req)
	85	{
	86	struct tegra_runtime_data prtd = (struct tegra_runtime_data )req->dev;
	87	struct snd_pcm_substream *substream = prtd->substream;
	88	struct snd_pcm_runtime *runtime = substream->runtime;
	89
	90	spin_lock(&prtd->lock);
	91
	92	if (!prtd->running) {
	93	spin_unlock(&prtd->lock);
	94	return;
	95	}
	96
	97	if (++prtd->period_index >= runtime->periods)
	98	prtd->period_index = 0;
	99
	100	tegra_pcm_queue_dma(prtd);
	101
	102	spin_unlock(&prtd->lock);
	103
	104	snd_pcm_period_elapsed(substream);
	105	}
	106
	107	static void setup_dma_tx_request(struct tegra_dma_req *req,
	108	struct tegra_pcm_dma_params * dmap)
	109	{
	110	req->complete = dma_complete_callback;
	111	req->to_memory = false;
	112	req->dest_addr = dmap->addr;
	113	req->dest_wrap = dmap->wrap;
	114	req->source_bus_width = 32;
	115	req->source_wrap = 0;
	116	req->dest_bus_width = dmap->width;
	117	req->req_sel = dmap->req_sel;
	118	}
	119
	120	static void setup_dma_rx_request(struct tegra_dma_req *req,
	121	struct tegra_pcm_dma_params * dmap)
	122	{
	123	req->complete = dma_complete_callback;
	124	req->to_memory = true;
125	req->source_addr = dmap->addr;
126	req->dest_wrap = 0;
127	req->source_bus_width = dmap->width;
128	req->source_wrap = dmap->wrap;
129	req->dest_bus_width = 32;
130	req->req_sel = dmap->req_sel;
131	}
132
133	static int tegra_pcm_open(struct snd_pcm_substream *substream)
134	{
135	struct snd_pcm_runtime *runtime = substream->runtime;
136	struct tegra_runtime_data *prtd;
137	struct snd_soc_pcm_runtime *rtd = substream->private_data;
138	struct tegra_pcm_dma_params * dmap;
139	int ret = 0;
140
141	prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
142	if (prtd == NULL)
143	return -ENOMEM;
144
145	runtime->private_data = prtd;
146	prtd->substream = substream;
147
148	spin_lock_init(&prtd->lock);
149
150	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
151	dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
152	setup_dma_tx_request(&prtd->dma_req[0], dmap);
153	setup_dma_tx_request(&prtd->dma_req[1], dmap);
154	} else {
155	dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
156	setup_dma_rx_request(&prtd->dma_req[0], dmap);
157	setup_dma_rx_request(&prtd->dma_req[1], dmap);
158	}
159
160	prtd->dma_req[0].dev = prtd;
161	prtd->dma_req[1].dev = prtd;
162
163	prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
e1412e63 SW	164	if (prtd->dma_chan == NULL) {
e1412e63 SW	165	ret = -ENOMEM;
7605eb5b SW	166	goto err;
	167	}
	168
	169	/* Set HW params now that initialization is complete */
	170	snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
	171
	172	/* Ensure that buffer size is a multiple of period size */
	173	ret = snd_pcm_hw_constraint_integer(runtime,
	174	SNDRV_PCM_HW_PARAM_PERIODS);
	175	if (ret < 0)
	176	goto err;
	177
	178	return 0;
	179
	180	err:
	181	if (prtd->dma_chan) {
	182	tegra_dma_free_channel(prtd->dma_chan);
	183	}
	184
	185	kfree(prtd);
	186
	187	return ret;
	188	}
	189
	190	static int tegra_pcm_close(struct snd_pcm_substream *substream)
	191	{
	192	struct snd_pcm_runtime *runtime = substream->runtime;
	193	struct tegra_runtime_data *prtd = runtime->private_data;
	194
	195	tegra_dma_free_channel(prtd->dma_chan);
	196
	197	kfree(prtd);
	198
	199	return 0;
	200	}
	201
	202	static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
	203	struct snd_pcm_hw_params *params)
	204	{
	205	struct snd_pcm_runtime *runtime = substream->runtime;
	206	struct tegra_runtime_data *prtd = runtime->private_data;
	207
	208	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	209
	210	prtd->dma_req[0].size = params_period_bytes(params);
	211	prtd->dma_req[1].size = prtd->dma_req[0].size;
	212
	213	return 0;
	214	}
	215
	216	static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
	217	{
	218	snd_pcm_set_runtime_buffer(substream, NULL);
	219
	220	return 0;
	221	}
	222
	223	static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
	224	{
	225	struct snd_pcm_runtime *runtime = substream->runtime;
	226	struct tegra_runtime_data *prtd = runtime->private_data;
	227	unsigned long flags;
	228
	229	switch (cmd) {
230	case SNDRV_PCM_TRIGGER_START:
231	prtd->dma_pos = 0;
232	prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
233	prtd->period_index = 0;
234	prtd->dma_req_idx = 0;
235	/* Fall-through */
236	case SNDRV_PCM_TRIGGER_RESUME:
237	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
238	spin_lock_irqsave(&prtd->lock, flags);
239	prtd->running = 1;
240	spin_unlock_irqrestore(&prtd->lock, flags);
241	tegra_pcm_queue_dma(prtd);
242	tegra_pcm_queue_dma(prtd);
243	break;
244	case SNDRV_PCM_TRIGGER_STOP:
245	case SNDRV_PCM_TRIGGER_SUSPEND:
246	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
247	spin_lock_irqsave(&prtd->lock, flags);
248	prtd->running = 0;
249	spin_unlock_irqrestore(&prtd->lock, flags);
250	tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
251	tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
252	break;
253	default:
254	return -EINVAL;
255	}
256
257	return 0;
258	}
259
260	static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
261	{
262	struct snd_pcm_runtime *runtime = substream->runtime;
263	struct tegra_runtime_data *prtd = runtime->private_data;
264
265	return prtd->period_index * runtime->period_size;
266	}
267
268
269	static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
270	struct vm_area_struct *vma)
271	{
272	struct snd_pcm_runtime *runtime = substream->runtime;
273
274	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
275	runtime->dma_area,
276	runtime->dma_addr,
277	runtime->dma_bytes);
278	}
279
280	static struct snd_pcm_ops tegra_pcm_ops = {
281	.open = tegra_pcm_open,
282	.close = tegra_pcm_close,
283	.ioctl = snd_pcm_lib_ioctl,
284	.hw_params = tegra_pcm_hw_params,
285	.hw_free = tegra_pcm_hw_free,
286	.trigger = tegra_pcm_trigger,
287	.pointer = tegra_pcm_pointer,
288	.mmap = tegra_pcm_mmap,
289	};
df79f55d LD	290	#else
	291	static int tegra_pcm_open(struct snd_pcm_substream *substream)
	292	{
	293	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	294	struct device *dev = rtd->platform->dev;
	295	int ret;
	296
	297	/* Set HW params now that initialization is complete */
	298	snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
	299
	300	ret = snd_dmaengine_pcm_open(substream, NULL, NULL);
	301	if (ret) {
	302	dev_err(dev, "dmaengine pcm open failed with err %d\n", ret);
	303	return ret;
	304	}
	305
	306	return 0;
	307	}
	308
	309	static int tegra_pcm_close(struct snd_pcm_substream *substream)
	310	{
	311	snd_dmaengine_pcm_close(substream);
	312	return 0;
	313	}
	314
	315	static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
	316	struct snd_pcm_hw_params *params)
	317	{
	318	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	319	struct device *dev = rtd->platform->dev;
	320	struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
	321	struct tegra_pcm_dma_params *dmap;
	322	struct dma_slave_config slave_config;
	323	int ret;
	324
	325	dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
	326
	327	ret = snd_hwparams_to_dma_slave_config(substream, params,
	328	&slave_config);
	329	if (ret) {
	330	dev_err(dev, "hw params config failed with err %d\n", ret);
	331	return ret;
	332	}
	333
	334	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	335	slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	336	slave_config.dst_addr = dmap->addr;
a32826e4	337	slave_config.dst_maxburst = 4;
df79f55d LD	338	} else {
	339	slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	340	slave_config.src_addr = dmap->addr;
a32826e4	341	slave_config.src_maxburst = 4;
df79f55d LD	342	}
	343	slave_config.slave_id = dmap->req_sel;
	344
	345	ret = dmaengine_slave_config(chan, &slave_config);
	346	if (ret < 0) {
	347	dev_err(dev, "dma slave config failed with err %d\n", ret);
	348	return ret;
	349	}
	350
	351	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
	352	return 0;
	353	}
	354
	355	static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
	356	{
	357	snd_pcm_set_runtime_buffer(substream, NULL);
	358	return 0;
	359	}
	360
	361	static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
	362	{
	363	switch (cmd) {
	364	case SNDRV_PCM_TRIGGER_START:
	365	case SNDRV_PCM_TRIGGER_RESUME:
	366	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	367	return snd_dmaengine_pcm_trigger(substream,
	368	SNDRV_PCM_TRIGGER_START);
	369
	370	case SNDRV_PCM_TRIGGER_STOP:
	371	case SNDRV_PCM_TRIGGER_SUSPEND:
	372	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	373	return snd_dmaengine_pcm_trigger(substream,
	374	SNDRV_PCM_TRIGGER_STOP);
	375	default:
	376	return -EINVAL;
	377	}
	378	return 0;
	379	}
	380
	381	static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
	382	struct vm_area_struct *vma)
	383	{
	384	struct snd_pcm_runtime *runtime = substream->runtime;
	385
	386	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
	387	runtime->dma_area,
	388	runtime->dma_addr,
	389	runtime->dma_bytes);
	390	}
	391
	392	static struct snd_pcm_ops tegra_pcm_ops = {
	393	.open = tegra_pcm_open,
	394	.close = tegra_pcm_close,
	395	.ioctl = snd_pcm_lib_ioctl,
	396	.hw_params = tegra_pcm_hw_params,
	397	.hw_free = tegra_pcm_hw_free,
	398	.trigger = tegra_pcm_trigger,
	399	.pointer = snd_dmaengine_pcm_pointer,
	400	.mmap = tegra_pcm_mmap,
	401	};
	402	#endif
7605eb5b SW	403
	404	static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
	405	{
	406	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
	407	struct snd_dma_buffer *buf = &substream->dma_buffer;
	408	size_t size = tegra_pcm_hardware.buffer_bytes_max;
	409
	410	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
	411	&buf->addr, GFP_KERNEL);
	412	if (!buf->area)
	413	return -ENOMEM;
	414
	415	buf->dev.type = SNDRV_DMA_TYPE_DEV;
	416	buf->dev.dev = pcm->card->dev;
	417	buf->private_data = NULL;
	418	buf->bytes = size;
	419
	420	return 0;
	421	}
	422
	423	static void tegra_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
	424	{
a96edd59 SW	425	struct snd_pcm_substream *substream;
	426	struct snd_dma_buffer *buf;
	427
	428	substream = pcm->streams[stream].substream;
	429	if (!substream)
	430	return;
7605eb5b	431
a96edd59	432	buf = &substream->dma_buffer;
7605eb5b SW	433	if (!buf->area)
	434	return;
	435
	436	dma_free_writecombine(pcm->card->dev, buf->bytes,
	437	buf->area, buf->addr);
	438	buf->area = NULL;
	439	}
	440
	441	static u64 tegra_dma_mask = DMA_BIT_MASK(32);
	442
552d1ef6	443	static int tegra_pcm_new(struct snd_soc_pcm_runtime *rtd)
7605eb5b	444	{
552d1ef6	445	struct snd_card *card = rtd->card->snd_card;
552d1ef6	446	struct snd_pcm *pcm = rtd->pcm;
7605eb5b SW	447	int ret = 0;
	448
	449	if (!card->dev->dma_mask)
	450	card->dev->dma_mask = &tegra_dma_mask;
	451	if (!card->dev->coherent_dma_mask)
350e16d5	452	card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
7605eb5b	453
25e9e756	454	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
7605eb5b SW	455	ret = tegra_pcm_preallocate_dma_buffer(pcm,
	456	SNDRV_PCM_STREAM_PLAYBACK);
	457	if (ret)
	458	goto err;
	459	}
	460
25e9e756	461	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
7605eb5b SW	462	ret = tegra_pcm_preallocate_dma_buffer(pcm,
	463	SNDRV_PCM_STREAM_CAPTURE);
	464	if (ret)
	465	goto err_free_play;
	466	}
	467
	468	return 0;
	469
	470	err_free_play:
	471	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
	472	err:
	473	return ret;
	474	}
	475
	476	static void tegra_pcm_free(struct snd_pcm *pcm)
	477	{
	478	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE);
	479	tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
	480	}
	481
01840bbe	482	static struct snd_soc_platform_driver tegra_pcm_platform = {
7605eb5b SW	483	.ops = &tegra_pcm_ops,
	484	.pcm_new = tegra_pcm_new,
	485	.pcm_free = tegra_pcm_free,
	486	};
	487
518de86b	488	int __devinit tegra_pcm_platform_register(struct device *dev)
7605eb5b	489	{
518de86b	490	return snd_soc_register_platform(dev, &tegra_pcm_platform);
7605eb5b	491	}
518de86b	492	EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
7605eb5b	493
518de86b	494	void __devexit tegra_pcm_platform_unregister(struct device *dev)
7605eb5b	495	{
518de86b	496	snd_soc_unregister_platform(dev);
7605eb5b	497	}
518de86b	498	EXPORT_SYMBOL_GPL(tegra_pcm_platform_unregister);
7605eb5b SW	499
	500	MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
	501	MODULE_DESCRIPTION("Tegra PCM ASoC driver");
	502	MODULE_LICENSE("GPL");