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ASoC: Ux500: Dispose of device nodes correctly
[deliverable/linux.git] / sound / soc / ux500 / ux500_msp_i2s.c
CommitLineData
3592b7f6
OL		 1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
6 * Sandeep Kaushik <sandeep.kaushik@st.com>
7 * for ST-Ericsson.
8 *
9 * License terms:
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
5ca032ee 18#include <linux/pinctrl/consumer.h>
3592b7f6
OL		 19#include <linux/delay.h>
20#include <linux/slab.h>
49731c23 21#include <linux/of.h>
3592b7f6
OL		 22
23#include <mach/hardware.h>
aa50fe55 24#include <mach/msp.h>
3592b7f6
OL		 25
26#include <sound/soc.h>
27
28#include "ux500_msp_i2s.h"
29
5ca032ee
LJ		 30/* MSP1/3 Tx/Rx usage protection */
31static DEFINE_SPINLOCK(msp_rxtx_lock);
32
3592b7f6
OL		 33 /* Protocol desciptors */
34static const struct msp_protdesc prot_descs[] = {
35 { /* I2S */
36 MSP_SINGLE_PHASE,
37 MSP_SINGLE_PHASE,
38 MSP_PHASE2_START_MODE_IMEDIATE,
39 MSP_PHASE2_START_MODE_IMEDIATE,
40 MSP_BTF_MS_BIT_FIRST,
41 MSP_BTF_MS_BIT_FIRST,
42 MSP_FRAME_LEN_1,
43 MSP_FRAME_LEN_1,
44 MSP_FRAME_LEN_1,
45 MSP_FRAME_LEN_1,
46 MSP_ELEM_LEN_32,
47 MSP_ELEM_LEN_32,
48 MSP_ELEM_LEN_32,
49 MSP_ELEM_LEN_32,
50 MSP_DELAY_1,
51 MSP_DELAY_1,
52 MSP_RISING_EDGE,
53 MSP_FALLING_EDGE,
54 MSP_FSYNC_POL_ACT_LO,
55 MSP_FSYNC_POL_ACT_LO,
56 MSP_SWAP_NONE,
57 MSP_SWAP_NONE,
58 MSP_COMPRESS_MODE_LINEAR,
59 MSP_EXPAND_MODE_LINEAR,
60 MSP_FSYNC_IGNORE,
61 31,
62 15,
63 32,
64 }, { /* PCM */
65 MSP_DUAL_PHASE,
66 MSP_DUAL_PHASE,
67 MSP_PHASE2_START_MODE_FSYNC,
68 MSP_PHASE2_START_MODE_FSYNC,
69 MSP_BTF_MS_BIT_FIRST,
70 MSP_BTF_MS_BIT_FIRST,
71 MSP_FRAME_LEN_1,
72 MSP_FRAME_LEN_1,
73 MSP_FRAME_LEN_1,
74 MSP_FRAME_LEN_1,
75 MSP_ELEM_LEN_16,
76 MSP_ELEM_LEN_16,
77 MSP_ELEM_LEN_16,
78 MSP_ELEM_LEN_16,
79 MSP_DELAY_0,
80 MSP_DELAY_0,
81 MSP_RISING_EDGE,
82 MSP_FALLING_EDGE,
83 MSP_FSYNC_POL_ACT_HI,
84 MSP_FSYNC_POL_ACT_HI,
85 MSP_SWAP_NONE,
86 MSP_SWAP_NONE,
87 MSP_COMPRESS_MODE_LINEAR,
88 MSP_EXPAND_MODE_LINEAR,
89 MSP_FSYNC_IGNORE,
90 255,
91 0,
92 256,
93 }, { /* Companded PCM */
94 MSP_SINGLE_PHASE,
95 MSP_SINGLE_PHASE,
96 MSP_PHASE2_START_MODE_FSYNC,
97 MSP_PHASE2_START_MODE_FSYNC,
98 MSP_BTF_MS_BIT_FIRST,
99 MSP_BTF_MS_BIT_FIRST,
100 MSP_FRAME_LEN_1,
101 MSP_FRAME_LEN_1,
102 MSP_FRAME_LEN_1,
103 MSP_FRAME_LEN_1,
104 MSP_ELEM_LEN_8,
105 MSP_ELEM_LEN_8,
106 MSP_ELEM_LEN_8,
107 MSP_ELEM_LEN_8,
108 MSP_DELAY_0,
109 MSP_DELAY_0,
110 MSP_RISING_EDGE,
111 MSP_RISING_EDGE,
112 MSP_FSYNC_POL_ACT_HI,
113 MSP_FSYNC_POL_ACT_HI,
114 MSP_SWAP_NONE,
115 MSP_SWAP_NONE,
116 MSP_COMPRESS_MODE_LINEAR,
117 MSP_EXPAND_MODE_LINEAR,
118 MSP_FSYNC_IGNORE,
119 255,
120 0,
121 256,
122 },
123};
124
125static void set_prot_desc_tx(struct ux500_msp *msp,
126 struct msp_protdesc *protdesc,
127 enum msp_data_size data_size)
128{
129 u32 temp_reg = 0;
130
131 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
132 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
133 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
134 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
135 if (msp->def_elem_len) {
136 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
137 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
138 } else {
139 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
140 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
141 }
142 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
143 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
144 temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
145 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
146 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
147 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
148
149 writel(temp_reg, msp->registers + MSP_TCF);
150}
151
152static void set_prot_desc_rx(struct ux500_msp *msp,
153 struct msp_protdesc *protdesc,
154 enum msp_data_size data_size)
155{
156 u32 temp_reg = 0;
157
158 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
159 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
160 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
161 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
162 if (msp->def_elem_len) {
163 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
164 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
165 } else {
166 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
167 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
168 }
169
170 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
171 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
172 temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
173 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
174 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
175 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
176
177 writel(temp_reg, msp->registers + MSP_RCF);
178}
179
180static int configure_protocol(struct ux500_msp *msp,
181 struct ux500_msp_config *config)
182{
183 struct msp_protdesc *protdesc;
184 enum msp_data_size data_size;
185 u32 temp_reg = 0;
186
187 data_size = config->data_size;
188 msp->def_elem_len = config->def_elem_len;
189 if (config->default_protdesc == 1) {
190 if (config->protocol >= MSP_INVALID_PROTOCOL) {
191 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
192 __func__);
193 return -EINVAL;
194 }
195 protdesc =
196 (struct msp_protdesc *)&prot_descs[config->protocol];
197 } else {
198 protdesc = (struct msp_protdesc *)&config->protdesc;
199 }
200
201 if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
202 dev_err(msp->dev,
203 "%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
204 __func__, data_size);
205 return -EINVAL;
206 }
207
208 if (config->direction & MSP_DIR_TX)
209 set_prot_desc_tx(msp, protdesc, data_size);
210 if (config->direction & MSP_DIR_RX)
211 set_prot_desc_rx(msp, protdesc, data_size);
212
213 /* The code below should not be separated. */
214 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
215 temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
216 writel(temp_reg, msp->registers + MSP_GCR);
217 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
218 temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
219 writel(temp_reg, msp->registers + MSP_GCR);
220
221 return 0;
222}
223
224static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
225{
226 u32 reg_val_GCR;
227 u32 frame_per = 0;
228 u32 sck_div = 0;
229 u32 frame_width = 0;
230 u32 temp_reg = 0;
231 struct msp_protdesc *protdesc = NULL;
232
233 reg_val_GCR = readl(msp->registers + MSP_GCR);
234 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
235
236 if (config->default_protdesc)
237 protdesc =
238 (struct msp_protdesc *)&prot_descs[config->protocol];
239 else
240 protdesc = (struct msp_protdesc *)&config->protdesc;
241
242 switch (config->protocol) {
243 case MSP_PCM_PROTOCOL:
244 case MSP_PCM_COMPAND_PROTOCOL:
245 frame_width = protdesc->frame_width;
246 sck_div = config->f_inputclk / (config->frame_freq *
247 (protdesc->clocks_per_frame));
248 frame_per = protdesc->frame_period;
249 break;
250 case MSP_I2S_PROTOCOL:
251 frame_width = protdesc->frame_width;
252 sck_div = config->f_inputclk / (config->frame_freq *
253 (protdesc->clocks_per_frame));
254 frame_per = protdesc->frame_period;
255 break;
256 default:
257 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
258 __func__,
259 config->protocol);
260 return -EINVAL;
261 }
262
263 temp_reg = (sck_div - 1) & SCK_DIV_MASK;
264 temp_reg |= FRAME_WIDTH_BITS(frame_width);
265 temp_reg |= FRAME_PERIOD_BITS(frame_per);
266 writel(temp_reg, msp->registers + MSP_SRG);
267
268 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
269
270 /* Enable bit-clock */
271 udelay(100);
272 reg_val_GCR = readl(msp->registers + MSP_GCR);
273 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
274 udelay(100);
275
276 return 0;
277}
278
279static int configure_multichannel(struct ux500_msp *msp,
280 struct ux500_msp_config *config)
281{
282 struct msp_protdesc *protdesc;
283 struct msp_multichannel_config *mcfg;
284 u32 reg_val_MCR;
285
286 if (config->default_protdesc == 1) {
287 if (config->protocol >= MSP_INVALID_PROTOCOL) {
288 dev_err(msp->dev,
289 "%s: ERROR: Invalid protocol (%d)!\n",
290 __func__, config->protocol);
291 return -EINVAL;
292 }
293 protdesc = (struct msp_protdesc *)
294 &prot_descs[config->protocol];
295 } else {
296 protdesc = (struct msp_protdesc *)&config->protdesc;
297 }
298
299 mcfg = &config->multichannel_config;
300 if (mcfg->tx_multichannel_enable) {
301 if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
302 reg_val_MCR = readl(msp->registers + MSP_MCR);
303 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
304 1 << TMCEN_BIT : 0),
305 msp->registers + MSP_MCR);
306 writel(mcfg->tx_channel_0_enable,
307 msp->registers + MSP_TCE0);
308 writel(mcfg->tx_channel_1_enable,
309 msp->registers + MSP_TCE1);
310 writel(mcfg->tx_channel_2_enable,
311 msp->registers + MSP_TCE2);
312 writel(mcfg->tx_channel_3_enable,
313 msp->registers + MSP_TCE3);
314 } else {
315 dev_err(msp->dev,
316 "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
317 __func__, protdesc->tx_phase_mode);
318 return -EINVAL;
319 }
320 }
321 if (mcfg->rx_multichannel_enable) {
322 if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
323 reg_val_MCR = readl(msp->registers + MSP_MCR);
324 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
325 1 << RMCEN_BIT : 0),
326 msp->registers + MSP_MCR);
327 writel(mcfg->rx_channel_0_enable,
328 msp->registers + MSP_RCE0);
329 writel(mcfg->rx_channel_1_enable,
330 msp->registers + MSP_RCE1);
331 writel(mcfg->rx_channel_2_enable,
332 msp->registers + MSP_RCE2);
333 writel(mcfg->rx_channel_3_enable,
334 msp->registers + MSP_RCE3);
335 } else {
336 dev_err(msp->dev,
337 "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
338 __func__, protdesc->rx_phase_mode);
339 return -EINVAL;
340 }
341 if (mcfg->rx_comparison_enable_mode) {
342 reg_val_MCR = readl(msp->registers + MSP_MCR);
343 writel(reg_val_MCR |
344 (mcfg->rx_comparison_enable_mode << RCMPM_BIT),
345 msp->registers + MSP_MCR);
346
347 writel(mcfg->comparison_mask,
348 msp->registers + MSP_RCM);
349 writel(mcfg->comparison_value,
350 msp->registers + MSP_RCV);
351
352 }
353 }
354
355 return 0;
356}
357
358static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
359{
5ca032ee 360 int status = 0, retval = 0;
3592b7f6 361 u32 reg_val_DMACR, reg_val_GCR;
5ca032ee 362 unsigned long flags;
3592b7f6
OL		 363
364 /* Check msp state whether in RUN or CONFIGURED Mode */
5ca032ee
LJ		 365 if (msp->msp_state == MSP_STATE_IDLE) {
366 spin_lock_irqsave(&msp_rxtx_lock, flags);
367 if (msp->pinctrl_rxtx_ref == 0 &&
368 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) {
369 retval = pinctrl_select_state(msp->pinctrl_p,
370 msp->pinctrl_def);
371 if (retval)
372 pr_err("could not set MSP defstate\n");
3592b7f6 373 }
5ca032ee
LJ		 374 if (!retval)
375 msp->pinctrl_rxtx_ref++;
376 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
3592b7f6
OL		 377 }
378
379 /* Configure msp with protocol dependent settings */
380 configure_protocol(msp, config);
381 setup_bitclk(msp, config);
382 if (config->multichannel_configured == 1) {
383 status = configure_multichannel(msp, config);
384 if (status)
385 dev_warn(msp->dev,
386 "%s: WARN: configure_multichannel failed (%d)!\n",
387 __func__, status);
388 }
389
390 /* Make sure the correct DMA-directions are configured */
391 if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) {
392 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
393 __func__);
394 return -EINVAL;
395 }
396 if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) {
397 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
398 __func__);
399 return -EINVAL;
400 }
401
402 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
403 if (config->direction & MSP_DIR_RX)
404 reg_val_DMACR |= RX_DMA_ENABLE;
405 if (config->direction & MSP_DIR_TX)
406 reg_val_DMACR |= TX_DMA_ENABLE;
407 writel(reg_val_DMACR, msp->registers + MSP_DMACR);
408
409 writel(config->iodelay, msp->registers + MSP_IODLY);
410
411 /* Enable frame generation logic */
412 reg_val_GCR = readl(msp->registers + MSP_GCR);
413 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
414
415 return status;
416}
417
418static void flush_fifo_rx(struct ux500_msp *msp)
419{
420 u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
421 u32 limit = 32;
422
423 reg_val_GCR = readl(msp->registers + MSP_GCR);
424 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
425
426 reg_val_FLR = readl(msp->registers + MSP_FLR);
427 while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
428 reg_val_DR = readl(msp->registers + MSP_DR);
429 reg_val_FLR = readl(msp->registers + MSP_FLR);
430 }
431
432 writel(reg_val_GCR, msp->registers + MSP_GCR);
433}
434
435static void flush_fifo_tx(struct ux500_msp *msp)
436{
437 u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
438 u32 limit = 32;
439
440 reg_val_GCR = readl(msp->registers + MSP_GCR);
441 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
442 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
443
444 reg_val_FLR = readl(msp->registers + MSP_FLR);
445 while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
446 reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
447 reg_val_FLR = readl(msp->registers + MSP_FLR);
448 }
449 writel(0x0, msp->registers + MSP_ITCR);
450 writel(reg_val_GCR, msp->registers + MSP_GCR);
451}
452
453int ux500_msp_i2s_open(struct ux500_msp *msp,
454 struct ux500_msp_config *config)
455{
456 u32 old_reg, new_reg, mask;
457 int res;
458 unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
459
460 if (in_interrupt()) {
461 dev_err(msp->dev,
462 "%s: ERROR: Open called in interrupt context!\n",
463 __func__);
464 return -1;
465 }
466
467 tx_sel = (config->direction & MSP_DIR_TX) > 0;
468 rx_sel = (config->direction & MSP_DIR_RX) > 0;
469 if (!tx_sel && !rx_sel) {
470 dev_err(msp->dev, "%s: Error: No direction selected!\n",
471 __func__);
472 return -EINVAL;
473 }
474
475 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
476 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
477 if (tx_busy && tx_sel) {
478 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
479 return -EBUSY;
480 }
481 if (rx_busy && rx_sel) {
482 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
483 return -EBUSY;
484 }
485
486 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
487
488 /* First do the global config register */
489 mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
490 TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
491 RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
492 LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
493
494 new_reg = (config->tx_clk_sel | config->rx_clk_sel |
495 config->rx_fsync_pol | config->tx_fsync_pol |
496 config->rx_fsync_sel | config->tx_fsync_sel |
497 config->rx_fifo_config | config->tx_fifo_config |
498 config->srg_clk_sel | config->loopback_enable |
499 config->tx_data_enable);
500
501 old_reg = readl(msp->registers + MSP_GCR);
502 old_reg &= ~mask;
503 new_reg |= old_reg;
504 writel(new_reg, msp->registers + MSP_GCR);
505
506 res = enable_msp(msp, config);
507 if (res < 0) {
508 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
509 __func__, res);
510 return -EBUSY;
511 }
512 if (config->loopback_enable & 0x80)
513 msp->loopback_enable = 1;
514
515 /* Flush FIFOs */
516 flush_fifo_tx(msp);
517 flush_fifo_rx(msp);
518
519 msp->msp_state = MSP_STATE_CONFIGURED;
520 return 0;
521}
522
523static void disable_msp_rx(struct ux500_msp *msp)
524{
525 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
526
527 reg_val_GCR = readl(msp->registers + MSP_GCR);
528 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
529 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
530 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
531 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
532 writel(reg_val_IMSC &
533 ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
534 msp->registers + MSP_IMSC);
535
536 msp->dir_busy &= ~MSP_DIR_RX;
537}
538
539static void disable_msp_tx(struct ux500_msp *msp)
540{
541 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
542
543 reg_val_GCR = readl(msp->registers + MSP_GCR);
544 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
545 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
546 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
547 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
548 writel(reg_val_IMSC &
549 ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
550 msp->registers + MSP_IMSC);
551
552 msp->dir_busy &= ~MSP_DIR_TX;
553}
554
555static int disable_msp(struct ux500_msp *msp, unsigned int dir)
556{
557 u32 reg_val_GCR;
558 int status = 0;
559 unsigned int disable_tx, disable_rx;
560
561 reg_val_GCR = readl(msp->registers + MSP_GCR);
562 disable_tx = dir & MSP_DIR_TX;
563 disable_rx = dir & MSP_DIR_TX;
564 if (disable_tx && disable_rx) {
565 reg_val_GCR = readl(msp->registers + MSP_GCR);
566 writel(reg_val_GCR | LOOPBACK_MASK,
567 msp->registers + MSP_GCR);
568
569 /* Flush TX-FIFO */
570 flush_fifo_tx(msp);
571
572 /* Disable TX-channel */
573 writel((readl(msp->registers + MSP_GCR) &
574 (~TX_ENABLE)), msp->registers + MSP_GCR);
575
576 /* Flush RX-FIFO */
577 flush_fifo_rx(msp);
578
579 /* Disable Loopback and Receive channel */
580 writel((readl(msp->registers + MSP_GCR) &
581 (~(RX_ENABLE | LOOPBACK_MASK))),
582 msp->registers + MSP_GCR);
583
584 disable_msp_tx(msp);
585 disable_msp_rx(msp);
586 } else if (disable_tx)
587 disable_msp_tx(msp);
588 else if (disable_rx)
589 disable_msp_rx(msp);
590
591 return status;
592}
593
594int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
595{
596 u32 reg_val_GCR, enable_bit;
597
598 if (msp->msp_state == MSP_STATE_IDLE) {
599 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
600 __func__);
601 return -EINVAL;
602 }
603
604 switch (cmd) {
605 case SNDRV_PCM_TRIGGER_START:
606 case SNDRV_PCM_TRIGGER_RESUME:
607 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
608 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
609 enable_bit = TX_ENABLE;
610 else
611 enable_bit = RX_ENABLE;
612 reg_val_GCR = readl(msp->registers + MSP_GCR);
613 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
614 break;
615
616 case SNDRV_PCM_TRIGGER_STOP:
617 case SNDRV_PCM_TRIGGER_SUSPEND:
618 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
619 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
620 disable_msp_tx(msp);
621 else
622 disable_msp_rx(msp);
623 break;
624 default:
625 return -EINVAL;
626 break;
627 }
628
629 return 0;
630}
631
632int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
633{
5ca032ee
LJ		 634 int status = 0, retval = 0;
635 unsigned long flags;
3592b7f6
OL		 636
637 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
638
639 status = disable_msp(msp, dir);
640 if (msp->dir_busy == 0) {
641 /* disable sample rate and frame generators */
642 msp->msp_state = MSP_STATE_IDLE;
643 writel((readl(msp->registers + MSP_GCR) &
644 (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
645 msp->registers + MSP_GCR);
5ca032ee
LJ		 646
647 spin_lock_irqsave(&msp_rxtx_lock, flags);
648 WARN_ON(!msp->pinctrl_rxtx_ref);
649 msp->pinctrl_rxtx_ref--;
650 if (msp->pinctrl_rxtx_ref == 0 &&
651 !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) {
652 retval = pinctrl_select_state(msp->pinctrl_p,
653 msp->pinctrl_sleep);
654 if (retval)
655 pr_err("could not set MSP sleepstate\n");
656 }
657 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
658
3592b7f6
OL		 659 writel(0, msp->registers + MSP_GCR);
660 writel(0, msp->registers + MSP_TCF);
661 writel(0, msp->registers + MSP_RCF);
662 writel(0, msp->registers + MSP_DMACR);
663 writel(0, msp->registers + MSP_SRG);
664 writel(0, msp->registers + MSP_MCR);
665 writel(0, msp->registers + MSP_RCM);
666 writel(0, msp->registers + MSP_RCV);
667 writel(0, msp->registers + MSP_TCE0);
668 writel(0, msp->registers + MSP_TCE1);
669 writel(0, msp->registers + MSP_TCE2);
670 writel(0, msp->registers + MSP_TCE3);
671 writel(0, msp->registers + MSP_RCE0);
672 writel(0, msp->registers + MSP_RCE1);
673 writel(0, msp->registers + MSP_RCE2);
674 writel(0, msp->registers + MSP_RCE3);
675 }
676
677 return status;
678
679}
680
681int ux500_msp_i2s_init_msp(struct platform_device *pdev,
682 struct ux500_msp **msp_p,
683 struct msp_i2s_platform_data *platform_data)
684{
3592b7f6
OL		 685 struct resource *res = NULL;
686 struct i2s_controller *i2s_cont;
49731c23 687 struct device_node *np = pdev->dev.of_node;
3592b7f6
OL		 688 struct ux500_msp *msp;
689
3592b7f6
OL		 690 *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
691 msp = *msp_p;
0dcd4742
LJ		 692 if (!msp)
693 return -ENOMEM;
3592b7f6 694
49731c23
LJ		 695 if (np) {
696 if (!platform_data) {
697 platform_data = devm_kzalloc(&pdev->dev,
698 sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
699 if (!platform_data)
700 ret = -ENOMEM;
701 }
702 } else
703 if (!platform_data)
704 ret = -EINVAL;
705
706 if (ret)
707 goto err_res;
708
709 dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
710 pdev->name, platform_data->id);
711
3592b7f6
OL		 712 msp->id = platform_data->id;
713 msp->dev = &pdev->dev;
3592b7f6
OL		 714 msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
715 msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
716
717 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
718 if (res == NULL) {
719 dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
720 __func__);
b18e93a4 721 return -ENOMEM;
3592b7f6
OL		 722 }
723
b18e93a4
JL		 724 msp->registers = devm_ioremap(&pdev->dev, res->start,
725 resource_size(res));
3592b7f6
OL		 726 if (msp->registers == NULL) {
727 dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
b18e93a4 728 return -ENOMEM;
3592b7f6
OL		 729 }
730
731 msp->msp_state = MSP_STATE_IDLE;
732 msp->loopback_enable = 0;
733
734 /* I2S-controller is allocated and added in I2S controller class. */
735 i2s_cont = devm_kzalloc(&pdev->dev, sizeof(*i2s_cont), GFP_KERNEL);
736 if (!i2s_cont) {
737 dev_err(&pdev->dev,
738 "%s: ERROR: Failed to allocate I2S-controller!\n",
739 __func__);
b18e93a4 740 return -ENOMEM;
3592b7f6
OL		 741 }
742 i2s_cont->dev.parent = &pdev->dev;
743 i2s_cont->data = (void *)msp;
744 i2s_cont->id = (s16)msp->id;
745 snprintf(i2s_cont->name, sizeof(i2s_cont->name), "ux500-msp-i2s.%04x",
746 msp->id);
747 dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
748 msp->i2s_cont = i2s_cont;
749
5ca032ee
LJ		 750 msp->pinctrl_p = pinctrl_get(msp->dev);
751 if (IS_ERR(msp->pinctrl_p))
752 dev_err(&pdev->dev, "could not get MSP pinctrl\n");
753 else {
754 msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p,
755 PINCTRL_STATE_DEFAULT);
756 if (IS_ERR(msp->pinctrl_def)) {
757 dev_err(&pdev->dev,
758 "could not get MSP defstate (%li)\n",
759 PTR_ERR(msp->pinctrl_def));
760 }
761 msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p,
762 PINCTRL_STATE_SLEEP);
763 if (IS_ERR(msp->pinctrl_sleep))
764 dev_err(&pdev->dev,
765 "could not get MSP idlestate (%li)\n",
766 PTR_ERR(msp->pinctrl_def));
767 }
768
3592b7f6 769 return 0;
3592b7f6
OL		 770}
771
772void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
773 struct ux500_msp *msp)
774{
775 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
776
777 device_unregister(&msp->i2s_cont->dev);
3592b7f6
OL		 778}
779
85f24391 780MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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