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ASoC: ux500: Ensure consistent configuration between DAIs
[deliverable/linux.git] / sound / soc / ux500 / ux500_msp_i2s.c
CommitLineData
3592b7f6
OL		 1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
6 * Sandeep Kaushik <sandeep.kaushik@st.com>
7 * for ST-Ericsson.
8 *
9 * License terms:
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/slab.h>
05304949 20#include <linux/io.h>
49731c23 21#include <linux/of.h>
ab0fc6ce 22#include <linux/platform_data/asoc-ux500-msp.h>
3592b7f6 23
3592b7f6
OL		 24#include <sound/soc.h>
25
26#include "ux500_msp_i2s.h"
27
28 /* Protocol desciptors */
29static const struct msp_protdesc prot_descs[] = {
30 { /* I2S */
31 MSP_SINGLE_PHASE,
32 MSP_SINGLE_PHASE,
33 MSP_PHASE2_START_MODE_IMEDIATE,
34 MSP_PHASE2_START_MODE_IMEDIATE,
35 MSP_BTF_MS_BIT_FIRST,
36 MSP_BTF_MS_BIT_FIRST,
37 MSP_FRAME_LEN_1,
38 MSP_FRAME_LEN_1,
39 MSP_FRAME_LEN_1,
40 MSP_FRAME_LEN_1,
41 MSP_ELEM_LEN_32,
42 MSP_ELEM_LEN_32,
43 MSP_ELEM_LEN_32,
44 MSP_ELEM_LEN_32,
45 MSP_DELAY_1,
46 MSP_DELAY_1,
47 MSP_RISING_EDGE,
48 MSP_FALLING_EDGE,
49 MSP_FSYNC_POL_ACT_LO,
50 MSP_FSYNC_POL_ACT_LO,
51 MSP_SWAP_NONE,
52 MSP_SWAP_NONE,
53 MSP_COMPRESS_MODE_LINEAR,
54 MSP_EXPAND_MODE_LINEAR,
55 MSP_FSYNC_IGNORE,
56 31,
57 15,
58 32,
59 }, { /* PCM */
60 MSP_DUAL_PHASE,
61 MSP_DUAL_PHASE,
62 MSP_PHASE2_START_MODE_FSYNC,
63 MSP_PHASE2_START_MODE_FSYNC,
64 MSP_BTF_MS_BIT_FIRST,
65 MSP_BTF_MS_BIT_FIRST,
66 MSP_FRAME_LEN_1,
67 MSP_FRAME_LEN_1,
68 MSP_FRAME_LEN_1,
69 MSP_FRAME_LEN_1,
70 MSP_ELEM_LEN_16,
71 MSP_ELEM_LEN_16,
72 MSP_ELEM_LEN_16,
73 MSP_ELEM_LEN_16,
74 MSP_DELAY_0,
75 MSP_DELAY_0,
76 MSP_RISING_EDGE,
77 MSP_FALLING_EDGE,
78 MSP_FSYNC_POL_ACT_HI,
79 MSP_FSYNC_POL_ACT_HI,
80 MSP_SWAP_NONE,
81 MSP_SWAP_NONE,
82 MSP_COMPRESS_MODE_LINEAR,
83 MSP_EXPAND_MODE_LINEAR,
84 MSP_FSYNC_IGNORE,
85 255,
86 0,
87 256,
88 }, { /* Companded PCM */
89 MSP_SINGLE_PHASE,
90 MSP_SINGLE_PHASE,
91 MSP_PHASE2_START_MODE_FSYNC,
92 MSP_PHASE2_START_MODE_FSYNC,
93 MSP_BTF_MS_BIT_FIRST,
94 MSP_BTF_MS_BIT_FIRST,
95 MSP_FRAME_LEN_1,
96 MSP_FRAME_LEN_1,
97 MSP_FRAME_LEN_1,
98 MSP_FRAME_LEN_1,
99 MSP_ELEM_LEN_8,
100 MSP_ELEM_LEN_8,
101 MSP_ELEM_LEN_8,
102 MSP_ELEM_LEN_8,
103 MSP_DELAY_0,
104 MSP_DELAY_0,
105 MSP_RISING_EDGE,
106 MSP_RISING_EDGE,
107 MSP_FSYNC_POL_ACT_HI,
108 MSP_FSYNC_POL_ACT_HI,
109 MSP_SWAP_NONE,
110 MSP_SWAP_NONE,
111 MSP_COMPRESS_MODE_LINEAR,
112 MSP_EXPAND_MODE_LINEAR,
113 MSP_FSYNC_IGNORE,
114 255,
115 0,
116 256,
117 },
118};
119
120static void set_prot_desc_tx(struct ux500_msp *msp,
121 struct msp_protdesc *protdesc,
122 enum msp_data_size data_size)
123{
124 u32 temp_reg = 0;
125
126 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
127 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
128 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
129 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
130 if (msp->def_elem_len) {
131 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
132 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
133 } else {
134 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
135 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
136 }
137 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
138 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
139 temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
140 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
141 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
142 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
143
144 writel(temp_reg, msp->registers + MSP_TCF);
145}
146
147static void set_prot_desc_rx(struct ux500_msp *msp,
148 struct msp_protdesc *protdesc,
149 enum msp_data_size data_size)
150{
151 u32 temp_reg = 0;
152
153 temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
154 temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
155 temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
156 temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
157 if (msp->def_elem_len) {
158 temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
159 temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
160 } else {
161 temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
162 temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
163 }
164
165 temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
166 temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
167 temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
168 temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
169 temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
170 temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
171
172 writel(temp_reg, msp->registers + MSP_RCF);
173}
174
175static int configure_protocol(struct ux500_msp *msp,
176 struct ux500_msp_config *config)
177{
178 struct msp_protdesc *protdesc;
179 enum msp_data_size data_size;
180 u32 temp_reg = 0;
181
182 data_size = config->data_size;
183 msp->def_elem_len = config->def_elem_len;
184 if (config->default_protdesc == 1) {
185 if (config->protocol >= MSP_INVALID_PROTOCOL) {
186 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
187 __func__);
188 return -EINVAL;
189 }
190 protdesc =
191 (struct msp_protdesc *)&prot_descs[config->protocol];
192 } else {
193 protdesc = (struct msp_protdesc *)&config->protdesc;
194 }
195
196 if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
197 dev_err(msp->dev,
198 "%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
199 __func__, data_size);
200 return -EINVAL;
201 }
202
203 if (config->direction & MSP_DIR_TX)
204 set_prot_desc_tx(msp, protdesc, data_size);
205 if (config->direction & MSP_DIR_RX)
206 set_prot_desc_rx(msp, protdesc, data_size);
207
208 /* The code below should not be separated. */
209 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
210 temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
211 writel(temp_reg, msp->registers + MSP_GCR);
212 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
213 temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
214 writel(temp_reg, msp->registers + MSP_GCR);
215
216 return 0;
217}
218
219static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
220{
221 u32 reg_val_GCR;
222 u32 frame_per = 0;
223 u32 sck_div = 0;
224 u32 frame_width = 0;
225 u32 temp_reg = 0;
226 struct msp_protdesc *protdesc = NULL;
227
228 reg_val_GCR = readl(msp->registers + MSP_GCR);
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
230
231 if (config->default_protdesc)
232 protdesc =
233 (struct msp_protdesc *)&prot_descs[config->protocol];
234 else
235 protdesc = (struct msp_protdesc *)&config->protdesc;
236
237 switch (config->protocol) {
238 case MSP_PCM_PROTOCOL:
239 case MSP_PCM_COMPAND_PROTOCOL:
240 frame_width = protdesc->frame_width;
241 sck_div = config->f_inputclk / (config->frame_freq *
242 (protdesc->clocks_per_frame));
243 frame_per = protdesc->frame_period;
244 break;
245 case MSP_I2S_PROTOCOL:
246 frame_width = protdesc->frame_width;
247 sck_div = config->f_inputclk / (config->frame_freq *
248 (protdesc->clocks_per_frame));
249 frame_per = protdesc->frame_period;
250 break;
251 default:
252 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
253 __func__,
254 config->protocol);
255 return -EINVAL;
256 }
257
258 temp_reg = (sck_div - 1) & SCK_DIV_MASK;
259 temp_reg |= FRAME_WIDTH_BITS(frame_width);
260 temp_reg |= FRAME_PERIOD_BITS(frame_per);
261 writel(temp_reg, msp->registers + MSP_SRG);
262
263 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
264
265 /* Enable bit-clock */
266 udelay(100);
267 reg_val_GCR = readl(msp->registers + MSP_GCR);
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
269 udelay(100);
270
271 return 0;
272}
273
274static int configure_multichannel(struct ux500_msp *msp,
275 struct ux500_msp_config *config)
276{
277 struct msp_protdesc *protdesc;
278 struct msp_multichannel_config *mcfg;
279 u32 reg_val_MCR;
280
281 if (config->default_protdesc == 1) {
282 if (config->protocol >= MSP_INVALID_PROTOCOL) {
283 dev_err(msp->dev,
284 "%s: ERROR: Invalid protocol (%d)!\n",
285 __func__, config->protocol);
286 return -EINVAL;
287 }
288 protdesc = (struct msp_protdesc *)
289 &prot_descs[config->protocol];
290 } else {
291 protdesc = (struct msp_protdesc *)&config->protdesc;
292 }
293
294 mcfg = &config->multichannel_config;
295 if (mcfg->tx_multichannel_enable) {
296 if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
297 reg_val_MCR = readl(msp->registers + MSP_MCR);
298 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
299 1 << TMCEN_BIT : 0),
300 msp->registers + MSP_MCR);
301 writel(mcfg->tx_channel_0_enable,
302 msp->registers + MSP_TCE0);
303 writel(mcfg->tx_channel_1_enable,
304 msp->registers + MSP_TCE1);
305 writel(mcfg->tx_channel_2_enable,
306 msp->registers + MSP_TCE2);
307 writel(mcfg->tx_channel_3_enable,
308 msp->registers + MSP_TCE3);
309 } else {
310 dev_err(msp->dev,
311 "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
312 __func__, protdesc->tx_phase_mode);
313 return -EINVAL;
314 }
315 }
316 if (mcfg->rx_multichannel_enable) {
317 if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
318 reg_val_MCR = readl(msp->registers + MSP_MCR);
319 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
320 1 << RMCEN_BIT : 0),
321 msp->registers + MSP_MCR);
322 writel(mcfg->rx_channel_0_enable,
323 msp->registers + MSP_RCE0);
324 writel(mcfg->rx_channel_1_enable,
325 msp->registers + MSP_RCE1);
326 writel(mcfg->rx_channel_2_enable,
327 msp->registers + MSP_RCE2);
328 writel(mcfg->rx_channel_3_enable,
329 msp->registers + MSP_RCE3);
330 } else {
331 dev_err(msp->dev,
332 "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
333 __func__, protdesc->rx_phase_mode);
334 return -EINVAL;
335 }
336 if (mcfg->rx_comparison_enable_mode) {
337 reg_val_MCR = readl(msp->registers + MSP_MCR);
338 writel(reg_val_MCR |
339 (mcfg->rx_comparison_enable_mode << RCMPM_BIT),
340 msp->registers + MSP_MCR);
341
342 writel(mcfg->comparison_mask,
343 msp->registers + MSP_RCM);
344 writel(mcfg->comparison_value,
345 msp->registers + MSP_RCV);
346
347 }
348 }
349
350 return 0;
351}
352
353static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
354{
6ee0b4b0 355 int status = 0;
3592b7f6 356 u32 reg_val_DMACR, reg_val_GCR;
3592b7f6
OL		 357
358 /* Configure msp with protocol dependent settings */
359 configure_protocol(msp, config);
360 setup_bitclk(msp, config);
361 if (config->multichannel_configured == 1) {
362 status = configure_multichannel(msp, config);
363 if (status)
364 dev_warn(msp->dev,
365 "%s: WARN: configure_multichannel failed (%d)!\n",
366 __func__, status);
367 }
368
369 /* Make sure the correct DMA-directions are configured */
370 if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) {
371 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
372 __func__);
373 return -EINVAL;
374 }
375 if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) {
376 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
377 __func__);
378 return -EINVAL;
379 }
380
381 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
382 if (config->direction & MSP_DIR_RX)
383 reg_val_DMACR |= RX_DMA_ENABLE;
384 if (config->direction & MSP_DIR_TX)
385 reg_val_DMACR |= TX_DMA_ENABLE;
386 writel(reg_val_DMACR, msp->registers + MSP_DMACR);
387
388 writel(config->iodelay, msp->registers + MSP_IODLY);
389
390 /* Enable frame generation logic */
391 reg_val_GCR = readl(msp->registers + MSP_GCR);
392 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
393
394 return status;
395}
396
397static void flush_fifo_rx(struct ux500_msp *msp)
398{
399 u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
400 u32 limit = 32;
401
402 reg_val_GCR = readl(msp->registers + MSP_GCR);
403 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
404
405 reg_val_FLR = readl(msp->registers + MSP_FLR);
406 while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
407 reg_val_DR = readl(msp->registers + MSP_DR);
408 reg_val_FLR = readl(msp->registers + MSP_FLR);
409 }
410
411 writel(reg_val_GCR, msp->registers + MSP_GCR);
412}
413
414static void flush_fifo_tx(struct ux500_msp *msp)
415{
416 u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
417 u32 limit = 32;
418
419 reg_val_GCR = readl(msp->registers + MSP_GCR);
420 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
421 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
422
423 reg_val_FLR = readl(msp->registers + MSP_FLR);
424 while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
425 reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
426 reg_val_FLR = readl(msp->registers + MSP_FLR);
427 }
428 writel(0x0, msp->registers + MSP_ITCR);
429 writel(reg_val_GCR, msp->registers + MSP_GCR);
430}
431
432int ux500_msp_i2s_open(struct ux500_msp *msp,
433 struct ux500_msp_config *config)
434{
435 u32 old_reg, new_reg, mask;
436 int res;
437 unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
438
439 if (in_interrupt()) {
440 dev_err(msp->dev,
441 "%s: ERROR: Open called in interrupt context!\n",
442 __func__);
443 return -1;
444 }
445
446 tx_sel = (config->direction & MSP_DIR_TX) > 0;
447 rx_sel = (config->direction & MSP_DIR_RX) > 0;
448 if (!tx_sel && !rx_sel) {
449 dev_err(msp->dev, "%s: Error: No direction selected!\n",
450 __func__);
451 return -EINVAL;
452 }
453
454 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
455 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
456 if (tx_busy && tx_sel) {
457 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
458 return -EBUSY;
459 }
460 if (rx_busy && rx_sel) {
461 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
462 return -EBUSY;
463 }
464
465 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
466
467 /* First do the global config register */
468 mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
469 TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
470 RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
471 LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
472
473 new_reg = (config->tx_clk_sel | config->rx_clk_sel |
474 config->rx_fsync_pol | config->tx_fsync_pol |
475 config->rx_fsync_sel | config->tx_fsync_sel |
476 config->rx_fifo_config | config->tx_fifo_config |
477 config->srg_clk_sel | config->loopback_enable |
478 config->tx_data_enable);
479
480 old_reg = readl(msp->registers + MSP_GCR);
481 old_reg &= ~mask;
482 new_reg |= old_reg;
483 writel(new_reg, msp->registers + MSP_GCR);
484
485 res = enable_msp(msp, config);
486 if (res < 0) {
487 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
488 __func__, res);
489 return -EBUSY;
490 }
491 if (config->loopback_enable & 0x80)
492 msp->loopback_enable = 1;
493
494 /* Flush FIFOs */
495 flush_fifo_tx(msp);
496 flush_fifo_rx(msp);
497
498 msp->msp_state = MSP_STATE_CONFIGURED;
499 return 0;
500}
501
502static void disable_msp_rx(struct ux500_msp *msp)
503{
504 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
505
506 reg_val_GCR = readl(msp->registers + MSP_GCR);
507 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
508 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
509 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
510 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
511 writel(reg_val_IMSC &
512 ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
513 msp->registers + MSP_IMSC);
514
515 msp->dir_busy &= ~MSP_DIR_RX;
516}
517
518static void disable_msp_tx(struct ux500_msp *msp)
519{
520 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
521
522 reg_val_GCR = readl(msp->registers + MSP_GCR);
523 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
524 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
525 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
526 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
527 writel(reg_val_IMSC &
528 ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
529 msp->registers + MSP_IMSC);
530
531 msp->dir_busy &= ~MSP_DIR_TX;
532}
533
534static int disable_msp(struct ux500_msp *msp, unsigned int dir)
535{
536 u32 reg_val_GCR;
537 int status = 0;
538 unsigned int disable_tx, disable_rx;
539
540 reg_val_GCR = readl(msp->registers + MSP_GCR);
541 disable_tx = dir & MSP_DIR_TX;
542 disable_rx = dir & MSP_DIR_TX;
543 if (disable_tx && disable_rx) {
544 reg_val_GCR = readl(msp->registers + MSP_GCR);
545 writel(reg_val_GCR | LOOPBACK_MASK,
546 msp->registers + MSP_GCR);
547
548 /* Flush TX-FIFO */
549 flush_fifo_tx(msp);
550
551 /* Disable TX-channel */
552 writel((readl(msp->registers + MSP_GCR) &
553 (~TX_ENABLE)), msp->registers + MSP_GCR);
554
555 /* Flush RX-FIFO */
556 flush_fifo_rx(msp);
557
558 /* Disable Loopback and Receive channel */
559 writel((readl(msp->registers + MSP_GCR) &
560 (~(RX_ENABLE | LOOPBACK_MASK))),
561 msp->registers + MSP_GCR);
562
563 disable_msp_tx(msp);
564 disable_msp_rx(msp);
565 } else if (disable_tx)
566 disable_msp_tx(msp);
567 else if (disable_rx)
568 disable_msp_rx(msp);
569
570 return status;
571}
572
573int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
574{
575 u32 reg_val_GCR, enable_bit;
576
577 if (msp->msp_state == MSP_STATE_IDLE) {
578 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
579 __func__);
580 return -EINVAL;
581 }
582
583 switch (cmd) {
584 case SNDRV_PCM_TRIGGER_START:
585 case SNDRV_PCM_TRIGGER_RESUME:
586 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
587 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
588 enable_bit = TX_ENABLE;
589 else
590 enable_bit = RX_ENABLE;
591 reg_val_GCR = readl(msp->registers + MSP_GCR);
592 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
593 break;
594
595 case SNDRV_PCM_TRIGGER_STOP:
596 case SNDRV_PCM_TRIGGER_SUSPEND:
597 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
598 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
599 disable_msp_tx(msp);
600 else
601 disable_msp_rx(msp);
602 break;
603 default:
604 return -EINVAL;
605 break;
606 }
607
608 return 0;
609}
610
611int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
612{
6ee0b4b0 613 int status = 0;
3592b7f6
OL		 614
615 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
616
617 status = disable_msp(msp, dir);
618 if (msp->dir_busy == 0) {
619 /* disable sample rate and frame generators */
620 msp->msp_state = MSP_STATE_IDLE;
621 writel((readl(msp->registers + MSP_GCR) &
622 (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
623 msp->registers + MSP_GCR);
5ca032ee 624
3592b7f6
OL		 625 writel(0, msp->registers + MSP_GCR);
626 writel(0, msp->registers + MSP_TCF);
627 writel(0, msp->registers + MSP_RCF);
628 writel(0, msp->registers + MSP_DMACR);
629 writel(0, msp->registers + MSP_SRG);
630 writel(0, msp->registers + MSP_MCR);
631 writel(0, msp->registers + MSP_RCM);
632 writel(0, msp->registers + MSP_RCV);
633 writel(0, msp->registers + MSP_TCE0);
634 writel(0, msp->registers + MSP_TCE1);
635 writel(0, msp->registers + MSP_TCE2);
636 writel(0, msp->registers + MSP_TCE3);
637 writel(0, msp->registers + MSP_RCE0);
638 writel(0, msp->registers + MSP_RCE1);
639 writel(0, msp->registers + MSP_RCE2);
640 writel(0, msp->registers + MSP_RCE3);
641 }
642
643 return status;
644
645}
646
647int ux500_msp_i2s_init_msp(struct platform_device *pdev,
648 struct ux500_msp **msp_p,
649 struct msp_i2s_platform_data *platform_data)
650{
3592b7f6 651 struct resource *res = NULL;
49731c23 652 struct device_node *np = pdev->dev.of_node;
3592b7f6
OL		 653 struct ux500_msp *msp;
654
3592b7f6
OL		 655 *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
656 msp = *msp_p;
0dcd4742
LJ		 657 if (!msp)
658 return -ENOMEM;
3592b7f6 659
49731c23
LJ		 660 if (np) {
661 if (!platform_data) {
662 platform_data = devm_kzalloc(&pdev->dev,
663 sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
664 if (!platform_data)
05304949 665 return -ENOMEM;
49731c23
LJ		 666 }
667 } else
668 if (!platform_data)
05304949 669 return -EINVAL;
49731c23
LJ		 670
671 dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
672 pdev->name, platform_data->id);
673
3592b7f6
OL		 674 msp->id = platform_data->id;
675 msp->dev = &pdev->dev;
3592b7f6
OL		 676 msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
677 msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
678
679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
680 if (res == NULL) {
681 dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
682 __func__);
b18e93a4 683 return -ENOMEM;
3592b7f6
OL		 684 }
685
b18e93a4
JL		 686 msp->registers = devm_ioremap(&pdev->dev, res->start,
687 resource_size(res));
3592b7f6
OL		 688 if (msp->registers == NULL) {
689 dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
b18e93a4 690 return -ENOMEM;
3592b7f6
OL		 691 }
692
693 msp->msp_state = MSP_STATE_IDLE;
694 msp->loopback_enable = 0;
695
3592b7f6 696 return 0;
3592b7f6
OL		 697}
698
699void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
700 struct ux500_msp *msp)
701{
702 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
3592b7f6
OL		 703}
704
85f24391 705MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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