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[CG6]: fix memory size detection
[deliverable/linux.git] / sound / sparc / cs4231.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for CS4231 sound chips found on Sparcs.
3 * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4 *
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
7 * and also sound/isa/cs423x/cs4231_lib.c which is:
8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/moduleparam.h>
18
19#include <sound/driver.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/info.h>
23#include <sound/control.h>
24#include <sound/timer.h>
25#include <sound/initval.h>
26#include <sound/pcm_params.h>
27
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#ifdef CONFIG_SBUS
32#define SBUS_SUPPORT
33#endif
34
35#ifdef SBUS_SUPPORT
36#include <asm/sbus.h>
37#endif
38
39#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
40#define EBUS_SUPPORT
41#endif
42
43#ifdef EBUS_SUPPORT
44#include <linux/pci.h>
45#include <asm/ebus.h>
46#endif
47
48static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
51
52module_param_array(index, int, NULL, 0444);
53MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
54module_param_array(id, charp, NULL, 0444);
55MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
56module_param_array(enable, bool, NULL, 0444);
57MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
58MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
59MODULE_DESCRIPTION("Sun CS4231");
60MODULE_LICENSE("GPL");
61MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
62
5a820fa7 63#ifdef SBUS_SUPPORT
be9b7e8c 64struct sbus_dma_info {
5a820fa7
GC		 65 spinlock_t lock;
66 int dir;
67 void __iomem *regs;
be9b7e8c 68};
5a820fa7
GC		 69#endif
70
4f3f2f6f 71struct snd_cs4231;
be9b7e8c 72struct cs4231_dma_control {
b128254f
GC		 73 void (*prepare)(struct cs4231_dma_control *dma_cont, int dir);
74 void (*enable)(struct cs4231_dma_control *dma_cont, int on);
75 int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len);
76 unsigned int (*address)(struct cs4231_dma_control *dma_cont);
be9b7e8c 77 void (*reset)(struct snd_cs4231 *chip);
4f3f2f6f 78 void (*preallocate)(struct snd_cs4231 *chip, struct snd_pcm *pcm);
1da177e4 79#ifdef EBUS_SUPPORT
b128254f 80 struct ebus_dma_info ebus_info;
1da177e4 81#endif
5a820fa7 82#ifdef SBUS_SUPPORT
b128254f 83 struct sbus_dma_info sbus_info;
5a820fa7 84#endif
be9b7e8c 85};
b128254f
GC		 86
87struct snd_cs4231 {
88 spinlock_t lock;
89 void __iomem *port;
90
be9b7e8c
TI		 91 struct cs4231_dma_control p_dma;
92 struct cs4231_dma_control c_dma;
5a820fa7 93
1da177e4
LT		 94 u32 flags;
95#define CS4231_FLAG_EBUS 0x00000001
96#define CS4231_FLAG_PLAYBACK 0x00000002
97#define CS4231_FLAG_CAPTURE 0x00000004
98
be9b7e8c
TI		 99 struct snd_card *card;
100 struct snd_pcm *pcm;
101 struct snd_pcm_substream *playback_substream;
1da177e4 102 unsigned int p_periods_sent;
be9b7e8c 103 struct snd_pcm_substream *capture_substream;
1da177e4 104 unsigned int c_periods_sent;
be9b7e8c 105 struct snd_timer *timer;
1da177e4
LT		 106
107 unsigned short mode;
108#define CS4231_MODE_NONE 0x0000
109#define CS4231_MODE_PLAY 0x0001
110#define CS4231_MODE_RECORD 0x0002
111#define CS4231_MODE_TIMER 0x0004
112#define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
113
114 unsigned char image[32]; /* registers image */
115 int mce_bit;
116 int calibrate_mute;
12aa7579
IM		 117 struct mutex mce_mutex;
118 struct mutex open_mutex;
1da177e4
LT		 119
120 union {
121#ifdef SBUS_SUPPORT
122 struct sbus_dev *sdev;
123#endif
124#ifdef EBUS_SUPPORT
125 struct pci_dev *pdev;
126#endif
127 } dev_u;
128 unsigned int irq[2];
129 unsigned int regs_size;
130 struct snd_cs4231 *next;
b128254f 131};
1da177e4 132
be9b7e8c 133static struct snd_cs4231 *cs4231_list;
1da177e4
LT		 134
135/* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
136 * now.... -DaveM
137 */
138
139/* IO ports */
140
141#define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
142
143/* XXX offsets are different than PC ISA chips... */
144#define c_d_c_CS4231REGSEL 0x0
145#define c_d_c_CS4231REG 0x4
146#define c_d_c_CS4231STATUS 0x8
147#define c_d_c_CS4231PIO 0xc
148
149/* codec registers */
150
151#define CS4231_LEFT_INPUT 0x00 /* left input control */
152#define CS4231_RIGHT_INPUT 0x01 /* right input control */
153#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
154#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
155#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
156#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
157#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
158#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
159#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
160#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
161#define CS4231_PIN_CTRL 0x0a /* pin control */
162#define CS4231_TEST_INIT 0x0b /* test and initialization */
163#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
164#define CS4231_LOOPBACK 0x0d /* loopback control */
165#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
166#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
167#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
168#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
169#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
170#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
171#define CS4231_TIMER_LOW 0x14 /* timer low byte */
172#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
173#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
174#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
175#define CS4236_EXT_REG 0x17 /* extended register access */
176#define CS4231_IRQ_STATUS 0x18 /* irq status register */
177#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
178#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
179#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
180#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
181#define CS4235_LEFT_MASTER 0x1b /* left master output control */
182#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
183#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
184#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
185#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
186#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
187
188/* definitions for codec register select port - CODECP( REGSEL ) */
189
190#define CS4231_INIT 0x80 /* CODEC is initializing */
191#define CS4231_MCE 0x40 /* mode change enable */
192#define CS4231_TRD 0x20 /* transfer request disable */
193
194/* definitions for codec status register - CODECP( STATUS ) */
195
196#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
197
a131430c 198/* definitions for codec irq status - CS4231_IRQ_STATUS */
1da177e4
LT		 199
200#define CS4231_PLAYBACK_IRQ 0x10
201#define CS4231_RECORD_IRQ 0x20
202#define CS4231_TIMER_IRQ 0x40
203#define CS4231_ALL_IRQS 0x70
204#define CS4231_REC_UNDERRUN 0x08
205#define CS4231_REC_OVERRUN 0x04
206#define CS4231_PLY_OVERRUN 0x02
207#define CS4231_PLY_UNDERRUN 0x01
208
209/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
210
211#define CS4231_ENABLE_MIC_GAIN 0x20
212
213#define CS4231_MIXS_LINE 0x00
214#define CS4231_MIXS_AUX1 0x40
215#define CS4231_MIXS_MIC 0x80
216#define CS4231_MIXS_ALL 0xc0
217
218/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
219
220#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
221#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
222#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
223#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
224#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
225#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
226#define CS4231_STEREO 0x10 /* stereo mode */
227/* bits 3-1 define frequency divisor */
228#define CS4231_XTAL1 0x00 /* 24.576 crystal */
229#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
230
231/* definitions for interface control register - CS4231_IFACE_CTRL */
232
233#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
234#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
235#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
236#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
237#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
238#define CS4231_RECORD_ENABLE 0x02 /* record enable */
239#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
240
241/* definitions for pin control register - CS4231_PIN_CTRL */
242
243#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
244#define CS4231_XCTL1 0x40 /* external control #1 */
245#define CS4231_XCTL0 0x80 /* external control #0 */
246
247/* definitions for test and init register - CS4231_TEST_INIT */
248
249#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
250#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
251
252/* definitions for misc control register - CS4231_MISC_INFO */
253
254#define CS4231_MODE2 0x40 /* MODE 2 */
255#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
256#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
257
258/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
259
260#define CS4231_DACZ 0x01 /* zero DAC when underrun */
261#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
262#define CS4231_OLB 0x80 /* output level bit */
263
264/* SBUS DMA register defines. */
265
266#define APCCSR 0x10UL /* APC DMA CSR */
267#define APCCVA 0x20UL /* APC Capture DMA Address */
268#define APCCC 0x24UL /* APC Capture Count */
269#define APCCNVA 0x28UL /* APC Capture DMA Next Address */
270#define APCCNC 0x2cUL /* APC Capture Next Count */
271#define APCPVA 0x30UL /* APC Play DMA Address */
272#define APCPC 0x34UL /* APC Play Count */
273#define APCPNVA 0x38UL /* APC Play DMA Next Address */
274#define APCPNC 0x3cUL /* APC Play Next Count */
275
5a820fa7
GC		 276/* Defines for SBUS DMA-routines */
277
278#define APCVA 0x0UL /* APC DMA Address */
279#define APCC 0x4UL /* APC Count */
280#define APCNVA 0x8UL /* APC DMA Next Address */
281#define APCNC 0xcUL /* APC Next Count */
282#define APC_PLAY 0x30UL /* Play registers start at 0x30 */
283#define APC_RECORD 0x20UL /* Record registers start at 0x20 */
284
1da177e4
LT		 285/* APCCSR bits */
286
287#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
288#define APC_PLAY_INT 0x400000 /* Playback interrupt */
289#define APC_CAPT_INT 0x200000 /* Capture interrupt */
290#define APC_GENL_INT 0x100000 /* General interrupt */
291#define APC_XINT_ENA 0x80000 /* General ext int. enable */
292#define APC_XINT_PLAY 0x40000 /* Playback ext intr */
293#define APC_XINT_CAPT 0x20000 /* Capture ext intr */
294#define APC_XINT_GENL 0x10000 /* Error ext intr */
295#define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
296#define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
297#define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
298#define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
299#define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
300#define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
301#define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
302#define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
303#define APC_PPAUSE 0x80 /* Pause the play DMA */
304#define APC_CPAUSE 0x40 /* Pause the capture DMA */
305#define APC_CDC_RESET 0x20 /* CODEC RESET */
306#define APC_PDMA_READY 0x08 /* Play DMA Go */
307#define APC_CDMA_READY 0x04 /* Capture DMA Go */
308#define APC_CHIP_RESET 0x01 /* Reset the chip */
309
310/* EBUS DMA register offsets */
311
312#define EBDMA_CSR 0x00UL /* Control/Status */
313#define EBDMA_ADDR 0x04UL /* DMA Address */
314#define EBDMA_COUNT 0x08UL /* DMA Count */
315
316/*
317 * Some variables
318 */
319
320static unsigned char freq_bits[14] = {
321 /* 5510 */ 0x00 | CS4231_XTAL2,
322 /* 6620 */ 0x0E | CS4231_XTAL2,
323 /* 8000 */ 0x00 | CS4231_XTAL1,
324 /* 9600 */ 0x0E | CS4231_XTAL1,
325 /* 11025 */ 0x02 | CS4231_XTAL2,
326 /* 16000 */ 0x02 | CS4231_XTAL1,
327 /* 18900 */ 0x04 | CS4231_XTAL2,
328 /* 22050 */ 0x06 | CS4231_XTAL2,
329 /* 27042 */ 0x04 | CS4231_XTAL1,
330 /* 32000 */ 0x06 | CS4231_XTAL1,
331 /* 33075 */ 0x0C | CS4231_XTAL2,
332 /* 37800 */ 0x08 | CS4231_XTAL2,
333 /* 44100 */ 0x0A | CS4231_XTAL2,
334 /* 48000 */ 0x0C | CS4231_XTAL1
335};
336
337static unsigned int rates[14] = {
338 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
339 27042, 32000, 33075, 37800, 44100, 48000
340};
341
be9b7e8c 342static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 343 .count = 14,
344 .list = rates,
345};
346
be9b7e8c 347static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
1da177e4
LT		 348{
349 return snd_pcm_hw_constraint_list(runtime, 0,
350 SNDRV_PCM_HW_PARAM_RATE,
351 &hw_constraints_rates);
352}
353
354static unsigned char snd_cs4231_original_image[32] =
355{
356 0x00, /* 00/00 - lic */
357 0x00, /* 01/01 - ric */
358 0x9f, /* 02/02 - la1ic */
359 0x9f, /* 03/03 - ra1ic */
360 0x9f, /* 04/04 - la2ic */
361 0x9f, /* 05/05 - ra2ic */
362 0xbf, /* 06/06 - loc */
363 0xbf, /* 07/07 - roc */
364 0x20, /* 08/08 - pdfr */
365 CS4231_AUTOCALIB, /* 09/09 - ic */
366 0x00, /* 0a/10 - pc */
367 0x00, /* 0b/11 - ti */
368 CS4231_MODE2, /* 0c/12 - mi */
369 0x00, /* 0d/13 - lbc */
370 0x00, /* 0e/14 - pbru */
371 0x00, /* 0f/15 - pbrl */
372 0x80, /* 10/16 - afei */
373 0x01, /* 11/17 - afeii */
374 0x9f, /* 12/18 - llic */
375 0x9f, /* 13/19 - rlic */
376 0x00, /* 14/20 - tlb */
377 0x00, /* 15/21 - thb */
378 0x00, /* 16/22 - la3mic/reserved */
379 0x00, /* 17/23 - ra3mic/reserved */
380 0x00, /* 18/24 - afs */
381 0x00, /* 19/25 - lamoc/version */
382 0x00, /* 1a/26 - mioc */
383 0x00, /* 1b/27 - ramoc/reserved */
384 0x20, /* 1c/28 - cdfr */
385 0x00, /* 1d/29 - res4 */
386 0x00, /* 1e/30 - cbru */
387 0x00, /* 1f/31 - cbrl */
388};
389
be9b7e8c 390static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
1da177e4
LT		 391{
392#ifdef EBUS_SUPPORT
393 if (cp->flags & CS4231_FLAG_EBUS) {
394 return readb(reg_addr);
395 } else {
396#endif
397#ifdef SBUS_SUPPORT
398 return sbus_readb(reg_addr);
399#endif
400#ifdef EBUS_SUPPORT
401 }
402#endif
403}
404
be9b7e8c 405static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, void __iomem *reg_addr)
1da177e4
LT		 406{
407#ifdef EBUS_SUPPORT
408 if (cp->flags & CS4231_FLAG_EBUS) {
409 return writeb(val, reg_addr);
410 } else {
411#endif
412#ifdef SBUS_SUPPORT
413 return sbus_writeb(val, reg_addr);
414#endif
415#ifdef EBUS_SUPPORT
416 }
417#endif
418}
419
420/*
421 * Basic I/O functions
422 */
423
be9b7e8c 424static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
1da177e4
LT		 425 unsigned char mask, unsigned char value)
426{
427 int timeout;
428 unsigned char tmp;
429
430 for (timeout = 250;
431 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
432 timeout--)
433 udelay(100);
434#ifdef CONFIG_SND_DEBUG
435 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 436 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
1da177e4
LT		 437#endif
438 if (chip->calibrate_mute) {
439 chip->image[reg] &= mask;
440 chip->image[reg] |= value;
441 } else {
442 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
443 mb();
444 tmp = (chip->image[reg] & mask) | value;
445 __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
446 chip->image[reg] = tmp;
447 mb();
448 }
449}
450
be9b7e8c 451static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
1da177e4
LT		 452{
453 int timeout;
454
455 for (timeout = 250;
456 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
457 timeout--)
458 udelay(100);
a131430c
CZ		 459#ifdef CONFIG_SND_DEBUG
460 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
461 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
462#endif
1da177e4
LT		 463 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
464 __cs4231_writeb(chip, value, CS4231P(chip, REG));
465 mb();
466}
467
be9b7e8c 468static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
1da177e4
LT		 469{
470 int timeout;
471
472 for (timeout = 250;
473 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
474 timeout--)
475 udelay(100);
476#ifdef CONFIG_SND_DEBUG
477 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 478 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
1da177e4
LT		 479#endif
480 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
481 __cs4231_writeb(chip, value, CS4231P(chip, REG));
482 chip->image[reg] = value;
483 mb();
1da177e4
LT		 484}
485
be9b7e8c 486static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
1da177e4
LT		 487{
488 int timeout;
489 unsigned char ret;
490
491 for (timeout = 250;
492 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
493 timeout--)
494 udelay(100);
495#ifdef CONFIG_SND_DEBUG
496 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 497 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg);
1da177e4
LT		 498#endif
499 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
500 mb();
501 ret = __cs4231_readb(chip, CS4231P(chip, REG));
1da177e4
LT		 502 return ret;
503}
504
1da177e4
LT		 505/*
506 * CS4231 detection / MCE routines
507 */
508
be9b7e8c 509static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
1da177e4
LT		 510{
511 int timeout;
512
513 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
514 for (timeout = 5; timeout > 0; timeout--)
515 __cs4231_readb(chip, CS4231P(chip, REGSEL));
a131430c 516
1da177e4 517 /* end of cleanup sequence */
a131430c 518 for (timeout = 500;
1da177e4
LT		 519 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
520 timeout--)
a131430c 521 udelay(1000);
1da177e4
LT		 522}
523
be9b7e8c 524static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
1da177e4
LT		 525{
526 unsigned long flags;
527 int timeout;
528
529 spin_lock_irqsave(&chip->lock, flags);
530 for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
531 udelay(100);
532#ifdef CONFIG_SND_DEBUG
533 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 534 snd_printdd("mce_up - auto calibration time out (0)\n");
1da177e4
LT		 535#endif
536 chip->mce_bit |= CS4231_MCE;
537 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
538 if (timeout == 0x80)
a131430c 539 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
1da177e4
LT		 540 if (!(timeout & CS4231_MCE))
541 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
542 spin_unlock_irqrestore(&chip->lock, flags);
543}
544
be9b7e8c 545static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
1da177e4
LT		 546{
547 unsigned long flags;
548 int timeout;
549
550 spin_lock_irqsave(&chip->lock, flags);
551 snd_cs4231_busy_wait(chip);
1da177e4
LT		 552#ifdef CONFIG_SND_DEBUG
553 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
a131430c 554 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
1da177e4
LT		 555#endif
556 chip->mce_bit &= ~CS4231_MCE;
557 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
558 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
559 if (timeout == 0x80)
a131430c 560 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
1da177e4
LT		 561 if ((timeout & CS4231_MCE) == 0) {
562 spin_unlock_irqrestore(&chip->lock, flags);
563 return;
564 }
565 snd_cs4231_busy_wait(chip);
566
567 /* calibration process */
568
569 for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
570 udelay(100);
571 if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
572 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
573 spin_unlock_irqrestore(&chip->lock, flags);
574 return;
575 }
a131430c 576
1da177e4
LT		 577 /* in 10ms increments, check condition, up to 250ms */
578 timeout = 25;
579 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
580 spin_unlock_irqrestore(&chip->lock, flags);
581 if (--timeout < 0) {
582 snd_printk("mce_down - auto calibration time out (2)\n");
583 return;
584 }
585 msleep(10);
586 spin_lock_irqsave(&chip->lock, flags);
587 }
a131430c 588
1da177e4
LT		 589 /* in 10ms increments, check condition, up to 100ms */
590 timeout = 10;
591 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
592 spin_unlock_irqrestore(&chip->lock, flags);
593 if (--timeout < 0) {
594 snd_printk("mce_down - auto calibration time out (3)\n");
595 return;
596 }
597 msleep(10);
598 spin_lock_irqsave(&chip->lock, flags);
599 }
600 spin_unlock_irqrestore(&chip->lock, flags);
1da177e4
LT		 601}
602
be9b7e8c
TI		 603static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
604 struct snd_pcm_substream *substream,
605 unsigned int *periods_sent)
1da177e4 606{
be9b7e8c 607 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 608
609 while (1) {
a131430c
CZ		 610 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
611 unsigned int offset = period_size * (*periods_sent);
1da177e4 612
817dd6ee 613 BUG_ON(period_size >= (1 << 24));
1da177e4 614
b128254f 615 if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size))
1da177e4 616 return;
1da177e4
LT		 617 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
618 }
619}
a131430c 620
be9b7e8c
TI		 621static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
622 unsigned int what, int on)
1da177e4 623{
be9b7e8c
TI		 624 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
625 struct cs4231_dma_control *dma_cont;
a131430c 626
5a820fa7 627 if (what & CS4231_PLAYBACK_ENABLE) {
b128254f 628 dma_cont = &chip->p_dma;
a131430c 629 if (on) {
b128254f
GC		 630 dma_cont->prepare(dma_cont, 0);
631 dma_cont->enable(dma_cont, 1);
632 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 633 chip->playback_substream,
634 &chip->p_periods_sent);
a131430c 635 } else {
b128254f 636 dma_cont->enable(dma_cont, 0);
a131430c 637 }
5a820fa7
GC		 638 }
639 if (what & CS4231_RECORD_ENABLE) {
b128254f 640 dma_cont = &chip->c_dma;
a131430c 641 if (on) {
b128254f
GC		 642 dma_cont->prepare(dma_cont, 1);
643 dma_cont->enable(dma_cont, 1);
644 snd_cs4231_advance_dma(dma_cont,
5a820fa7
GC		 645 chip->capture_substream,
646 &chip->c_periods_sent);
a131430c 647 } else {
b128254f 648 dma_cont->enable(dma_cont, 0);
a131430c 649 }
a131430c 650 }
1da177e4
LT		 651}
652
be9b7e8c 653static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 654{
be9b7e8c 655 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 656 int result = 0;
657
658 switch (cmd) {
659 case SNDRV_PCM_TRIGGER_START:
660 case SNDRV_PCM_TRIGGER_STOP:
661 {
662 unsigned int what = 0;
be9b7e8c 663 struct snd_pcm_substream *s;
1da177e4
LT		 664 unsigned long flags;
665
ef991b95 666 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 667 if (s == chip->playback_substream) {
668 what |= CS4231_PLAYBACK_ENABLE;
669 snd_pcm_trigger_done(s, substream);
670 } else if (s == chip->capture_substream) {
671 what |= CS4231_RECORD_ENABLE;
672 snd_pcm_trigger_done(s, substream);
673 }
674 }
675
1da177e4
LT		 676 spin_lock_irqsave(&chip->lock, flags);
677 if (cmd == SNDRV_PCM_TRIGGER_START) {
a131430c 678 cs4231_dma_trigger(substream, what, 1);
1da177e4 679 chip->image[CS4231_IFACE_CTRL] |= what;
1da177e4 680 } else {
a131430c 681 cs4231_dma_trigger(substream, what, 0);
1da177e4
LT		 682 chip->image[CS4231_IFACE_CTRL] &= ~what;
683 }
684 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
685 chip->image[CS4231_IFACE_CTRL]);
686 spin_unlock_irqrestore(&chip->lock, flags);
687 break;
688 }
689 default:
690 result = -EINVAL;
691 break;
692 }
a131430c 693
1da177e4
LT		 694 return result;
695}
696
697/*
698 * CODEC I/O
699 */
700
701static unsigned char snd_cs4231_get_rate(unsigned int rate)
702{
703 int i;
704
705 for (i = 0; i < 14; i++)
706 if (rate == rates[i])
707 return freq_bits[i];
708 // snd_BUG();
709 return freq_bits[13];
710}
711
be9b7e8c 712static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, int channels)
1da177e4
LT		 713{
714 unsigned char rformat;
715
716 rformat = CS4231_LINEAR_8;
717 switch (format) {
718 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
719 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
720 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
721 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
722 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
723 }
724 if (channels > 1)
725 rformat |= CS4231_STEREO;
1da177e4
LT		 726 return rformat;
727}
728
be9b7e8c 729static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
1da177e4
LT		 730{
731 unsigned long flags;
732
733 mute = mute ? 1 : 0;
734 spin_lock_irqsave(&chip->lock, flags);
735 if (chip->calibrate_mute == mute) {
736 spin_unlock_irqrestore(&chip->lock, flags);
737 return;
738 }
739 if (!mute) {
740 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
741 chip->image[CS4231_LEFT_INPUT]);
742 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
743 chip->image[CS4231_RIGHT_INPUT]);
744 snd_cs4231_dout(chip, CS4231_LOOPBACK,
745 chip->image[CS4231_LOOPBACK]);
746 }
747 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
748 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
749 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
750 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
751 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
752 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
753 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
754 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
755 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
756 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
757 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
758 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
759 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
760 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
761 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
762 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
763 snd_cs4231_dout(chip, CS4231_MONO_CTRL,
764 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
765 chip->calibrate_mute = mute;
766 spin_unlock_irqrestore(&chip->lock, flags);
767}
768
be9b7e8c 769static void snd_cs4231_playback_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
1da177e4
LT		 770 unsigned char pdfr)
771{
772 unsigned long flags;
773
12aa7579 774 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 775 snd_cs4231_calibrate_mute(chip, 1);
776
777 snd_cs4231_mce_up(chip);
778
779 spin_lock_irqsave(&chip->lock, flags);
780 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
781 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
782 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
783 pdfr);
784 spin_unlock_irqrestore(&chip->lock, flags);
785
786 snd_cs4231_mce_down(chip);
787
788 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 789 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 790}
791
be9b7e8c 792static void snd_cs4231_capture_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
1da177e4
LT		 793 unsigned char cdfr)
794{
795 unsigned long flags;
796
12aa7579 797 mutex_lock(&chip->mce_mutex);
1da177e4
LT		 798 snd_cs4231_calibrate_mute(chip, 1);
799
800 snd_cs4231_mce_up(chip);
801
802 spin_lock_irqsave(&chip->lock, flags);
803 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
804 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
805 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
806 (cdfr & 0x0f));
807 spin_unlock_irqrestore(&chip->lock, flags);
808 snd_cs4231_mce_down(chip);
809 snd_cs4231_mce_up(chip);
810 spin_lock_irqsave(&chip->lock, flags);
811 }
812 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
813 spin_unlock_irqrestore(&chip->lock, flags);
814
815 snd_cs4231_mce_down(chip);
816
817 snd_cs4231_calibrate_mute(chip, 0);
12aa7579 818 mutex_unlock(&chip->mce_mutex);
1da177e4
LT		 819}
820
821/*
822 * Timer interface
823 */
824
be9b7e8c 825static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
1da177e4 826{
be9b7e8c 827 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 828
829 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
830}
831
be9b7e8c 832static int snd_cs4231_timer_start(struct snd_timer *timer)
1da177e4
LT		 833{
834 unsigned long flags;
835 unsigned int ticks;
be9b7e8c 836 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 837
838 spin_lock_irqsave(&chip->lock, flags);
839 ticks = timer->sticks;
840 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
841 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
842 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
843 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
844 chip->image[CS4231_TIMER_HIGH] =
845 (unsigned char) (ticks >> 8));
846 snd_cs4231_out(chip, CS4231_TIMER_LOW,
847 chip->image[CS4231_TIMER_LOW] =
848 (unsigned char) ticks);
849 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
850 chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
851 }
852 spin_unlock_irqrestore(&chip->lock, flags);
853
854 return 0;
855}
856
be9b7e8c 857static int snd_cs4231_timer_stop(struct snd_timer *timer)
1da177e4
LT		 858{
859 unsigned long flags;
be9b7e8c 860 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 861
862 spin_lock_irqsave(&chip->lock, flags);
863 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
864 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
865 spin_unlock_irqrestore(&chip->lock, flags);
866
867 return 0;
868}
869
be9b7e8c 870static void __init snd_cs4231_init(struct snd_cs4231 *chip)
1da177e4
LT		 871{
872 unsigned long flags;
873
874 snd_cs4231_mce_down(chip);
875
876#ifdef SNDRV_DEBUG_MCE
a131430c 877 snd_printdd("init: (1)\n");
1da177e4
LT		 878#endif
879 snd_cs4231_mce_up(chip);
880 spin_lock_irqsave(&chip->lock, flags);
881 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
882 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
883 CS4231_CALIB_MODE);
884 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
885 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
886 spin_unlock_irqrestore(&chip->lock, flags);
887 snd_cs4231_mce_down(chip);
888
889#ifdef SNDRV_DEBUG_MCE
a131430c 890 snd_printdd("init: (2)\n");
1da177e4
LT		 891#endif
892
893 snd_cs4231_mce_up(chip);
894 spin_lock_irqsave(&chip->lock, flags);
895 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
896 spin_unlock_irqrestore(&chip->lock, flags);
897 snd_cs4231_mce_down(chip);
898
899#ifdef SNDRV_DEBUG_MCE
a131430c 900 snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
1da177e4
LT		 901#endif
902
903 spin_lock_irqsave(&chip->lock, flags);
904 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
905 spin_unlock_irqrestore(&chip->lock, flags);
906
907 snd_cs4231_mce_up(chip);
908 spin_lock_irqsave(&chip->lock, flags);
909 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
910 spin_unlock_irqrestore(&chip->lock, flags);
911 snd_cs4231_mce_down(chip);
912
913#ifdef SNDRV_DEBUG_MCE
a131430c 914 snd_printdd("init: (4)\n");
1da177e4
LT		 915#endif
916
917 snd_cs4231_mce_up(chip);
918 spin_lock_irqsave(&chip->lock, flags);
919 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
920 spin_unlock_irqrestore(&chip->lock, flags);
921 snd_cs4231_mce_down(chip);
922
923#ifdef SNDRV_DEBUG_MCE
a131430c 924 snd_printdd("init: (5)\n");
1da177e4
LT		 925#endif
926}
927
be9b7e8c 928static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 929{
930 unsigned long flags;
931
12aa7579 932 mutex_lock(&chip->open_mutex);
1da177e4 933 if ((chip->mode & mode)) {
12aa7579 934 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 935 return -EAGAIN;
936 }
937 if (chip->mode & CS4231_MODE_OPEN) {
938 chip->mode |= mode;
12aa7579 939 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 940 return 0;
941 }
942 /* ok. now enable and ack CODEC IRQ */
943 spin_lock_irqsave(&chip->lock, flags);
944 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
945 CS4231_RECORD_IRQ |
946 CS4231_TIMER_IRQ);
947 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
948 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
949 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
950
951 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
952 CS4231_RECORD_IRQ |
953 CS4231_TIMER_IRQ);
954 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
a131430c 955
1da177e4
LT		 956 spin_unlock_irqrestore(&chip->lock, flags);
957
958 chip->mode = mode;
12aa7579 959 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 960 return 0;
961}
962
be9b7e8c 963static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
1da177e4
LT		 964{
965 unsigned long flags;
966
12aa7579 967 mutex_lock(&chip->open_mutex);
1da177e4
LT		 968 chip->mode &= ~mode;
969 if (chip->mode & CS4231_MODE_OPEN) {
12aa7579 970 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 971 return;
972 }
973 snd_cs4231_calibrate_mute(chip, 1);
974
975 /* disable IRQ */
976 spin_lock_irqsave(&chip->lock, flags);
977 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
978 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
979 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
980
981 /* now disable record & playback */
982
983 if (chip->image[CS4231_IFACE_CTRL] &
984 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
985 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
986 spin_unlock_irqrestore(&chip->lock, flags);
987 snd_cs4231_mce_up(chip);
988 spin_lock_irqsave(&chip->lock, flags);
989 chip->image[CS4231_IFACE_CTRL] &=
990 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
991 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
992 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
993 spin_unlock_irqrestore(&chip->lock, flags);
994 snd_cs4231_mce_down(chip);
995 spin_lock_irqsave(&chip->lock, flags);
996 }
997
998 /* clear IRQ again */
999 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1000 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1001 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
1002 spin_unlock_irqrestore(&chip->lock, flags);
1003
1004 snd_cs4231_calibrate_mute(chip, 0);
1005
1006 chip->mode = 0;
12aa7579 1007 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1008}
1009
1010/*
1011 * timer open/close
1012 */
1013
be9b7e8c 1014static int snd_cs4231_timer_open(struct snd_timer *timer)
1da177e4 1015{
be9b7e8c 1016 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 1017 snd_cs4231_open(chip, CS4231_MODE_TIMER);
1018 return 0;
1019}
1020
be9b7e8c 1021static int snd_cs4231_timer_close(struct snd_timer * timer)
1da177e4 1022{
be9b7e8c 1023 struct snd_cs4231 *chip = snd_timer_chip(timer);
1da177e4
LT		 1024 snd_cs4231_close(chip, CS4231_MODE_TIMER);
1025 return 0;
1026}
1027
be9b7e8c 1028static struct snd_timer_hardware snd_cs4231_timer_table =
1da177e4
LT		 1029{
1030 .flags = SNDRV_TIMER_HW_AUTO,
1031 .resolution = 9945,
1032 .ticks = 65535,
1033 .open = snd_cs4231_timer_open,
1034 .close = snd_cs4231_timer_close,
1035 .c_resolution = snd_cs4231_timer_resolution,
1036 .start = snd_cs4231_timer_start,
1037 .stop = snd_cs4231_timer_stop,
1038};
1039
1040/*
1041 * ok.. exported functions..
1042 */
1043
be9b7e8c
TI		 1044static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
1045 struct snd_pcm_hw_params *hw_params)
1da177e4 1046{
be9b7e8c 1047 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1048 unsigned char new_pdfr;
1049 int err;
1050
1051 if ((err = snd_pcm_lib_malloc_pages(substream,
1052 params_buffer_bytes(hw_params))) < 0)
1053 return err;
1054 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1055 params_channels(hw_params)) |
1056 snd_cs4231_get_rate(params_rate(hw_params));
1057 snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1058
1059 return 0;
1060}
1061
be9b7e8c 1062static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1063{
1064 return snd_pcm_lib_free_pages(substream);
1065}
1066
be9b7e8c 1067static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1068{
be9b7e8c
TI		 1069 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1070 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1071 unsigned long flags;
1072
1073 spin_lock_irqsave(&chip->lock, flags);
a131430c 1074
1da177e4
LT		 1075 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1076 CS4231_PLAYBACK_PIO);
a131430c 1077
817dd6ee 1078 BUG_ON(runtime->period_size > 0xffff + 1);
a131430c 1079
a131430c 1080 chip->p_periods_sent = 0;
1da177e4
LT		 1081 spin_unlock_irqrestore(&chip->lock, flags);
1082
1083 return 0;
1084}
1085
be9b7e8c
TI		 1086static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
1087 struct snd_pcm_hw_params *hw_params)
1da177e4 1088{
be9b7e8c 1089 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1090 unsigned char new_cdfr;
1091 int err;
1092
1093 if ((err = snd_pcm_lib_malloc_pages(substream,
1094 params_buffer_bytes(hw_params))) < 0)
1095 return err;
1096 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1097 params_channels(hw_params)) |
1098 snd_cs4231_get_rate(params_rate(hw_params));
1099 snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1100
1101 return 0;
1102}
1103
be9b7e8c 1104static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1105{
1106 return snd_pcm_lib_free_pages(substream);
1107}
1108
be9b7e8c 1109static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1110{
be9b7e8c 1111 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&chip->lock, flags);
1115 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1116 CS4231_RECORD_PIO);
1117
a131430c 1118
5a820fa7 1119 chip->c_periods_sent = 0;
1da177e4
LT		 1120 spin_unlock_irqrestore(&chip->lock, flags);
1121
1122 return 0;
1123}
1124
be9b7e8c 1125static void snd_cs4231_overrange(struct snd_cs4231 *chip)
1da177e4
LT		 1126{
1127 unsigned long flags;
1128 unsigned char res;
1129
1130 spin_lock_irqsave(&chip->lock, flags);
1131 res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1132 spin_unlock_irqrestore(&chip->lock, flags);
1133
1134 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1135 chip->capture_substream->runtime->overrange++;
1136}
1137
be9b7e8c 1138static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
1da177e4 1139{
1da177e4
LT		 1140 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1141 snd_pcm_period_elapsed(chip->playback_substream);
b128254f 1142 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1da177e4
LT		 1143 &chip->p_periods_sent);
1144 }
1145}
1146
be9b7e8c 1147static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
1da177e4 1148{
1da177e4
LT		 1149 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1150 snd_pcm_period_elapsed(chip->capture_substream);
b128254f 1151 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1da177e4
LT		 1152 &chip->c_periods_sent);
1153 }
1154}
1da177e4 1155
be9b7e8c 1156static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1157{
be9b7e8c
TI		 1158 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1159 struct cs4231_dma_control *dma_cont = &chip->p_dma;
5a820fa7 1160 size_t ptr;
5a820fa7 1161
1da177e4
LT		 1162 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1163 return 0;
b128254f
GC		 1164 ptr = dma_cont->address(dma_cont);
1165 if (ptr != 0)
1166 ptr -= substream->runtime->dma_addr;
1167
1da177e4
LT		 1168 return bytes_to_frames(substream->runtime, ptr);
1169}
1170
be9b7e8c 1171static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1172{
be9b7e8c
TI		 1173 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1174 struct cs4231_dma_control *dma_cont = &chip->c_dma;
5a820fa7 1175 size_t ptr;
1da177e4
LT		 1176
1177 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1178 return 0;
b128254f
GC		 1179 ptr = dma_cont->address(dma_cont);
1180 if (ptr != 0)
1181 ptr -= substream->runtime->dma_addr;
1182
1da177e4
LT		 1183 return bytes_to_frames(substream->runtime, ptr);
1184}
1185
1186/*
1187
1188 */
1189
be9b7e8c 1190static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
1da177e4
LT		 1191{
1192 unsigned long flags;
1193 int i, id, vers;
1194 unsigned char *ptr;
1195
1da177e4
LT		 1196 id = vers = 0;
1197 for (i = 0; i < 50; i++) {
1198 mb();
1199 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
1200 udelay(2000);
1201 else {
1202 spin_lock_irqsave(&chip->lock, flags);
1203 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1204 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1205 vers = snd_cs4231_in(chip, CS4231_VERSION);
1206 spin_unlock_irqrestore(&chip->lock, flags);
1207 if (id == 0x0a)
1208 break; /* this is valid value */
1209 }
1210 }
1211 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1212 if (id != 0x0a)
1213 return -ENODEV; /* no valid device found */
1214
1215 spin_lock_irqsave(&chip->lock, flags);
1216
1217
b128254f
GC		 1218 /* Reset DMA engine (sbus only). */
1219 chip->p_dma.reset(chip);
1da177e4
LT		 1220
1221 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
1222 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1223 mb();
1224
1225 spin_unlock_irqrestore(&chip->lock, flags);
1226
1227 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1228 chip->image[CS4231_IFACE_CTRL] =
1229 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1230 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1231 chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1232 if (vers & 0x20)
1233 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1234
1235 ptr = (unsigned char *) &chip->image;
1236
1237 snd_cs4231_mce_down(chip);
1238
1239 spin_lock_irqsave(&chip->lock, flags);
1240
1241 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
1242 snd_cs4231_out(chip, i, *ptr++);
1243
1244 spin_unlock_irqrestore(&chip->lock, flags);
1245
1246 snd_cs4231_mce_up(chip);
1247
1248 snd_cs4231_mce_down(chip);
1249
1250 mdelay(2);
1251
1252 return 0; /* all things are ok.. */
1253}
1254
be9b7e8c 1255static struct snd_pcm_hardware snd_cs4231_playback =
1da177e4
LT		 1256{
1257 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1258 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1259 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1260 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1261 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1262 SNDRV_PCM_FMTBIT_S16_BE),
1263 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1264 .rate_min = 5510,
1265 .rate_max = 48000,
1266 .channels_min = 1,
1267 .channels_max = 2,
1268 .buffer_bytes_max = (32*1024),
f9af1d9d 1269 .period_bytes_min = 64,
1da177e4
LT		 1270 .period_bytes_max = (32*1024),
1271 .periods_min = 1,
1272 .periods_max = 1024,
1273};
1274
be9b7e8c 1275static struct snd_pcm_hardware snd_cs4231_capture =
1da177e4
LT		 1276{
1277 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1278 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1279 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1280 SNDRV_PCM_FMTBIT_IMA_ADPCM |
1281 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1282 SNDRV_PCM_FMTBIT_S16_BE),
1283 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1284 .rate_min = 5510,
1285 .rate_max = 48000,
1286 .channels_min = 1,
1287 .channels_max = 2,
1288 .buffer_bytes_max = (32*1024),
f9af1d9d 1289 .period_bytes_min = 64,
1da177e4
LT		 1290 .period_bytes_max = (32*1024),
1291 .periods_min = 1,
1292 .periods_max = 1024,
1293};
1294
be9b7e8c 1295static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
1da177e4 1296{
be9b7e8c
TI		 1297 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1298 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1299 int err;
1300
1301 runtime->hw = snd_cs4231_playback;
1302
1303 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1304 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1305 return err;
1306 }
1307 chip->playback_substream = substream;
1308 chip->p_periods_sent = 0;
1309 snd_pcm_set_sync(substream);
1310 snd_cs4231_xrate(runtime);
1311
1312 return 0;
1313}
1314
be9b7e8c 1315static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
1da177e4 1316{
be9b7e8c
TI		 1317 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1318 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1319 int err;
1320
1321 runtime->hw = snd_cs4231_capture;
1322
1323 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1324 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1325 return err;
1326 }
1327 chip->capture_substream = substream;
1328 chip->c_periods_sent = 0;
1329 snd_pcm_set_sync(substream);
1330 snd_cs4231_xrate(runtime);
1331
1332 return 0;
1333}
1334
be9b7e8c 1335static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
1da177e4 1336{
be9b7e8c 1337 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1338
1da177e4 1339 snd_cs4231_close(chip, CS4231_MODE_PLAY);
b128254f 1340 chip->playback_substream = NULL;
1da177e4
LT		 1341
1342 return 0;
1343}
1344
be9b7e8c 1345static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
1da177e4 1346{
be9b7e8c 1347 struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
1da177e4 1348
1da177e4 1349 snd_cs4231_close(chip, CS4231_MODE_RECORD);
b128254f 1350 chip->capture_substream = NULL;
1da177e4
LT		 1351
1352 return 0;
1353}
1354
1355/* XXX We can do some power-management, in particular on EBUS using
1356 * XXX the audio AUXIO register...
1357 */
1358
be9b7e8c 1359static struct snd_pcm_ops snd_cs4231_playback_ops = {
1da177e4
LT		 1360 .open = snd_cs4231_playback_open,
1361 .close = snd_cs4231_playback_close,
1362 .ioctl = snd_pcm_lib_ioctl,
1363 .hw_params = snd_cs4231_playback_hw_params,
1364 .hw_free = snd_cs4231_playback_hw_free,
1365 .prepare = snd_cs4231_playback_prepare,
1366 .trigger = snd_cs4231_trigger,
1367 .pointer = snd_cs4231_playback_pointer,
1368};
1369
be9b7e8c 1370static struct snd_pcm_ops snd_cs4231_capture_ops = {
1da177e4
LT		 1371 .open = snd_cs4231_capture_open,
1372 .close = snd_cs4231_capture_close,
1373 .ioctl = snd_pcm_lib_ioctl,
1374 .hw_params = snd_cs4231_capture_hw_params,
1375 .hw_free = snd_cs4231_capture_hw_free,
1376 .prepare = snd_cs4231_capture_prepare,
1377 .trigger = snd_cs4231_trigger,
1378 .pointer = snd_cs4231_capture_pointer,
1379};
1380
be9b7e8c 1381static int __init snd_cs4231_pcm(struct snd_cs4231 *chip)
1da177e4 1382{
be9b7e8c 1383 struct snd_pcm *pcm;
1da177e4
LT		 1384 int err;
1385
1386 if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
1387 return err;
1388
1389 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1390 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1391
1392 /* global setup */
1393 pcm->private_data = chip;
1da177e4
LT		 1394 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1395 strcpy(pcm->name, "CS4231");
1396
b128254f 1397 chip->p_dma.preallocate(chip, pcm);
1da177e4
LT		 1398
1399 chip->pcm = pcm;
1400
1401 return 0;
1402}
1403
be9b7e8c 1404static int __init snd_cs4231_timer(struct snd_cs4231 *chip)
1da177e4 1405{
be9b7e8c
TI		 1406 struct snd_timer *timer;
1407 struct snd_timer_id tid;
1da177e4
LT		 1408 int err;
1409
1410 /* Timer initialization */
1411 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1412 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1413 tid.card = chip->card->number;
1414 tid.device = 0;
1415 tid.subdevice = 0;
1416 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1417 return err;
1418 strcpy(timer->name, "CS4231");
1419 timer->private_data = chip;
1da177e4
LT		 1420 timer->hw = snd_cs4231_timer_table;
1421 chip->timer = timer;
1422
1423 return 0;
1424}
1425
1426/*
1427 * MIXER part
1428 */
1429
be9b7e8c
TI		 1430static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
1431 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1432{
1433 static char *texts[4] = {
1434 "Line", "CD", "Mic", "Mix"
1435 };
be9b7e8c 1436 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1437
1438 snd_assert(chip->card != NULL, return -EINVAL);
1439 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1440 uinfo->count = 2;
1441 uinfo->value.enumerated.items = 4;
1442 if (uinfo->value.enumerated.item > 3)
1443 uinfo->value.enumerated.item = 3;
1444 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1445
1446 return 0;
1447}
1448
be9b7e8c
TI		 1449static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
1450 struct snd_ctl_elem_value *ucontrol)
1da177e4 1451{
be9b7e8c 1452 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&chip->lock, flags);
1456 ucontrol->value.enumerated.item[0] =
1457 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1458 ucontrol->value.enumerated.item[1] =
1459 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1460 spin_unlock_irqrestore(&chip->lock, flags);
1461
1462 return 0;
1463}
1464
be9b7e8c
TI		 1465static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
1466 struct snd_ctl_elem_value *ucontrol)
1da177e4 1467{
be9b7e8c 1468 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1469 unsigned long flags;
1470 unsigned short left, right;
1471 int change;
1472
1473 if (ucontrol->value.enumerated.item[0] > 3 ||
1474 ucontrol->value.enumerated.item[1] > 3)
1475 return -EINVAL;
1476 left = ucontrol->value.enumerated.item[0] << 6;
1477 right = ucontrol->value.enumerated.item[1] << 6;
1478
1479 spin_lock_irqsave(&chip->lock, flags);
1480
1481 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1482 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1483 change = left != chip->image[CS4231_LEFT_INPUT] ||
1484 right != chip->image[CS4231_RIGHT_INPUT];
1485 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1486 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1487
1488 spin_unlock_irqrestore(&chip->lock, flags);
1489
1490 return change;
1491}
1492
be9b7e8c
TI		 1493static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
1494 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1495{
1496 int mask = (kcontrol->private_value >> 16) & 0xff;
1497
1498 uinfo->type = (mask == 1) ?
1499 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1500 uinfo->count = 1;
1501 uinfo->value.integer.min = 0;
1502 uinfo->value.integer.max = mask;
1503
1504 return 0;
1505}
1506
be9b7e8c
TI		 1507static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
1508 struct snd_ctl_elem_value *ucontrol)
1da177e4 1509{
be9b7e8c 1510 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1511 unsigned long flags;
1512 int reg = kcontrol->private_value & 0xff;
1513 int shift = (kcontrol->private_value >> 8) & 0xff;
1514 int mask = (kcontrol->private_value >> 16) & 0xff;
1515 int invert = (kcontrol->private_value >> 24) & 0xff;
1516
1517 spin_lock_irqsave(&chip->lock, flags);
1518
1519 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1520
1521 spin_unlock_irqrestore(&chip->lock, flags);
1522
1523 if (invert)
1524 ucontrol->value.integer.value[0] =
1525 (mask - ucontrol->value.integer.value[0]);
1526
1527 return 0;
1528}
1529
be9b7e8c
TI		 1530static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
1531 struct snd_ctl_elem_value *ucontrol)
1da177e4 1532{
be9b7e8c 1533 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1534 unsigned long flags;
1535 int reg = kcontrol->private_value & 0xff;
1536 int shift = (kcontrol->private_value >> 8) & 0xff;
1537 int mask = (kcontrol->private_value >> 16) & 0xff;
1538 int invert = (kcontrol->private_value >> 24) & 0xff;
1539 int change;
1540 unsigned short val;
1541
1542 val = (ucontrol->value.integer.value[0] & mask);
1543 if (invert)
1544 val = mask - val;
1545 val <<= shift;
1546
1547 spin_lock_irqsave(&chip->lock, flags);
1548
1549 val = (chip->image[reg] & ~(mask << shift)) | val;
1550 change = val != chip->image[reg];
1551 snd_cs4231_out(chip, reg, val);
1552
1553 spin_unlock_irqrestore(&chip->lock, flags);
1554
1555 return change;
1556}
1557
be9b7e8c
TI		 1558static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
1559 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1560{
1561 int mask = (kcontrol->private_value >> 24) & 0xff;
1562
1563 uinfo->type = mask == 1 ?
1564 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1565 uinfo->count = 2;
1566 uinfo->value.integer.min = 0;
1567 uinfo->value.integer.max = mask;
1568
1569 return 0;
1570}
1571
be9b7e8c
TI		 1572static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
1573 struct snd_ctl_elem_value *ucontrol)
1da177e4 1574{
be9b7e8c 1575 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1576 unsigned long flags;
1577 int left_reg = kcontrol->private_value & 0xff;
1578 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1579 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1580 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1581 int mask = (kcontrol->private_value >> 24) & 0xff;
1582 int invert = (kcontrol->private_value >> 22) & 1;
1583
1584 spin_lock_irqsave(&chip->lock, flags);
1585
1586 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1587 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1588
1589 spin_unlock_irqrestore(&chip->lock, flags);
1590
1591 if (invert) {
1592 ucontrol->value.integer.value[0] =
1593 (mask - ucontrol->value.integer.value[0]);
1594 ucontrol->value.integer.value[1] =
1595 (mask - ucontrol->value.integer.value[1]);
1596 }
1597
1598 return 0;
1599}
1600
be9b7e8c
TI		 1601static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
1602 struct snd_ctl_elem_value *ucontrol)
1da177e4 1603{
be9b7e8c 1604 struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1605 unsigned long flags;
1606 int left_reg = kcontrol->private_value & 0xff;
1607 int right_reg = (kcontrol->private_value >> 8) & 0xff;
1608 int shift_left = (kcontrol->private_value >> 16) & 0x07;
1609 int shift_right = (kcontrol->private_value >> 19) & 0x07;
1610 int mask = (kcontrol->private_value >> 24) & 0xff;
1611 int invert = (kcontrol->private_value >> 22) & 1;
1612 int change;
1613 unsigned short val1, val2;
1614
1615 val1 = ucontrol->value.integer.value[0] & mask;
1616 val2 = ucontrol->value.integer.value[1] & mask;
1617 if (invert) {
1618 val1 = mask - val1;
1619 val2 = mask - val2;
1620 }
1621 val1 <<= shift_left;
1622 val2 <<= shift_right;
1623
1624 spin_lock_irqsave(&chip->lock, flags);
1625
1626 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1627 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1628 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1629 snd_cs4231_out(chip, left_reg, val1);
1630 snd_cs4231_out(chip, right_reg, val2);
1631
1632 spin_unlock_irqrestore(&chip->lock, flags);
1633
1634 return change;
1635}
1636
1637#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1638{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1639 .info = snd_cs4231_info_single, \
1640 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1641 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1642
1643#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1644{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1645 .info = snd_cs4231_info_double, \
1646 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1647 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1648
be9b7e8c 1649static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = {
1da177e4
LT		 1650CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1651CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1652CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1653CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1654CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1655CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1656CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1657CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1658CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1659CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1660CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1661CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1662CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1663{
1664 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1665 .name = "Capture Source",
1666 .info = snd_cs4231_info_mux,
1667 .get = snd_cs4231_get_mux,
1668 .put = snd_cs4231_put_mux,
1669},
1670CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1671CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1672CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1673/* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1674CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1675CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1676};
1677
be9b7e8c 1678static int __init snd_cs4231_mixer(struct snd_cs4231 *chip)
1da177e4 1679{
be9b7e8c 1680 struct snd_card *card;
1da177e4
LT		 1681 int err, idx;
1682
1683 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1684
1685 card = chip->card;
1686
1687 strcpy(card->mixername, chip->pcm->name);
1688
1689 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1690 if ((err = snd_ctl_add(card,
1691 snd_ctl_new1(&snd_cs4231_controls[idx],
1692 chip))) < 0)
1693 return err;
1694 }
1695 return 0;
1696}
1697
1698static int dev;
1699
be9b7e8c 1700static int __init cs4231_attach_begin(struct snd_card **rcard)
1da177e4 1701{
be9b7e8c 1702 struct snd_card *card;
1da177e4
LT		 1703
1704 *rcard = NULL;
1705
1706 if (dev >= SNDRV_CARDS)
1707 return -ENODEV;
1708
1709 if (!enable[dev]) {
1710 dev++;
1711 return -ENOENT;
1712 }
1713
1714 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1715 if (card == NULL)
1716 return -ENOMEM;
1717
1718 strcpy(card->driver, "CS4231");
1719 strcpy(card->shortname, "Sun CS4231");
1720
1721 *rcard = card;
1722 return 0;
1723}
1724
be9b7e8c 1725static int __init cs4231_attach_finish(struct snd_card *card, struct snd_cs4231 *chip)
1da177e4
LT		 1726{
1727 int err;
1728
1729 if ((err = snd_cs4231_pcm(chip)) < 0)
1730 goto out_err;
1731
1732 if ((err = snd_cs4231_mixer(chip)) < 0)
1733 goto out_err;
1734
1735 if ((err = snd_cs4231_timer(chip)) < 0)
1736 goto out_err;
1737
1738 if ((err = snd_card_register(card)) < 0)
1739 goto out_err;
1740
1741 chip->next = cs4231_list;
1742 cs4231_list = chip;
1743
1744 dev++;
1745 return 0;
1746
1747out_err:
1748 snd_card_free(card);
1749 return err;
1750}
1751
1752#ifdef SBUS_SUPPORT
b128254f 1753
7d12e780 1754static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
b128254f
GC		 1755{
1756 unsigned long flags;
1757 unsigned char status;
1758 u32 csr;
be9b7e8c 1759 struct snd_cs4231 *chip = dev_id;
b128254f
GC		 1760
1761 /*This is IRQ is not raised by the cs4231*/
1762 if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
1763 return IRQ_NONE;
1764
1765 /* ACK the APC interrupt. */
1766 csr = sbus_readl(chip->port + APCCSR);
1767
1768 sbus_writel(csr, chip->port + APCCSR);
1769
1770 if ((csr & APC_PDMA_READY) &&
1771 (csr & APC_PLAY_INT) &&
1772 (csr & APC_XINT_PNVA) &&
1773 !(csr & APC_XINT_EMPT))
1774 snd_cs4231_play_callback(chip);
1775
1776 if ((csr & APC_CDMA_READY) &&
1777 (csr & APC_CAPT_INT) &&
1778 (csr & APC_XINT_CNVA) &&
1779 !(csr & APC_XINT_EMPT))
1780 snd_cs4231_capture_callback(chip);
1781
1782 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1783
1784 if (status & CS4231_TIMER_IRQ) {
1785 if (chip->timer)
1786 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1787 }
1788
1789 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1790 snd_cs4231_overrange(chip);
1791
1792 /* ACK the CS4231 interrupt. */
1793 spin_lock_irqsave(&chip->lock, flags);
1794 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1795 spin_unlock_irqrestore(&chip->lock, flags);
1796
d35a1b9e 1797 return IRQ_HANDLED;
b128254f
GC		 1798}
1799
1800/*
1801 * SBUS DMA routines
1802 */
1803
be9b7e8c 1804static int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
b128254f
GC		 1805{
1806 unsigned long flags;
1807 u32 test, csr;
1808 int err;
be9b7e8c 1809 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1810
1811 if (len >= (1 << 24))
1812 return -EINVAL;
1813 spin_lock_irqsave(&base->lock, flags);
1814 csr = sbus_readl(base->regs + APCCSR);
1815 err = -EINVAL;
1816 test = APC_CDMA_READY;
1817 if ( base->dir == APC_PLAY )
1818 test = APC_PDMA_READY;
1819 if (!(csr & test))
1820 goto out;
1821 err = -EBUSY;
b128254f
GC		 1822 test = APC_XINT_CNVA;
1823 if ( base->dir == APC_PLAY )
1824 test = APC_XINT_PNVA;
1825 if (!(csr & test))
1826 goto out;
1827 err = 0;
1828 sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1829 sbus_writel(len, base->regs + base->dir + APCNC);
1830out:
1831 spin_unlock_irqrestore(&base->lock, flags);
1832 return err;
1833}
1834
be9b7e8c 1835static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
b128254f
GC		 1836{
1837 unsigned long flags;
1838 u32 csr, test;
be9b7e8c 1839 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1840
1841 spin_lock_irqsave(&base->lock, flags);
1842 csr = sbus_readl(base->regs + APCCSR);
1843 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1844 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1845 APC_XINT_PENA;
1846 if ( base->dir == APC_RECORD )
1847 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1848 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1849 csr |= test;
1850 sbus_writel(csr, base->regs + APCCSR);
1851 spin_unlock_irqrestore(&base->lock, flags);
1852}
1853
be9b7e8c 1854static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 1855{
1856 unsigned long flags;
1857 u32 csr, shift;
be9b7e8c 1858 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1859
1860 spin_lock_irqsave(&base->lock, flags);
1861 if (!on) {
d35a1b9e
GC		 1862 sbus_writel(0, base->regs + base->dir + APCNC);
1863 sbus_writel(0, base->regs + base->dir + APCNVA);
1864 sbus_writel(0, base->regs + base->dir + APCC);
1865 sbus_writel(0, base->regs + base->dir + APCVA);
1866
1867 /* ACK any APC interrupts. */
1868 csr = sbus_readl(base->regs + APCCSR);
1869 sbus_writel(csr, base->regs + APCCSR);
b128254f 1870 }
d35a1b9e 1871 udelay(1000);
b128254f
GC		 1872 csr = sbus_readl(base->regs + APCCSR);
1873 shift = 0;
1874 if ( base->dir == APC_PLAY )
1875 shift = 1;
1876 if (on)
1877 csr &= ~(APC_CPAUSE << shift);
1878 else
1879 csr |= (APC_CPAUSE << shift);
1880 sbus_writel(csr, base->regs + APCCSR);
1881 if (on)
1882 csr |= (APC_CDMA_READY << shift);
1883 else
1884 csr &= ~(APC_CDMA_READY << shift);
1885 sbus_writel(csr, base->regs + APCCSR);
1886
1887 spin_unlock_irqrestore(&base->lock, flags);
1888}
1889
be9b7e8c 1890static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f 1891{
be9b7e8c 1892 struct sbus_dma_info *base = &dma_cont->sbus_info;
b128254f
GC		 1893
1894 return sbus_readl(base->regs + base->dir + APCVA);
1895}
1896
be9b7e8c 1897static void sbus_dma_reset(struct snd_cs4231 *chip)
b128254f
GC		 1898{
1899 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
1900 sbus_writel(0x00, chip->port + APCCSR);
1901 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
1902 chip->port + APCCSR);
1903
1904 udelay(20);
1905
1906 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
1907 chip->port + APCCSR);
1908 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
1909 APC_XINT_PENA |
1910 APC_XINT_CENA),
1911 chip->port + APCCSR);
1912}
1913
be9b7e8c 1914static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
b128254f
GC		 1915{
1916 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
1917 snd_dma_sbus_data(chip->dev_u.sdev),
1918 64*1024, 128*1024);
1919}
1920
1921/*
1922 * Init and exit routines
1923 */
1924
be9b7e8c 1925static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
1da177e4
LT		 1926{
1927 if (chip->irq[0])
1928 free_irq(chip->irq[0], chip);
1929
1930 if (chip->port)
1931 sbus_iounmap(chip->port, chip->regs_size);
1932
1da177e4
LT		 1933 kfree(chip);
1934
1935 return 0;
1936}
1937
be9b7e8c 1938static int snd_cs4231_sbus_dev_free(struct snd_device *device)
1da177e4 1939{
be9b7e8c 1940 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 1941
1942 return snd_cs4231_sbus_free(cp);
1943}
1944
be9b7e8c 1945static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
1da177e4
LT		 1946 .dev_free = snd_cs4231_sbus_dev_free,
1947};
1948
be9b7e8c 1949static int __init snd_cs4231_sbus_create(struct snd_card *card,
1da177e4
LT		 1950 struct sbus_dev *sdev,
1951 int dev,
be9b7e8c 1952 struct snd_cs4231 **rchip)
1da177e4 1953{
be9b7e8c 1954 struct snd_cs4231 *chip;
1da177e4
LT		 1955 int err;
1956
1957 *rchip = NULL;
561b220a 1958 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1959 if (chip == NULL)
1960 return -ENOMEM;
1961
1962 spin_lock_init(&chip->lock);
b128254f
GC		 1963 spin_lock_init(&chip->c_dma.sbus_info.lock);
1964 spin_lock_init(&chip->p_dma.sbus_info.lock);
12aa7579
IM		 1965 mutex_init(&chip->mce_mutex);
1966 mutex_init(&chip->open_mutex);
1da177e4
LT		 1967 chip->card = card;
1968 chip->dev_u.sdev = sdev;
1969 chip->regs_size = sdev->reg_addrs[0].reg_size;
1970 memcpy(&chip->image, &snd_cs4231_original_image,
1971 sizeof(snd_cs4231_original_image));
1972
1973 chip->port = sbus_ioremap(&sdev->resource[0], 0,
1974 chip->regs_size, "cs4231");
1975 if (!chip->port) {
a131430c 1976 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 1977 return -EIO;
1978 }
1979
b128254f
GC		 1980 chip->c_dma.sbus_info.regs = chip->port;
1981 chip->p_dma.sbus_info.regs = chip->port;
1982 chip->c_dma.sbus_info.dir = APC_RECORD;
1983 chip->p_dma.sbus_info.dir = APC_PLAY;
1984
1985 chip->p_dma.prepare = sbus_dma_prepare;
1986 chip->p_dma.enable = sbus_dma_enable;
1987 chip->p_dma.request = sbus_dma_request;
1988 chip->p_dma.address = sbus_dma_addr;
1989 chip->p_dma.reset = sbus_dma_reset;
1990 chip->p_dma.preallocate = sbus_dma_preallocate;
1991
1992 chip->c_dma.prepare = sbus_dma_prepare;
1993 chip->c_dma.enable = sbus_dma_enable;
1994 chip->c_dma.request = sbus_dma_request;
1995 chip->c_dma.address = sbus_dma_addr;
1996 chip->c_dma.reset = sbus_dma_reset;
1997 chip->c_dma.preallocate = sbus_dma_preallocate;
5a820fa7 1998
1da177e4 1999 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
65ca68b3 2000 IRQF_SHARED, "cs4231", chip)) {
c6387a48
DM		 2001 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
2002 dev, sdev->irqs[0]);
1da177e4
LT		 2003 snd_cs4231_sbus_free(chip);
2004 return -EBUSY;
2005 }
2006 chip->irq[0] = sdev->irqs[0];
2007
2008 if (snd_cs4231_probe(chip) < 0) {
2009 snd_cs4231_sbus_free(chip);
2010 return -ENODEV;
2011 }
2012 snd_cs4231_init(chip);
2013
2014 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2015 chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2016 snd_cs4231_sbus_free(chip);
2017 return err;
2018 }
2019
2020 *rchip = chip;
2021 return 0;
2022}
2023
be9b7e8c 2024static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
1da177e4
LT		 2025{
2026 struct resource *rp = &sdev->resource[0];
be9b7e8c
TI		 2027 struct snd_cs4231 *cp;
2028 struct snd_card *card;
1da177e4
LT		 2029 int err;
2030
2031 err = cs4231_attach_begin(&card);
2032 if (err)
2033 return err;
2034
5863aa65 2035 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
1da177e4
LT		 2036 card->shortname,
2037 rp->flags & 0xffL,
aa0a2ddc 2038 (unsigned long long)rp->start,
c6387a48 2039 sdev->irqs[0]);
1da177e4
LT		 2040
2041 if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
2042 snd_card_free(card);
2043 return err;
2044 }
2045
2046 return cs4231_attach_finish(card, cp);
2047}
2048#endif
2049
2050#ifdef EBUS_SUPPORT
b128254f
GC		 2051
2052static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
2053{
be9b7e8c 2054 struct snd_cs4231 *chip = cookie;
b128254f
GC		 2055
2056 snd_cs4231_play_callback(chip);
2057}
2058
2059static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
2060{
be9b7e8c 2061 struct snd_cs4231 *chip = cookie;
b128254f
GC		 2062
2063 snd_cs4231_capture_callback(chip);
2064}
2065
2066/*
2067 * EBUS DMA wrappers
2068 */
2069
be9b7e8c 2070static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
b128254f
GC		 2071{
2072 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
2073}
2074
be9b7e8c 2075static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
b128254f
GC		 2076{
2077 ebus_dma_enable(&dma_cont->ebus_info, on);
2078}
2079
be9b7e8c 2080static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
b128254f
GC		 2081{
2082 ebus_dma_prepare(&dma_cont->ebus_info, dir);
2083}
2084
be9b7e8c 2085static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
b128254f
GC		 2086{
2087 return ebus_dma_addr(&dma_cont->ebus_info);
2088}
2089
be9b7e8c 2090static void _ebus_dma_reset(struct snd_cs4231 *chip)
b128254f
GC		 2091{
2092 return;
2093}
2094
be9b7e8c 2095static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
b128254f
GC		 2096{
2097 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2098 snd_dma_pci_data(chip->dev_u.pdev),
2099 64*1024, 128*1024);
2100}
2101
2102/*
2103 * Init and exit routines
2104 */
2105
be9b7e8c 2106static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
1da177e4 2107{
b128254f
GC		 2108 if (chip->c_dma.ebus_info.regs) {
2109 ebus_dma_unregister(&chip->c_dma.ebus_info);
2110 iounmap(chip->c_dma.ebus_info.regs);
1da177e4 2111 }
b128254f
GC		 2112 if (chip->p_dma.ebus_info.regs) {
2113 ebus_dma_unregister(&chip->p_dma.ebus_info);
2114 iounmap(chip->p_dma.ebus_info.regs);
1da177e4
LT		 2115 }
2116
2117 if (chip->port)
2118 iounmap(chip->port);
1da177e4
LT		 2119
2120 kfree(chip);
2121
2122 return 0;
2123}
2124
be9b7e8c 2125static int snd_cs4231_ebus_dev_free(struct snd_device *device)
1da177e4 2126{
be9b7e8c 2127 struct snd_cs4231 *cp = device->device_data;
1da177e4
LT		 2128
2129 return snd_cs4231_ebus_free(cp);
2130}
2131
be9b7e8c 2132static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
1da177e4
LT		 2133 .dev_free = snd_cs4231_ebus_dev_free,
2134};
2135
be9b7e8c 2136static int __init snd_cs4231_ebus_create(struct snd_card *card,
1da177e4
LT		 2137 struct linux_ebus_device *edev,
2138 int dev,
be9b7e8c 2139 struct snd_cs4231 **rchip)
1da177e4 2140{
be9b7e8c 2141 struct snd_cs4231 *chip;
1da177e4
LT		 2142 int err;
2143
2144 *rchip = NULL;
561b220a 2145 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2146 if (chip == NULL)
2147 return -ENOMEM;
2148
2149 spin_lock_init(&chip->lock);
b128254f
GC		 2150 spin_lock_init(&chip->c_dma.ebus_info.lock);
2151 spin_lock_init(&chip->p_dma.ebus_info.lock);
12aa7579
IM		 2152 mutex_init(&chip->mce_mutex);
2153 mutex_init(&chip->open_mutex);
1da177e4
LT		 2154 chip->flags |= CS4231_FLAG_EBUS;
2155 chip->card = card;
2156 chip->dev_u.pdev = edev->bus->self;
2157 memcpy(&chip->image, &snd_cs4231_original_image,
2158 sizeof(snd_cs4231_original_image));
b128254f
GC		 2159 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
2160 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2161 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
2162 chip->c_dma.ebus_info.client_cookie = chip;
2163 chip->c_dma.ebus_info.irq = edev->irqs[0];
2164 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
2165 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2166 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
2167 chip->p_dma.ebus_info.client_cookie = chip;
2168 chip->p_dma.ebus_info.irq = edev->irqs[1];
2169
2170 chip->p_dma.prepare = _ebus_dma_prepare;
2171 chip->p_dma.enable = _ebus_dma_enable;
2172 chip->p_dma.request = _ebus_dma_request;
2173 chip->p_dma.address = _ebus_dma_addr;
2174 chip->p_dma.reset = _ebus_dma_reset;
2175 chip->p_dma.preallocate = _ebus_dma_preallocate;
2176
2177 chip->c_dma.prepare = _ebus_dma_prepare;
2178 chip->c_dma.enable = _ebus_dma_enable;
2179 chip->c_dma.request = _ebus_dma_request;
2180 chip->c_dma.address = _ebus_dma_addr;
2181 chip->c_dma.reset = _ebus_dma_reset;
2182 chip->c_dma.preallocate = _ebus_dma_preallocate;
1da177e4
LT		 2183
2184 chip->port = ioremap(edev->resource[0].start, 0x10);
b128254f
GC		 2185 chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
2186 chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
2187 if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) {
1da177e4 2188 snd_cs4231_ebus_free(chip);
a131430c 2189 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1da177e4
LT		 2190 return -EIO;
2191 }
2192
b128254f 2193 if (ebus_dma_register(&chip->c_dma.ebus_info)) {
1da177e4 2194 snd_cs4231_ebus_free(chip);
a131430c 2195 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
1da177e4
LT		 2196 return -EBUSY;
2197 }
b128254f 2198 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
1da177e4 2199 snd_cs4231_ebus_free(chip);
a131430c 2200 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
1da177e4
LT		 2201 return -EBUSY;
2202 }
2203
b128254f 2204 if (ebus_dma_register(&chip->p_dma.ebus_info)) {
1da177e4 2205 snd_cs4231_ebus_free(chip);
a131430c 2206 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
1da177e4
LT		 2207 return -EBUSY;
2208 }
b128254f 2209 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
1da177e4 2210 snd_cs4231_ebus_free(chip);
a131430c 2211 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
1da177e4
LT		 2212 return -EBUSY;
2213 }
2214
2215 if (snd_cs4231_probe(chip) < 0) {
2216 snd_cs4231_ebus_free(chip);
2217 return -ENODEV;
2218 }
2219 snd_cs4231_init(chip);
2220
2221 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2222 chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2223 snd_cs4231_ebus_free(chip);
2224 return err;
2225 }
2226
2227 *rchip = chip;
2228 return 0;
2229}
2230
be9b7e8c 2231static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
1da177e4 2232{
be9b7e8c
TI		 2233 struct snd_card *card;
2234 struct snd_cs4231 *chip;
1da177e4
LT		 2235 int err;
2236
2237 err = cs4231_attach_begin(&card);
2238 if (err)
2239 return err;
2240
c6387a48 2241 sprintf(card->longname, "%s at 0x%lx, irq %d",
1da177e4
LT		 2242 card->shortname,
2243 edev->resource[0].start,
c6387a48 2244 edev->irqs[0]);
1da177e4
LT		 2245
2246 if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
2247 snd_card_free(card);
2248 return err;
2249 }
2250
2251 return cs4231_attach_finish(card, chip);
2252}
2253#endif
2254
2255static int __init cs4231_init(void)
2256{
2257#ifdef SBUS_SUPPORT
2258 struct sbus_bus *sbus;
2259 struct sbus_dev *sdev;
2260#endif
2261#ifdef EBUS_SUPPORT
2262 struct linux_ebus *ebus;
2263 struct linux_ebus_device *edev;
2264#endif
2265 int found;
2266
2267 found = 0;
2268
2269#ifdef SBUS_SUPPORT
2270 for_all_sbusdev(sdev, sbus) {
2271 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2272 if (cs4231_sbus_attach(sdev) == 0)
2273 found++;
2274 }
2275 }
2276#endif
2277#ifdef EBUS_SUPPORT
2278 for_each_ebus(ebus) {
2279 for_each_ebusdev(edev, ebus) {
2280 int match = 0;
2281
690c8fd3 2282 if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) {
1da177e4 2283 match = 1;
690c8fd3 2284 } else if (!strcmp(edev->prom_node->name, "audio")) {
3198514d 2285 const char *compat;
1da177e4 2286
690c8fd3
DM		 2287 compat = of_get_property(edev->prom_node,
2288 "compatible", NULL);
2289 if (compat && !strcmp(compat, "SUNW,CS4231"))
1da177e4
LT		 2290 match = 1;
2291 }
2292
2293 if (match &&
2294 cs4231_ebus_attach(edev) == 0)
2295 found++;
2296 }
2297 }
2298#endif
2299
2300
2301 return (found > 0) ? 0 : -EIO;
2302}
2303
2304static void __exit cs4231_exit(void)
2305{
be9b7e8c 2306 struct snd_cs4231 *p = cs4231_list;
1da177e4
LT		 2307
2308 while (p != NULL) {
be9b7e8c 2309 struct snd_cs4231 *next = p->next;
1da177e4
LT		 2310
2311 snd_card_free(p->card);
2312
2313 p = next;
2314 }
2315
2316 cs4231_list = NULL;
2317}
2318
2319module_init(cs4231_init);
2320module_exit(cs4231_exit);
Linux kernel - Deliverables
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