[deliverable/linux.git] / tools / perf / perf.h

#ifndef _PERF_PERF_H
#define _PERF_PERF_H

#include <asm/unistd.h>

#if defined(__i386__)
#define mb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define wmb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define rmb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define cpu_relax()	asm volatile("rep; nop" ::: "memory");
#define CPUINFO_PROC	"model name"
#ifndef __NR_perf_event_open
# define __NR_perf_event_open 336
#endif
#ifndef __NR_futex
# define __NR_futex 240
#endif
#endif

#if defined(__x86_64__)
#define mb()		asm volatile("mfence" ::: "memory")
#define wmb()		asm volatile("sfence" ::: "memory")
#define rmb()		asm volatile("lfence" ::: "memory")
#define cpu_relax()	asm volatile("rep; nop" ::: "memory");
#define CPUINFO_PROC	"model name"
#ifndef __NR_perf_event_open
# define __NR_perf_event_open 298
#endif
#ifndef __NR_futex
# define __NR_futex 202
#endif
#endif

#ifdef __powerpc__
#include "../../arch/powerpc/include/uapi/asm/unistd.h"
#define mb()		asm volatile ("sync" ::: "memory")
#define wmb()		asm volatile ("sync" ::: "memory")
#define rmb()		asm volatile ("sync" ::: "memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __s390__
#define mb()		asm volatile("bcr 15,0" ::: "memory")
#define wmb()		asm volatile("bcr 15,0" ::: "memory")
#define rmb()		asm volatile("bcr 15,0" ::: "memory")
#endif

#ifdef __sh__
#if defined(__SH4A__) || defined(__SH5__)
# define mb()		asm volatile("synco" ::: "memory")
# define wmb()		asm volatile("synco" ::: "memory")
# define rmb()		asm volatile("synco" ::: "memory")
#else
# define mb()		asm volatile("" ::: "memory")
# define wmb()		asm volatile("" ::: "memory")
# define rmb()		asm volatile("" ::: "memory")
#endif
#define CPUINFO_PROC	"cpu type"
#endif

#ifdef __hppa__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __sparc__
#ifdef __LP64__
#define mb()		asm volatile("ba,pt %%xcc, 1f\n"	\
				     "membar #StoreLoad\n"	\
				     "1:\n":::"memory")
#else
#define mb()		asm volatile("":::"memory")
#endif
#define wmb()		asm volatile("":::"memory")
#define rmb()		asm volatile("":::"memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __alpha__
#define mb()		asm volatile("mb" ::: "memory")
#define wmb()		asm volatile("wmb" ::: "memory")
#define rmb()		asm volatile("mb" ::: "memory")
#define CPUINFO_PROC	"cpu model"
#endif

#ifdef __ia64__
#define mb()		asm volatile ("mf" ::: "memory")
#define wmb()		asm volatile ("mf" ::: "memory")
#define rmb()		asm volatile ("mf" ::: "memory")
#define cpu_relax()	asm volatile ("hint @pause" ::: "memory")
#define CPUINFO_PROC	"model name"
#endif

#ifdef __arm__
/*
 * Use the __kuser_memory_barrier helper in the CPU helper page. See
 * arch/arm/kernel/entry-armv.S in the kernel source for details.
 */
#define mb()		((void(*)(void))0xffff0fa0)()
#define wmb()		((void(*)(void))0xffff0fa0)()
#define rmb()		((void(*)(void))0xffff0fa0)()
#define CPUINFO_PROC	"Processor"
#endif

#ifdef __aarch64__
#define mb()		asm volatile("dmb ish" ::: "memory")
#define wmb()		asm volatile("dmb ishst" ::: "memory")
#define rmb()		asm volatile("dmb ishld" ::: "memory")
#define cpu_relax()	asm volatile("yield" ::: "memory")
#endif

#ifdef __mips__
#define mb()		asm volatile(					\
				".set	mips2\n\t"			\
				"sync\n\t"				\
				".set	mips0"				\
				: /* no output */			\
				: /* no input */			\
				: "memory")
#define wmb()	mb()
#define rmb()	mb()
#define CPUINFO_PROC	"cpu model"
#endif

#ifdef __arc__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"Processor"
#endif

#ifdef __metag__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"CPU"
#endif

#ifdef __xtensa__
#define mb()		asm volatile("memw" ::: "memory")
#define wmb()		asm volatile("memw" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"core ID"
#endif

#define barrier() asm volatile ("" ::: "memory")

#ifndef cpu_relax
#define cpu_relax() barrier()
#endif

#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))


#include <time.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/syscall.h>

#include <linux/perf_event.h>
#include "util/types.h"
#include <stdbool.h>

/*
 * prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
 * counters in the current task.
 */
#define PR_TASK_PERF_EVENTS_DISABLE   31
#define PR_TASK_PERF_EVENTS_ENABLE    32

#ifndef NSEC_PER_SEC
# define NSEC_PER_SEC			1000000000ULL
#endif
#ifndef NSEC_PER_USEC
# define NSEC_PER_USEC			1000ULL
#endif

static inline unsigned long long rdclock(void)
{
	struct timespec ts;

	clock_gettime(CLOCK_MONOTONIC, &ts);
	return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
}

/*
 * Pick up some kernel type conventions:
 */
#define __user
#define asmlinkage

#define unlikely(x)	__builtin_expect(!!(x), 0)
#define min(x, y) ({				\
	typeof(x) _min1 = (x);			\
	typeof(y) _min2 = (y);			\
	(void) (&_min1 == &_min2);		\
	_min1 < _min2 ? _min1 : _min2; })

extern bool test_attr__enabled;
void test_attr__init(void);
void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu,
		     int fd, int group_fd, unsigned long flags);

static inline int
sys_perf_event_open(struct perf_event_attr *attr,
		      pid_t pid, int cpu, int group_fd,
		      unsigned long flags)
{
	int fd;

	fd = syscall(__NR_perf_event_open, attr, pid, cpu,
		     group_fd, flags);

	if (unlikely(test_attr__enabled))
		test_attr__open(attr, pid, cpu, fd, group_fd, flags);

	return fd;
}

#define MAX_COUNTERS			256
#define MAX_NR_CPUS			256

struct ip_callchain {
	u64 nr;
	u64 ips[0];
};

struct branch_flags {
	u64 mispred:1;
	u64 predicted:1;
	u64 in_tx:1;
	u64 abort:1;
	u64 reserved:60;
};

struct branch_entry {
	u64				from;
	u64				to;
	struct branch_flags flags;
};

struct branch_stack {
	u64				nr;
	struct branch_entry	entries[0];
};

extern const char *input_name;
extern bool perf_host, perf_guest;
extern const char perf_version_string[];

void pthread__unblock_sigwinch(void);

#include "util/target.h"

enum perf_call_graph_mode {
	CALLCHAIN_NONE,
	CALLCHAIN_FP,
	CALLCHAIN_DWARF,
	CALLCHAIN_MAX
};

struct record_opts {
	struct target target;
	int	     call_graph;
	bool         call_graph_enabled;
	bool	     group;
	bool	     inherit_stat;
	bool	     no_buffering;
	bool	     no_inherit;
	bool	     no_inherit_set;
	bool	     no_samples;
	bool	     raw_samples;
	bool	     sample_address;
	bool	     sample_weight;
	bool	     sample_time;
	bool	     period;
	unsigned int freq;
	unsigned int mmap_pages;
	unsigned int user_freq;
	u64          branch_stack;
	u64	     default_interval;
	u64	     user_interval;
	u16	     stack_dump_size;
	bool	     sample_transaction;
	unsigned     initial_delay;
};

#endif
Commit	Line	Data
6eda5838 TG	1	#ifndef _PERF_PERF_H
	2	#define _PERF_PERF_H
	3
d2709c7c DH	4	#include <asm/unistd.h>
d2709c7c DH	5
11d1578f	6	#if defined(__i386__)
a94d342b PZ	7	#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
a94d342b PZ	8	#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
11d1578f VW	9	#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
11d1578f VW	10	#define cpu_relax() asm volatile("rep; nop" ::: "memory");
fbe96f29	11	#define CPUINFO_PROC "model name"
eae7a755 IM	12	#ifndef __NR_perf_event_open
	13	# define __NR_perf_event_open 336
	14	#endif
a0439711 DB	15	#ifndef __NR_futex
	16	# define __NR_futex 240
	17	#endif
11d1578f VW	18	#endif
	19
	20	#if defined(__x86_64__)
a94d342b PZ	21	#define mb() asm volatile("mfence" ::: "memory")
a94d342b PZ	22	#define wmb() asm volatile("sfence" ::: "memory")
1a482f38 PZ	23	#define rmb() asm volatile("lfence" ::: "memory")
1a482f38 PZ	24	#define cpu_relax() asm volatile("rep; nop" ::: "memory");
fbe96f29	25	#define CPUINFO_PROC "model name"
eae7a755 IM	26	#ifndef __NR_perf_event_open
	27	# define __NR_perf_event_open 298
	28	#endif
a0439711 DB	29	#ifndef __NR_futex
	30	# define __NR_futex 202
	31	#endif
1a482f38 PZ	32	#endif
	33
	34	#ifdef __powerpc__
1483c2ae	35	#include "../../arch/powerpc/include/uapi/asm/unistd.h"
a94d342b PZ	36	#define mb() asm volatile ("sync" ::: "memory")
a94d342b PZ	37	#define wmb() asm volatile ("sync" ::: "memory")
1a482f38	38	#define rmb() asm volatile ("sync" ::: "memory")
fbe96f29	39	#define CPUINFO_PROC "cpu"
1a482f38 PZ	40	#endif
1a482f38 PZ	41
12310e9c	42	#ifdef __s390__
a94d342b PZ	43	#define mb() asm volatile("bcr 15,0" ::: "memory")
a94d342b PZ	44	#define wmb() asm volatile("bcr 15,0" ::: "memory")
12310e9c	45	#define rmb() asm volatile("bcr 15,0" ::: "memory")
12310e9c MS	46	#endif
12310e9c MS	47
febe8345	48	#ifdef __sh__
febe8345	49	#if defined(__SH4A__) \|\| defined(__SH5__)
a94d342b PZ	50	# define mb() asm volatile("synco" ::: "memory")
a94d342b PZ	51	# define wmb() asm volatile("synco" ::: "memory")
febe8345 PM	52	# define rmb() asm volatile("synco" ::: "memory")
febe8345 PM	53	#else
a94d342b PZ	54	# define mb() asm volatile("" ::: "memory")
a94d342b PZ	55	# define wmb() asm volatile("" ::: "memory")
febe8345 PM	56	# define rmb() asm volatile("" ::: "memory")
febe8345 PM	57	#endif
fbe96f29	58	#define CPUINFO_PROC "cpu type"
febe8345 PM	59	#endif
febe8345 PM	60
2d4618dc	61	#ifdef __hppa__
a94d342b PZ	62	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	63	#define wmb() asm volatile("" ::: "memory")
2d4618dc	64	#define rmb() asm volatile("" ::: "memory")
fbe96f29	65	#define CPUINFO_PROC "cpu"
2d4618dc KM	66	#endif
2d4618dc KM	67
825c9fb4	68	#ifdef __sparc__
a94d342b PZ	69	#ifdef __LP64__
	70	#define mb() asm volatile("ba,pt %%xcc, 1f\n" \
	71	"membar #StoreLoad\n" \
	72	"1:\n":::"memory")
	73	#else
	74	#define mb() asm volatile("":::"memory")
	75	#endif
	76	#define wmb() asm volatile("":::"memory")
825c9fb4	77	#define rmb() asm volatile("":::"memory")
fbe96f29	78	#define CPUINFO_PROC "cpu"
825c9fb4 JA	79	#endif
825c9fb4 JA	80
fcd14b32	81	#ifdef __alpha__
a94d342b PZ	82	#define mb() asm volatile("mb" ::: "memory")
a94d342b PZ	83	#define wmb() asm volatile("wmb" ::: "memory")
fcd14b32	84	#define rmb() asm volatile("mb" ::: "memory")
fbe96f29	85	#define CPUINFO_PROC "cpu model"
fcd14b32 MC	86	#endif
fcd14b32 MC	87
11ada26c	88	#ifdef __ia64__
a94d342b PZ	89	#define mb() asm volatile ("mf" ::: "memory")
a94d342b PZ	90	#define wmb() asm volatile ("mf" ::: "memory")
11ada26c LT	91	#define rmb() asm volatile ("mf" ::: "memory")
11ada26c LT	92	#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
fbe96f29	93	#define CPUINFO_PROC "model name"
11ada26c LT	94	#endif
11ada26c LT	95
58e9f941	96	#ifdef __arm__
58e9f941 JI	97	/*
	98	* Use the __kuser_memory_barrier helper in the CPU helper page. See
	99	* arch/arm/kernel/entry-armv.S in the kernel source for details.
	100	*/
a94d342b PZ	101	#define mb() ((void(*)(void))0xffff0fa0)()
a94d342b PZ	102	#define wmb() ((void(*)(void))0xffff0fa0)()
da7196e1	103	#define rmb() ((void(*)(void))0xffff0fa0)()
fbe96f29	104	#define CPUINFO_PROC "Processor"
58e9f941 JI	105	#endif
58e9f941 JI	106
03089688	107	#ifdef __aarch64__
a94d342b	108	#define mb() asm volatile("dmb ish" ::: "memory")
f428ebd1 PZ	109	#define wmb() asm volatile("dmb ishst" ::: "memory")
f428ebd1 PZ	110	#define rmb() asm volatile("dmb ishld" ::: "memory")
03089688 WD	111	#define cpu_relax() asm volatile("yield" ::: "memory")
	112	#endif
	113
c1e028ef	114	#ifdef __mips__
a94d342b	115	#define mb() asm volatile( \
c1e028ef DCZ	116	".set mips2\n\t" \
	117	"sync\n\t" \
	118	".set mips0" \
	119	: /* no output */ \
	120	: /* no input */ \
	121	: "memory")
a94d342b PZ	122	#define wmb() mb()
a94d342b PZ	123	#define rmb() mb()
fbe96f29	124	#define CPUINFO_PROC "cpu model"
c1e028ef DCZ	125	#endif
c1e028ef DCZ	126
9854783e	127	#ifdef __arc__
a94d342b PZ	128	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	129	#define wmb() asm volatile("" ::: "memory")
9854783e	130	#define rmb() asm volatile("" ::: "memory")
9854783e VG	131	#define CPUINFO_PROC "Processor"
	132	#endif
	133
1bea5b81	134	#ifdef __metag__
a94d342b PZ	135	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	136	#define wmb() asm volatile("" ::: "memory")
1bea5b81	137	#define rmb() asm volatile("" ::: "memory")
1bea5b81 JH	138	#define CPUINFO_PROC "CPU"
	139	#endif
	140
3a46817f BS	141	#ifdef __xtensa__
	142	#define mb() asm volatile("memw" ::: "memory")
	143	#define wmb() asm volatile("memw" ::: "memory")
	144	#define rmb() asm volatile("" ::: "memory")
	145	#define CPUINFO_PROC "core ID"
	146	#endif
	147
a94d342b PZ	148	#define barrier() asm volatile ("" ::: "memory")
	149
	150	#ifndef cpu_relax
	151	#define cpu_relax() barrier()
	152	#endif
	153
	154	#define ACCESS_ONCE(x) ((volatile typeof(x) )&(x))
	155
	156
1a482f38 PZ	157	#include <time.h>
	158	#include <unistd.h>
	159	#include <sys/types.h>
	160	#include <sys/syscall.h>
	161
d2709c7c	162	#include <linux/perf_event.h>
7c6a1c65	163	#include "util/types.h"
8035458f	164	#include <stdbool.h>
1a482f38	165
6eda5838	166	/*
cdd6c482	167	* prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
6eda5838 TG	168	* counters in the current task.
6eda5838 TG	169	*/
cdd6c482 IM	170	#define PR_TASK_PERF_EVENTS_DISABLE 31
cdd6c482 IM	171	#define PR_TASK_PERF_EVENTS_ENABLE 32
6eda5838	172
a92e7023 TG	173	#ifndef NSEC_PER_SEC
	174	# define NSEC_PER_SEC 1000000000ULL
	175	#endif
70f7b4a7 DA	176	#ifndef NSEC_PER_USEC
	177	# define NSEC_PER_USEC 1000ULL
	178	#endif
a92e7023 TG	179
	180	static inline unsigned long long rdclock(void)
	181	{
	182	struct timespec ts;
	183
	184	clock_gettime(CLOCK_MONOTONIC, &ts);
	185	return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
	186	}
6eda5838 TG	187
	188	/*
	189	* Pick up some kernel type conventions:
	190	*/
	191	#define __user
	192	#define asmlinkage
	193
6eda5838 TG	194	#define unlikely(x) __builtin_expect(!!(x), 0)
	195	#define min(x, y) ({ \
	196	typeof(x) _min1 = (x); \
	197	typeof(y) _min2 = (y); \
	198	(void) (&_min1 == &_min2); \
	199	_min1 < _min2 ? _min1 : _min2; })
	200
52502bf2 JO	201	extern bool test_attr__enabled;
	202	void test_attr__init(void);
	203	void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu,
	204	int fd, int group_fd, unsigned long flags);
	205
6eda5838	206	static inline int
cdd6c482	207	sys_perf_event_open(struct perf_event_attr *attr,
6eda5838 TG	208	pid_t pid, int cpu, int group_fd,
	209	unsigned long flags)
	210	{
52502bf2 JO	211	int fd;
	212
	213	fd = syscall(__NR_perf_event_open, attr, pid, cpu,
	214	group_fd, flags);
	215
	216	if (unlikely(test_attr__enabled))
	217	test_attr__open(attr, pid, cpu, fd, group_fd, flags);
	218
	219	return fd;
6eda5838 TG	220	}
6eda5838 TG	221
85a9f920 IM	222	#define MAX_COUNTERS 256
85a9f920 IM	223	#define MAX_NR_CPUS 256
6eda5838	224
8cb76d99 FW	225	struct ip_callchain {
	226	u64 nr;
	227	u64 ips[0];
f5970550 PZ	228	};
f5970550 PZ	229
b5387528 RAV	230	struct branch_flags {
	231	u64 mispred:1;
	232	u64 predicted:1;
f5d05bce AK	233	u64 in_tx:1;
	234	u64 abort:1;
	235	u64 reserved:60;
b5387528 RAV	236	};
	237
	238	struct branch_entry {
	239	u64 from;
	240	u64 to;
	241	struct branch_flags flags;
	242	};
	243
	244	struct branch_stack {
	245	u64 nr;
	246	struct branch_entry entries[0];
	247	};
	248
70cb4e96	249	extern const char *input_name;
8035458f	250	extern bool perf_host, perf_guest;
fbe96f29	251	extern const char perf_version_string[];
a1645ce1	252
3af6e338 ACM	253	void pthread__unblock_sigwinch(void);
3af6e338 ACM	254
12864b31	255	#include "util/target.h"
bea03405	256
26d33022 JO	257	enum perf_call_graph_mode {
	258	CALLCHAIN_NONE,
	259	CALLCHAIN_FP,
a601fdff JO	260	CALLCHAIN_DWARF,
a601fdff JO	261	CALLCHAIN_MAX
26d33022 JO	262	};
26d33022 JO	263
b4006796	264	struct record_opts {
602ad878	265	struct target target;
26d33022	266	int call_graph;
eb853e80	267	bool call_graph_enabled;
ed80f581	268	bool group;
0f82ebc4	269	bool inherit_stat;
509051ea	270	bool no_buffering;
0f82ebc4	271	bool no_inherit;
69e7e5b0	272	bool no_inherit_set;
0f82ebc4 ACM	273	bool no_samples;
	274	bool raw_samples;
	275	bool sample_address;
05484298	276	bool sample_weight;
0f82ebc4	277	bool sample_time;
3e76ac78	278	bool period;
0f82ebc4	279	unsigned int freq;
01c2d99b	280	unsigned int mmap_pages;
0f82ebc4	281	unsigned int user_freq;
a00dc319	282	u64 branch_stack;
0f82ebc4 ACM	283	u64 default_interval;
0f82ebc4 ACM	284	u64 user_interval;
26d33022	285	u16 stack_dump_size;
475eeab9	286	bool sample_transaction;
6619a53e	287	unsigned initial_delay;
0f82ebc4 ACM	288	};
0f82ebc4 ACM	289
6eda5838	290	#endif