[deliverable/linux.git] / tools / perf / perf.h

#ifndef _PERF_PERF_H
#define _PERF_PERF_H

#include <asm/unistd.h>

#if defined(__i386__)
#define mb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define wmb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define rmb()		asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
#define cpu_relax()	asm volatile("rep; nop" ::: "memory");
#define CPUINFO_PROC	"model name"
#ifndef __NR_perf_event_open
# define __NR_perf_event_open 336
#endif
#ifndef __NR_futex
# define __NR_futex 240
#endif
#ifndef __NR_gettid
# define __NR_gettid 224
#endif
#endif

#if defined(__x86_64__)
#define mb()		asm volatile("mfence" ::: "memory")
#define wmb()		asm volatile("sfence" ::: "memory")
#define rmb()		asm volatile("lfence" ::: "memory")
#define cpu_relax()	asm volatile("rep; nop" ::: "memory");
#define CPUINFO_PROC	"model name"
#ifndef __NR_perf_event_open
# define __NR_perf_event_open 298
#endif
#ifndef __NR_futex
# define __NR_futex 202
#endif
#ifndef __NR_gettid
# define __NR_gettid 186
#endif
#endif

#ifdef __powerpc__
#include "../../arch/powerpc/include/uapi/asm/unistd.h"
#define mb()		asm volatile ("sync" ::: "memory")
#define wmb()		asm volatile ("sync" ::: "memory")
#define rmb()		asm volatile ("sync" ::: "memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __s390__
#define mb()		asm volatile("bcr 15,0" ::: "memory")
#define wmb()		asm volatile("bcr 15,0" ::: "memory")
#define rmb()		asm volatile("bcr 15,0" ::: "memory")
#endif

#ifdef __sh__
#if defined(__SH4A__) || defined(__SH5__)
# define mb()		asm volatile("synco" ::: "memory")
# define wmb()		asm volatile("synco" ::: "memory")
# define rmb()		asm volatile("synco" ::: "memory")
#else
# define mb()		asm volatile("" ::: "memory")
# define wmb()		asm volatile("" ::: "memory")
# define rmb()		asm volatile("" ::: "memory")
#endif
#define CPUINFO_PROC	"cpu type"
#endif

#ifdef __hppa__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __sparc__
#ifdef __LP64__
#define mb()		asm volatile("ba,pt %%xcc, 1f\n"	\
				     "membar #StoreLoad\n"	\
				     "1:\n":::"memory")
#else
#define mb()		asm volatile("":::"memory")
#endif
#define wmb()		asm volatile("":::"memory")
#define rmb()		asm volatile("":::"memory")
#define CPUINFO_PROC	"cpu"
#endif

#ifdef __alpha__
#define mb()		asm volatile("mb" ::: "memory")
#define wmb()		asm volatile("wmb" ::: "memory")
#define rmb()		asm volatile("mb" ::: "memory")
#define CPUINFO_PROC	"cpu model"
#endif

#ifdef __ia64__
#define mb()		asm volatile ("mf" ::: "memory")
#define wmb()		asm volatile ("mf" ::: "memory")
#define rmb()		asm volatile ("mf" ::: "memory")
#define cpu_relax()	asm volatile ("hint @pause" ::: "memory")
#define CPUINFO_PROC	"model name"
#endif

#ifdef __arm__
/*
 * Use the __kuser_memory_barrier helper in the CPU helper page. See
 * arch/arm/kernel/entry-armv.S in the kernel source for details.
 */
#define mb()		((void(*)(void))0xffff0fa0)()
#define wmb()		((void(*)(void))0xffff0fa0)()
#define rmb()		((void(*)(void))0xffff0fa0)()
#define CPUINFO_PROC	"Processor"
#endif

#ifdef __aarch64__
#define mb()		asm volatile("dmb ish" ::: "memory")
#define wmb()		asm volatile("dmb ishst" ::: "memory")
#define rmb()		asm volatile("dmb ishld" ::: "memory")
#define cpu_relax()	asm volatile("yield" ::: "memory")
#endif

#ifdef __mips__
#define mb()		asm volatile(					\
				".set	mips2\n\t"			\
				"sync\n\t"				\
				".set	mips0"				\
				: /* no output */			\
				: /* no input */			\
				: "memory")
#define wmb()	mb()
#define rmb()	mb()
#define CPUINFO_PROC	"cpu model"
#endif

#ifdef __arc__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"Processor"
#endif

#ifdef __metag__
#define mb()		asm volatile("" ::: "memory")
#define wmb()		asm volatile("" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"CPU"
#endif

#ifdef __xtensa__
#define mb()		asm volatile("memw" ::: "memory")
#define wmb()		asm volatile("memw" ::: "memory")
#define rmb()		asm volatile("" ::: "memory")
#define CPUINFO_PROC	"core ID"
#endif

#ifdef __tile__
#define mb()		asm volatile ("mf" ::: "memory")
#define wmb()		asm volatile ("mf" ::: "memory")
#define rmb()		asm volatile ("mf" ::: "memory")
#define cpu_relax()	asm volatile ("mfspr zero, PASS" ::: "memory")
#define CPUINFO_PROC    "model name"
#endif

#define barrier() asm volatile ("" ::: "memory")

#ifndef cpu_relax
#define cpu_relax() barrier()
#endif

#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))


#include <time.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/syscall.h>

#include <linux/types.h>
#include <linux/perf_event.h>

/*
 * prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
 * counters in the current task.
 */
#define PR_TASK_PERF_EVENTS_DISABLE   31
#define PR_TASK_PERF_EVENTS_ENABLE    32

#ifndef NSEC_PER_SEC
# define NSEC_PER_SEC			1000000000ULL
#endif
#ifndef NSEC_PER_USEC
# define NSEC_PER_USEC			1000ULL
#endif

static inline unsigned long long rdclock(void)
{
	struct timespec ts;

	clock_gettime(CLOCK_MONOTONIC, &ts);
	return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
}

/*
 * Pick up some kernel type conventions:
 */
#define asmlinkage

#define unlikely(x)	__builtin_expect(!!(x), 0)
#define min(x, y) ({				\
	typeof(x) _min1 = (x);			\
	typeof(y) _min2 = (y);			\
	(void) (&_min1 == &_min2);		\
	_min1 < _min2 ? _min1 : _min2; })

extern bool test_attr__enabled;
void test_attr__init(void);
void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu,
		     int fd, int group_fd, unsigned long flags);

static inline int
sys_perf_event_open(struct perf_event_attr *attr,
		      pid_t pid, int cpu, int group_fd,
		      unsigned long flags)
{
	int fd;

	fd = syscall(__NR_perf_event_open, attr, pid, cpu,
		     group_fd, flags);

	if (unlikely(test_attr__enabled))
		test_attr__open(attr, pid, cpu, fd, group_fd, flags);

	return fd;
}

#define MAX_COUNTERS			256
#define MAX_NR_CPUS			256

struct ip_callchain {
	u64 nr;
	u64 ips[0];
};

struct branch_flags {
	u64 mispred:1;
	u64 predicted:1;
	u64 in_tx:1;
	u64 abort:1;
	u64 reserved:60;
};

struct branch_entry {
	u64				from;
	u64				to;
	struct branch_flags flags;
};

struct branch_stack {
	u64				nr;
	struct branch_entry	entries[0];
};

extern const char *input_name;
extern bool perf_host, perf_guest;
extern const char perf_version_string[];

void pthread__unblock_sigwinch(void);

#include "util/target.h"

enum perf_call_graph_mode {
	CALLCHAIN_NONE,
	CALLCHAIN_FP,
	CALLCHAIN_DWARF,
	CALLCHAIN_MAX
};

struct record_opts {
	struct target target;
	int	     call_graph;
	bool         call_graph_enabled;
	bool	     group;
	bool	     inherit_stat;
	bool	     no_buffering;
	bool	     no_inherit;
	bool	     no_inherit_set;
	bool	     no_samples;
	bool	     raw_samples;
	bool	     sample_address;
	bool	     sample_weight;
	bool	     sample_time;
	bool	     period;
	unsigned int freq;
	unsigned int mmap_pages;
	unsigned int user_freq;
	u64          branch_stack;
	u64	     default_interval;
	u64	     user_interval;
	u16	     stack_dump_size;
	bool	     sample_transaction;
	unsigned     initial_delay;
};

#endif
Commit	Line	Data
6eda5838 TG	1	#ifndef _PERF_PERF_H
	2	#define _PERF_PERF_H
	3
d2709c7c DH	4	#include <asm/unistd.h>
d2709c7c DH	5
11d1578f	6	#if defined(__i386__)
a94d342b PZ	7	#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
a94d342b PZ	8	#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
11d1578f VW	9	#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
11d1578f VW	10	#define cpu_relax() asm volatile("rep; nop" ::: "memory");
fbe96f29	11	#define CPUINFO_PROC "model name"
eae7a755 IM	12	#ifndef __NR_perf_event_open
	13	# define __NR_perf_event_open 336
	14	#endif
a0439711 DB	15	#ifndef __NR_futex
	16	# define __NR_futex 240
	17	#endif
4e85edfc JO	18	#ifndef __NR_gettid
	19	# define __NR_gettid 224
	20	#endif
11d1578f VW	21	#endif
	22
	23	#if defined(__x86_64__)
a94d342b PZ	24	#define mb() asm volatile("mfence" ::: "memory")
a94d342b PZ	25	#define wmb() asm volatile("sfence" ::: "memory")
1a482f38 PZ	26	#define rmb() asm volatile("lfence" ::: "memory")
1a482f38 PZ	27	#define cpu_relax() asm volatile("rep; nop" ::: "memory");
fbe96f29	28	#define CPUINFO_PROC "model name"
eae7a755 IM	29	#ifndef __NR_perf_event_open
	30	# define __NR_perf_event_open 298
	31	#endif
a0439711 DB	32	#ifndef __NR_futex
	33	# define __NR_futex 202
	34	#endif
4e85edfc JO	35	#ifndef __NR_gettid
	36	# define __NR_gettid 186
	37	#endif
1a482f38 PZ	38	#endif
	39
	40	#ifdef __powerpc__
1483c2ae	41	#include "../../arch/powerpc/include/uapi/asm/unistd.h"
a94d342b PZ	42	#define mb() asm volatile ("sync" ::: "memory")
a94d342b PZ	43	#define wmb() asm volatile ("sync" ::: "memory")
1a482f38	44	#define rmb() asm volatile ("sync" ::: "memory")
fbe96f29	45	#define CPUINFO_PROC "cpu"
1a482f38 PZ	46	#endif
1a482f38 PZ	47
12310e9c	48	#ifdef __s390__
a94d342b PZ	49	#define mb() asm volatile("bcr 15,0" ::: "memory")
a94d342b PZ	50	#define wmb() asm volatile("bcr 15,0" ::: "memory")
12310e9c	51	#define rmb() asm volatile("bcr 15,0" ::: "memory")
12310e9c MS	52	#endif
12310e9c MS	53
febe8345	54	#ifdef __sh__
febe8345	55	#if defined(__SH4A__) \|\| defined(__SH5__)
a94d342b PZ	56	# define mb() asm volatile("synco" ::: "memory")
a94d342b PZ	57	# define wmb() asm volatile("synco" ::: "memory")
febe8345 PM	58	# define rmb() asm volatile("synco" ::: "memory")
febe8345 PM	59	#else
a94d342b PZ	60	# define mb() asm volatile("" ::: "memory")
a94d342b PZ	61	# define wmb() asm volatile("" ::: "memory")
febe8345 PM	62	# define rmb() asm volatile("" ::: "memory")
febe8345 PM	63	#endif
fbe96f29	64	#define CPUINFO_PROC "cpu type"
febe8345 PM	65	#endif
febe8345 PM	66
2d4618dc	67	#ifdef __hppa__
a94d342b PZ	68	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	69	#define wmb() asm volatile("" ::: "memory")
2d4618dc	70	#define rmb() asm volatile("" ::: "memory")
fbe96f29	71	#define CPUINFO_PROC "cpu"
2d4618dc KM	72	#endif
2d4618dc KM	73
825c9fb4	74	#ifdef __sparc__
a94d342b PZ	75	#ifdef __LP64__
	76	#define mb() asm volatile("ba,pt %%xcc, 1f\n" \
	77	"membar #StoreLoad\n" \
	78	"1:\n":::"memory")
	79	#else
	80	#define mb() asm volatile("":::"memory")
	81	#endif
	82	#define wmb() asm volatile("":::"memory")
825c9fb4	83	#define rmb() asm volatile("":::"memory")
fbe96f29	84	#define CPUINFO_PROC "cpu"
825c9fb4 JA	85	#endif
825c9fb4 JA	86
fcd14b32	87	#ifdef __alpha__
a94d342b PZ	88	#define mb() asm volatile("mb" ::: "memory")
a94d342b PZ	89	#define wmb() asm volatile("wmb" ::: "memory")
fcd14b32	90	#define rmb() asm volatile("mb" ::: "memory")
fbe96f29	91	#define CPUINFO_PROC "cpu model"
fcd14b32 MC	92	#endif
fcd14b32 MC	93
11ada26c	94	#ifdef __ia64__
a94d342b PZ	95	#define mb() asm volatile ("mf" ::: "memory")
a94d342b PZ	96	#define wmb() asm volatile ("mf" ::: "memory")
11ada26c LT	97	#define rmb() asm volatile ("mf" ::: "memory")
11ada26c LT	98	#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
fbe96f29	99	#define CPUINFO_PROC "model name"
11ada26c LT	100	#endif
11ada26c LT	101
58e9f941	102	#ifdef __arm__
58e9f941 JI	103	/*
	104	* Use the __kuser_memory_barrier helper in the CPU helper page. See
	105	* arch/arm/kernel/entry-armv.S in the kernel source for details.
	106	*/
a94d342b PZ	107	#define mb() ((void(*)(void))0xffff0fa0)()
a94d342b PZ	108	#define wmb() ((void(*)(void))0xffff0fa0)()
da7196e1	109	#define rmb() ((void(*)(void))0xffff0fa0)()
fbe96f29	110	#define CPUINFO_PROC "Processor"
58e9f941 JI	111	#endif
58e9f941 JI	112
03089688	113	#ifdef __aarch64__
a94d342b	114	#define mb() asm volatile("dmb ish" ::: "memory")
f428ebd1 PZ	115	#define wmb() asm volatile("dmb ishst" ::: "memory")
f428ebd1 PZ	116	#define rmb() asm volatile("dmb ishld" ::: "memory")
03089688 WD	117	#define cpu_relax() asm volatile("yield" ::: "memory")
	118	#endif
	119
c1e028ef	120	#ifdef __mips__
a94d342b	121	#define mb() asm volatile( \
c1e028ef DCZ	122	".set mips2\n\t" \
	123	"sync\n\t" \
	124	".set mips0" \
	125	: /* no output */ \
	126	: /* no input */ \
	127	: "memory")
a94d342b PZ	128	#define wmb() mb()
a94d342b PZ	129	#define rmb() mb()
fbe96f29	130	#define CPUINFO_PROC "cpu model"
c1e028ef DCZ	131	#endif
c1e028ef DCZ	132
9854783e	133	#ifdef __arc__
a94d342b PZ	134	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	135	#define wmb() asm volatile("" ::: "memory")
9854783e	136	#define rmb() asm volatile("" ::: "memory")
9854783e VG	137	#define CPUINFO_PROC "Processor"
	138	#endif
	139
1bea5b81	140	#ifdef __metag__
a94d342b PZ	141	#define mb() asm volatile("" ::: "memory")
a94d342b PZ	142	#define wmb() asm volatile("" ::: "memory")
1bea5b81	143	#define rmb() asm volatile("" ::: "memory")
1bea5b81 JH	144	#define CPUINFO_PROC "CPU"
	145	#endif
	146
3a46817f BS	147	#ifdef __xtensa__
	148	#define mb() asm volatile("memw" ::: "memory")
	149	#define wmb() asm volatile("memw" ::: "memory")
	150	#define rmb() asm volatile("" ::: "memory")
	151	#define CPUINFO_PROC "core ID"
	152	#endif
	153
620830b6 ZL	154	#ifdef __tile__
	155	#define mb() asm volatile ("mf" ::: "memory")
	156	#define wmb() asm volatile ("mf" ::: "memory")
	157	#define rmb() asm volatile ("mf" ::: "memory")
	158	#define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory")
	159	#define CPUINFO_PROC "model name"
	160	#endif
	161
a94d342b PZ	162	#define barrier() asm volatile ("" ::: "memory")
	163
	164	#ifndef cpu_relax
	165	#define cpu_relax() barrier()
	166	#endif
	167
	168	#define ACCESS_ONCE(x) ((volatile typeof(x) )&(x))
	169
	170
1a482f38 PZ	171	#include <time.h>
	172	#include <unistd.h>
	173	#include <sys/types.h>
	174	#include <sys/syscall.h>
	175
d944c4ee	176	#include <linux/types.h>
d2709c7c	177	#include <linux/perf_event.h>
1a482f38	178
6eda5838	179	/*
cdd6c482	180	* prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
6eda5838 TG	181	* counters in the current task.
6eda5838 TG	182	*/
cdd6c482 IM	183	#define PR_TASK_PERF_EVENTS_DISABLE 31
cdd6c482 IM	184	#define PR_TASK_PERF_EVENTS_ENABLE 32
6eda5838	185
a92e7023 TG	186	#ifndef NSEC_PER_SEC
	187	# define NSEC_PER_SEC 1000000000ULL
	188	#endif
70f7b4a7 DA	189	#ifndef NSEC_PER_USEC
	190	# define NSEC_PER_USEC 1000ULL
	191	#endif
a92e7023 TG	192
	193	static inline unsigned long long rdclock(void)
	194	{
	195	struct timespec ts;
	196
	197	clock_gettime(CLOCK_MONOTONIC, &ts);
	198	return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
	199	}
6eda5838 TG	200
	201	/*
	202	* Pick up some kernel type conventions:
	203	*/
6eda5838 TG	204	#define asmlinkage
6eda5838 TG	205
6eda5838 TG	206	#define unlikely(x) __builtin_expect(!!(x), 0)
	207	#define min(x, y) ({ \
	208	typeof(x) _min1 = (x); \
	209	typeof(y) _min2 = (y); \
	210	(void) (&_min1 == &_min2); \
	211	_min1 < _min2 ? _min1 : _min2; })
	212
52502bf2 JO	213	extern bool test_attr__enabled;
	214	void test_attr__init(void);
	215	void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu,
	216	int fd, int group_fd, unsigned long flags);
	217
6eda5838	218	static inline int
cdd6c482	219	sys_perf_event_open(struct perf_event_attr *attr,
6eda5838 TG	220	pid_t pid, int cpu, int group_fd,
	221	unsigned long flags)
	222	{
52502bf2 JO	223	int fd;
	224
	225	fd = syscall(__NR_perf_event_open, attr, pid, cpu,
	226	group_fd, flags);
	227
	228	if (unlikely(test_attr__enabled))
	229	test_attr__open(attr, pid, cpu, fd, group_fd, flags);
	230
	231	return fd;
6eda5838 TG	232	}
6eda5838 TG	233
85a9f920 IM	234	#define MAX_COUNTERS 256
85a9f920 IM	235	#define MAX_NR_CPUS 256
6eda5838	236
8cb76d99 FW	237	struct ip_callchain {
	238	u64 nr;
	239	u64 ips[0];
f5970550 PZ	240	};
f5970550 PZ	241
b5387528 RAV	242	struct branch_flags {
	243	u64 mispred:1;
	244	u64 predicted:1;
f5d05bce AK	245	u64 in_tx:1;
	246	u64 abort:1;
	247	u64 reserved:60;
b5387528 RAV	248	};
	249
	250	struct branch_entry {
	251	u64 from;
	252	u64 to;
	253	struct branch_flags flags;
	254	};
	255
	256	struct branch_stack {
	257	u64 nr;
	258	struct branch_entry entries[0];
	259	};
	260
70cb4e96	261	extern const char *input_name;
8035458f	262	extern bool perf_host, perf_guest;
fbe96f29	263	extern const char perf_version_string[];
a1645ce1	264
3af6e338 ACM	265	void pthread__unblock_sigwinch(void);
3af6e338 ACM	266
12864b31	267	#include "util/target.h"
bea03405	268
26d33022 JO	269	enum perf_call_graph_mode {
	270	CALLCHAIN_NONE,
	271	CALLCHAIN_FP,
a601fdff JO	272	CALLCHAIN_DWARF,
a601fdff JO	273	CALLCHAIN_MAX
26d33022 JO	274	};
26d33022 JO	275
b4006796	276	struct record_opts {
602ad878	277	struct target target;
26d33022	278	int call_graph;
eb853e80	279	bool call_graph_enabled;
ed80f581	280	bool group;
0f82ebc4	281	bool inherit_stat;
509051ea	282	bool no_buffering;
0f82ebc4	283	bool no_inherit;
69e7e5b0	284	bool no_inherit_set;
0f82ebc4 ACM	285	bool no_samples;
	286	bool raw_samples;
	287	bool sample_address;
05484298	288	bool sample_weight;
0f82ebc4	289	bool sample_time;
3e76ac78	290	bool period;
0f82ebc4	291	unsigned int freq;
01c2d99b	292	unsigned int mmap_pages;
0f82ebc4	293	unsigned int user_freq;
a00dc319	294	u64 branch_stack;
0f82ebc4 ACM	295	u64 default_interval;
0f82ebc4 ACM	296	u64 user_interval;
26d33022	297	u16 stack_dump_size;
475eeab9	298	bool sample_transaction;
6619a53e	299	unsigned initial_delay;
0f82ebc4 ACM	300	};
0f82ebc4 ACM	301
6eda5838	302	#endif