[deliverable/linux.git] / tools / perf / util / stat-shadow.c

#include <stdio.h>
#include "evsel.h"
#include "stat.h"
#include "color.h"
#include "pmu.h"

enum {
	CTX_BIT_USER	= 1 << 0,
	CTX_BIT_KERNEL	= 1 << 1,
	CTX_BIT_HV	= 1 << 2,
	CTX_BIT_HOST	= 1 << 3,
	CTX_BIT_IDLE	= 1 << 4,
	CTX_BIT_MAX	= 1 << 5,
};

#define NUM_CTX CTX_BIT_MAX

/*
 * AGGR_GLOBAL: Use CPU 0
 * AGGR_SOCKET: Use first CPU of socket
 * AGGR_CORE: Use first CPU of core
 * AGGR_NONE: Use matching CPU
 * AGGR_THREAD: Not supported?
 */
static struct stats runtime_nsecs_stats[MAX_NR_CPUS];
static struct stats runtime_cycles_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_stalled_cycles_front_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_stalled_cycles_back_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_branches_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_cacherefs_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_l1_dcache_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_l1_icache_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_ll_cache_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_itlb_cache_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_dtlb_cache_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_cycles_in_tx_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_transaction_stats[NUM_CTX][MAX_NR_CPUS];
static struct stats runtime_elision_stats[NUM_CTX][MAX_NR_CPUS];
static bool have_frontend_stalled;

struct stats walltime_nsecs_stats;

void perf_stat__init_shadow_stats(void)
{
	have_frontend_stalled = pmu_have_event("cpu", "stalled-cycles-frontend");
}

static int evsel_context(struct perf_evsel *evsel)
{
	int ctx = 0;

	if (evsel->attr.exclude_kernel)
		ctx |= CTX_BIT_KERNEL;
	if (evsel->attr.exclude_user)
		ctx |= CTX_BIT_USER;
	if (evsel->attr.exclude_hv)
		ctx |= CTX_BIT_HV;
	if (evsel->attr.exclude_host)
		ctx |= CTX_BIT_HOST;
	if (evsel->attr.exclude_idle)
		ctx |= CTX_BIT_IDLE;

	return ctx;
}

void perf_stat__reset_shadow_stats(void)
{
	memset(runtime_nsecs_stats, 0, sizeof(runtime_nsecs_stats));
	memset(runtime_cycles_stats, 0, sizeof(runtime_cycles_stats));
	memset(runtime_stalled_cycles_front_stats, 0, sizeof(runtime_stalled_cycles_front_stats));
	memset(runtime_stalled_cycles_back_stats, 0, sizeof(runtime_stalled_cycles_back_stats));
	memset(runtime_branches_stats, 0, sizeof(runtime_branches_stats));
	memset(runtime_cacherefs_stats, 0, sizeof(runtime_cacherefs_stats));
	memset(runtime_l1_dcache_stats, 0, sizeof(runtime_l1_dcache_stats));
	memset(runtime_l1_icache_stats, 0, sizeof(runtime_l1_icache_stats));
	memset(runtime_ll_cache_stats, 0, sizeof(runtime_ll_cache_stats));
	memset(runtime_itlb_cache_stats, 0, sizeof(runtime_itlb_cache_stats));
	memset(runtime_dtlb_cache_stats, 0, sizeof(runtime_dtlb_cache_stats));
	memset(runtime_cycles_in_tx_stats, 0,
			sizeof(runtime_cycles_in_tx_stats));
	memset(runtime_transaction_stats, 0,
		sizeof(runtime_transaction_stats));
	memset(runtime_elision_stats, 0, sizeof(runtime_elision_stats));
	memset(&walltime_nsecs_stats, 0, sizeof(walltime_nsecs_stats));
}

/*
 * Update various tracking values we maintain to print
 * more semantic information such as miss/hit ratios,
 * instruction rates, etc:
 */
void perf_stat__update_shadow_stats(struct perf_evsel *counter, u64 *count,
				    int cpu)
{
	int ctx = evsel_context(counter);

	if (perf_evsel__match(counter, SOFTWARE, SW_TASK_CLOCK))
		update_stats(&runtime_nsecs_stats[cpu], count[0]);
	else if (perf_evsel__match(counter, HARDWARE, HW_CPU_CYCLES))
		update_stats(&runtime_cycles_stats[ctx][cpu], count[0]);
	else if (perf_stat_evsel__is(counter, CYCLES_IN_TX))
		update_stats(&runtime_cycles_in_tx_stats[ctx][cpu], count[0]);
	else if (perf_stat_evsel__is(counter, TRANSACTION_START))
		update_stats(&runtime_transaction_stats[ctx][cpu], count[0]);
	else if (perf_stat_evsel__is(counter, ELISION_START))
		update_stats(&runtime_elision_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND))
		update_stats(&runtime_stalled_cycles_front_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND))
		update_stats(&runtime_stalled_cycles_back_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS))
		update_stats(&runtime_branches_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES))
		update_stats(&runtime_cacherefs_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1D))
		update_stats(&runtime_l1_dcache_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1I))
		update_stats(&runtime_ll_cache_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_LL))
		update_stats(&runtime_ll_cache_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_DTLB))
		update_stats(&runtime_dtlb_cache_stats[ctx][cpu], count[0]);
	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_ITLB))
		update_stats(&runtime_itlb_cache_stats[ctx][cpu], count[0]);
}

/* used for get_ratio_color() */
enum grc_type {
	GRC_STALLED_CYCLES_FE,
	GRC_STALLED_CYCLES_BE,
	GRC_CACHE_MISSES,
	GRC_MAX_NR
};

static const char *get_ratio_color(enum grc_type type, double ratio)
{
	static const double grc_table[GRC_MAX_NR][3] = {
		[GRC_STALLED_CYCLES_FE] = { 50.0, 30.0, 10.0 },
		[GRC_STALLED_CYCLES_BE] = { 75.0, 50.0, 20.0 },
		[GRC_CACHE_MISSES] 	= { 20.0, 10.0, 5.0 },
	};
	const char *color = PERF_COLOR_NORMAL;

	if (ratio > grc_table[type][0])
		color = PERF_COLOR_RED;
	else if (ratio > grc_table[type][1])
		color = PERF_COLOR_MAGENTA;
	else if (ratio > grc_table[type][2])
		color = PERF_COLOR_YELLOW;

	return color;
}

static void print_stalled_cycles_frontend(int cpu,
					  struct perf_evsel *evsel, double avg,
					  struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_STALLED_CYCLES_FE, ratio);

	if (ratio)
		out->print_metric(out->ctx, color, "%7.2f%%", "frontend cycles idle",
				  ratio);
	else
		out->print_metric(out->ctx, NULL, NULL, "frontend cycles idle", 0);
}

static void print_stalled_cycles_backend(int cpu,
					 struct perf_evsel *evsel, double avg,
					 struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_STALLED_CYCLES_BE, ratio);

	out->print_metric(out->ctx, color, "%6.2f%%", "backend cycles idle", ratio);
}

static void print_branch_misses(int cpu,
				struct perf_evsel *evsel,
				double avg,
				struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_branches_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(out->ctx, color, "%7.2f%%", "of all branches", ratio);
}

static void print_l1_dcache_misses(int cpu,
				   struct perf_evsel *evsel,
				   double avg,
				   struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_l1_dcache_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(out->ctx, color, "%7.2f%%", "of all L1-dcache hits", ratio);
}

static void print_l1_icache_misses(int cpu,
				   struct perf_evsel *evsel,
				   double avg,
				   struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_l1_icache_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	out->print_metric(out->ctx, color, "%7.2f%%", "of all L1-icache hits", ratio);
}

static void print_dtlb_cache_misses(int cpu,
				    struct perf_evsel *evsel,
				    double avg,
				    struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_dtlb_cache_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	out->print_metric(out->ctx, color, "%7.2f%%", "of all dTLB cache hits", ratio);
}

static void print_itlb_cache_misses(int cpu,
				    struct perf_evsel *evsel,
				    double avg,
				    struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_itlb_cache_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	out->print_metric(out->ctx, color, "%7.2f%%", "of all iTLB cache hits", ratio);
}

static void print_ll_cache_misses(int cpu,
				  struct perf_evsel *evsel,
				  double avg,
				  struct perf_stat_output_ctx *out)
{
	double total, ratio = 0.0;
	const char *color;
	int ctx = evsel_context(evsel);

	total = avg_stats(&runtime_ll_cache_stats[ctx][cpu]);

	if (total)
		ratio = avg / total * 100.0;

	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	out->print_metric(out->ctx, color, "%7.2f%%", "of all LL-cache hits", ratio);
}

void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
				   double avg, int cpu,
				   struct perf_stat_output_ctx *out)
{
	void *ctxp = out->ctx;
	print_metric_t print_metric = out->print_metric;
	double total, ratio = 0.0, total2;
	int ctx = evsel_context(evsel);

	if (perf_evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) {
		total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
		if (total) {
			ratio = avg / total;
			print_metric(ctxp, NULL, "%7.2f ",
					"insn per cycle", ratio);
		} else {
			print_metric(ctxp, NULL, NULL, "insn per cycle", 0);
		}
		total = avg_stats(&runtime_stalled_cycles_front_stats[ctx][cpu]);
		total = max(total, avg_stats(&runtime_stalled_cycles_back_stats[ctx][cpu]));

		if (total && avg) {
			out->new_line(ctxp);
			ratio = total / avg;
			print_metric(ctxp, NULL, "%7.2f ",
					"stalled cycles per insn",
					ratio);
		} else if (have_frontend_stalled) {
			print_metric(ctxp, NULL, NULL,
				     "stalled cycles per insn", 0);
		}
	} else if (perf_evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) {
		if (runtime_branches_stats[ctx][cpu].n != 0)
			print_branch_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all branches", 0);
	} else if (
		evsel->attr.type == PERF_TYPE_HW_CACHE &&
		evsel->attr.config ==  ( PERF_COUNT_HW_CACHE_L1D |
					((PERF_COUNT_HW_CACHE_OP_READ) << 8) |
					 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
		if (runtime_l1_dcache_stats[ctx][cpu].n != 0)
			print_l1_dcache_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all L1-dcache hits", 0);
	} else if (
		evsel->attr.type == PERF_TYPE_HW_CACHE &&
		evsel->attr.config ==  ( PERF_COUNT_HW_CACHE_L1I |
					((PERF_COUNT_HW_CACHE_OP_READ) << 8) |
					 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
		if (runtime_l1_icache_stats[ctx][cpu].n != 0)
			print_l1_icache_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all L1-icache hits", 0);
	} else if (
		evsel->attr.type == PERF_TYPE_HW_CACHE &&
		evsel->attr.config ==  ( PERF_COUNT_HW_CACHE_DTLB |
					((PERF_COUNT_HW_CACHE_OP_READ) << 8) |
					 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
		if (runtime_dtlb_cache_stats[ctx][cpu].n != 0)
			print_dtlb_cache_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all dTLB cache hits", 0);
	} else if (
		evsel->attr.type == PERF_TYPE_HW_CACHE &&
		evsel->attr.config ==  ( PERF_COUNT_HW_CACHE_ITLB |
					((PERF_COUNT_HW_CACHE_OP_READ) << 8) |
					 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
		if (runtime_itlb_cache_stats[ctx][cpu].n != 0)
			print_itlb_cache_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all iTLB cache hits", 0);
	} else if (
		evsel->attr.type == PERF_TYPE_HW_CACHE &&
		evsel->attr.config ==  ( PERF_COUNT_HW_CACHE_LL |
					((PERF_COUNT_HW_CACHE_OP_READ) << 8) |
					 ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
		if (runtime_ll_cache_stats[ctx][cpu].n != 0)
			print_ll_cache_misses(cpu, evsel, avg, out);
		else
			print_metric(ctxp, NULL, NULL, "of all LL-cache hits", 0);
	} else if (perf_evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {
		total = avg_stats(&runtime_cacherefs_stats[ctx][cpu]);

		if (total)
			ratio = avg * 100 / total;

		if (runtime_cacherefs_stats[ctx][cpu].n != 0)
			print_metric(ctxp, NULL, "%8.3f %%",
				     "of all cache refs", ratio);
		else
			print_metric(ctxp, NULL, NULL, "of all cache refs", 0);
	} else if (perf_evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) {
		print_stalled_cycles_frontend(cpu, evsel, avg, out);
	} else if (perf_evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) {
		print_stalled_cycles_backend(cpu, evsel, avg, out);
	} else if (perf_evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) {
		total = avg_stats(&runtime_nsecs_stats[cpu]);

		if (total) {
			ratio = avg / total;
			print_metric(ctxp, NULL, "%8.3f", "GHz", ratio);
		} else {
			print_metric(ctxp, NULL, NULL, "Ghz", 0);
		}
	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX)) {
		total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
		if (total)
			print_metric(ctxp, NULL,
					"%7.2f%%", "transactional cycles",
					100.0 * (avg / total));
		else
			print_metric(ctxp, NULL, NULL, "transactional cycles",
				     0);
	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX_CP)) {
		total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
		total2 = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);
		if (total2 < avg)
			total2 = avg;
		if (total)
			print_metric(ctxp, NULL, "%7.2f%%", "aborted cycles",
				100.0 * ((total2-avg) / total));
		else
			print_metric(ctxp, NULL, NULL, "aborted cycles", 0);
	} else if (perf_stat_evsel__is(evsel, TRANSACTION_START)) {
		total = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);

		if (avg)
			ratio = total / avg;

		if (runtime_cycles_in_tx_stats[ctx][cpu].n != 0)
			print_metric(ctxp, NULL, "%8.0f",
				     "cycles / transaction", ratio);
		else
			print_metric(ctxp, NULL, NULL, "cycles / transaction",
				     0);
	} else if (perf_stat_evsel__is(evsel, ELISION_START)) {
		total = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);

		if (avg)
			ratio = total / avg;

		print_metric(ctxp, NULL, "%8.0f", "cycles / elision", ratio);
	} else if (perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK)) {
		if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0)
			print_metric(ctxp, NULL, "%8.3f", "CPUs utilized",
				     avg / ratio);
		else
			print_metric(ctxp, NULL, NULL, "CPUs utilized", 0);
	} else if (runtime_nsecs_stats[cpu].n != 0) {
		char unit = 'M';
		char unit_buf[10];

		total = avg_stats(&runtime_nsecs_stats[cpu]);

		if (total)
			ratio = 1000.0 * avg / total;
		if (ratio < 0.001) {
			ratio *= 1000;
			unit = 'K';
		}
		snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit);
		print_metric(ctxp, NULL, "%8.3f", unit_buf, ratio);
	} else {
		print_metric(ctxp, NULL, NULL, NULL, 0);
	}
}
Commit	Line	Data
f87027b9 JO	1	#include <stdio.h>
	2	#include "evsel.h"
	3	#include "stat.h"
	4	#include "color.h"
fb4605ba	5	#include "pmu.h"
f87027b9 JO	6
	7	enum {
	8	CTX_BIT_USER = 1 << 0,
	9	CTX_BIT_KERNEL = 1 << 1,
	10	CTX_BIT_HV = 1 << 2,
	11	CTX_BIT_HOST = 1 << 3,
	12	CTX_BIT_IDLE = 1 << 4,
	13	CTX_BIT_MAX = 1 << 5,
	14	};
	15
	16	#define NUM_CTX CTX_BIT_MAX
	17
44d49a60 AK	18	/*
	19	* AGGR_GLOBAL: Use CPU 0
	20	* AGGR_SOCKET: Use first CPU of socket
	21	* AGGR_CORE: Use first CPU of core
	22	* AGGR_NONE: Use matching CPU
	23	* AGGR_THREAD: Not supported?
	24	*/
f87027b9 JO	25	static struct stats runtime_nsecs_stats[MAX_NR_CPUS];
	26	static struct stats runtime_cycles_stats[NUM_CTX][MAX_NR_CPUS];
	27	static struct stats runtime_stalled_cycles_front_stats[NUM_CTX][MAX_NR_CPUS];
	28	static struct stats runtime_stalled_cycles_back_stats[NUM_CTX][MAX_NR_CPUS];
	29	static struct stats runtime_branches_stats[NUM_CTX][MAX_NR_CPUS];
	30	static struct stats runtime_cacherefs_stats[NUM_CTX][MAX_NR_CPUS];
	31	static struct stats runtime_l1_dcache_stats[NUM_CTX][MAX_NR_CPUS];
	32	static struct stats runtime_l1_icache_stats[NUM_CTX][MAX_NR_CPUS];
	33	static struct stats runtime_ll_cache_stats[NUM_CTX][MAX_NR_CPUS];
	34	static struct stats runtime_itlb_cache_stats[NUM_CTX][MAX_NR_CPUS];
	35	static struct stats runtime_dtlb_cache_stats[NUM_CTX][MAX_NR_CPUS];
	36	static struct stats runtime_cycles_in_tx_stats[NUM_CTX][MAX_NR_CPUS];
	37	static struct stats runtime_transaction_stats[NUM_CTX][MAX_NR_CPUS];
	38	static struct stats runtime_elision_stats[NUM_CTX][MAX_NR_CPUS];
fb4605ba	39	static bool have_frontend_stalled;
f87027b9 JO	40
	41	struct stats walltime_nsecs_stats;
	42
fb4605ba AK	43	void perf_stat__init_shadow_stats(void)
	44	{
	45	have_frontend_stalled = pmu_have_event("cpu", "stalled-cycles-frontend");
	46	}
	47
f87027b9 JO	48	static int evsel_context(struct perf_evsel *evsel)
	49	{
	50	int ctx = 0;
	51
	52	if (evsel->attr.exclude_kernel)
	53	ctx \|= CTX_BIT_KERNEL;
	54	if (evsel->attr.exclude_user)
	55	ctx \|= CTX_BIT_USER;
	56	if (evsel->attr.exclude_hv)
	57	ctx \|= CTX_BIT_HV;
	58	if (evsel->attr.exclude_host)
	59	ctx \|= CTX_BIT_HOST;
	60	if (evsel->attr.exclude_idle)
	61	ctx \|= CTX_BIT_IDLE;
	62
	63	return ctx;
	64	}
	65
	66	void perf_stat__reset_shadow_stats(void)
	67	{
	68	memset(runtime_nsecs_stats, 0, sizeof(runtime_nsecs_stats));
	69	memset(runtime_cycles_stats, 0, sizeof(runtime_cycles_stats));
	70	memset(runtime_stalled_cycles_front_stats, 0, sizeof(runtime_stalled_cycles_front_stats));
	71	memset(runtime_stalled_cycles_back_stats, 0, sizeof(runtime_stalled_cycles_back_stats));
	72	memset(runtime_branches_stats, 0, sizeof(runtime_branches_stats));
	73	memset(runtime_cacherefs_stats, 0, sizeof(runtime_cacherefs_stats));
	74	memset(runtime_l1_dcache_stats, 0, sizeof(runtime_l1_dcache_stats));
	75	memset(runtime_l1_icache_stats, 0, sizeof(runtime_l1_icache_stats));
	76	memset(runtime_ll_cache_stats, 0, sizeof(runtime_ll_cache_stats));
	77	memset(runtime_itlb_cache_stats, 0, sizeof(runtime_itlb_cache_stats));
	78	memset(runtime_dtlb_cache_stats, 0, sizeof(runtime_dtlb_cache_stats));
	79	memset(runtime_cycles_in_tx_stats, 0,
	80	sizeof(runtime_cycles_in_tx_stats));
	81	memset(runtime_transaction_stats, 0,
	82	sizeof(runtime_transaction_stats));
	83	memset(runtime_elision_stats, 0, sizeof(runtime_elision_stats));
	84	memset(&walltime_nsecs_stats, 0, sizeof(walltime_nsecs_stats));
	85	}
	86
	87	/*
	88	* Update various tracking values we maintain to print
	89	* more semantic information such as miss/hit ratios,
	90	* instruction rates, etc:
	91	*/
	92	void perf_stat__update_shadow_stats(struct perf_evsel counter, u64 count,
	93	int cpu)
	94	{
	95	int ctx = evsel_context(counter);
	96
	97	if (perf_evsel__match(counter, SOFTWARE, SW_TASK_CLOCK))
	98	update_stats(&runtime_nsecs_stats[cpu], count[0]);
	99	else if (perf_evsel__match(counter, HARDWARE, HW_CPU_CYCLES))
	100	update_stats(&runtime_cycles_stats[ctx][cpu], count[0]);
	101	else if (perf_stat_evsel__is(counter, CYCLES_IN_TX))
54976285	102	update_stats(&runtime_cycles_in_tx_stats[ctx][cpu], count[0]);
f87027b9 JO	103	else if (perf_stat_evsel__is(counter, TRANSACTION_START))
	104	update_stats(&runtime_transaction_stats[ctx][cpu], count[0]);
	105	else if (perf_stat_evsel__is(counter, ELISION_START))
	106	update_stats(&runtime_elision_stats[ctx][cpu], count[0]);
	107	else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND))
	108	update_stats(&runtime_stalled_cycles_front_stats[ctx][cpu], count[0]);
	109	else if (perf_evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND))
	110	update_stats(&runtime_stalled_cycles_back_stats[ctx][cpu], count[0]);
	111	else if (perf_evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS))
	112	update_stats(&runtime_branches_stats[ctx][cpu], count[0]);
	113	else if (perf_evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES))
	114	update_stats(&runtime_cacherefs_stats[ctx][cpu], count[0]);
	115	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1D))
	116	update_stats(&runtime_l1_dcache_stats[ctx][cpu], count[0]);
	117	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_L1I))
	118	update_stats(&runtime_ll_cache_stats[ctx][cpu], count[0]);
	119	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_LL))
	120	update_stats(&runtime_ll_cache_stats[ctx][cpu], count[0]);
	121	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_DTLB))
	122	update_stats(&runtime_dtlb_cache_stats[ctx][cpu], count[0]);
	123	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_ITLB))
	124	update_stats(&runtime_itlb_cache_stats[ctx][cpu], count[0]);
	125	}
	126
	127	/* used for get_ratio_color() */
	128	enum grc_type {
	129	GRC_STALLED_CYCLES_FE,
	130	GRC_STALLED_CYCLES_BE,
	131	GRC_CACHE_MISSES,
	132	GRC_MAX_NR
	133	};
	134
	135	static const char *get_ratio_color(enum grc_type type, double ratio)
	136	{
	137	static const double grc_table[GRC_MAX_NR][3] = {
	138	[GRC_STALLED_CYCLES_FE] = { 50.0, 30.0, 10.0 },
	139	[GRC_STALLED_CYCLES_BE] = { 75.0, 50.0, 20.0 },
	140	[GRC_CACHE_MISSES] = { 20.0, 10.0, 5.0 },
	141	};
	142	const char *color = PERF_COLOR_NORMAL;
	143
	144	if (ratio > grc_table[type][0])
	145	color = PERF_COLOR_RED;
	146	else if (ratio > grc_table[type][1])
	147	color = PERF_COLOR_MAGENTA;
	148	else if (ratio > grc_table[type][2])
	149	color = PERF_COLOR_YELLOW;
	150
	151	return color;
	152	}
	153
140aeadc	154	static void print_stalled_cycles_frontend(int cpu,
b8f8eb84	155	struct perf_evsel *evsel, double avg,
140aeadc	156	struct perf_stat_output_ctx *out)
f87027b9 JO	157	{
	158	double total, ratio = 0.0;
	159	const char *color;
	160	int ctx = evsel_context(evsel);
	161
	162	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
	163
	164	if (total)
	165	ratio = avg / total * 100.0;
	166
	167	color = get_ratio_color(GRC_STALLED_CYCLES_FE, ratio);
	168
140aeadc AK	169	if (ratio)
	170	out->print_metric(out->ctx, color, "%7.2f%%", "frontend cycles idle",
	171	ratio);
	172	else
	173	out->print_metric(out->ctx, NULL, NULL, "frontend cycles idle", 0);
f87027b9 JO	174	}
f87027b9 JO	175
140aeadc	176	static void print_stalled_cycles_backend(int cpu,
b8f8eb84	177	struct perf_evsel *evsel, double avg,
140aeadc	178	struct perf_stat_output_ctx *out)
f87027b9 JO	179	{
	180	double total, ratio = 0.0;
	181	const char *color;
	182	int ctx = evsel_context(evsel);
	183
	184	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
	185
	186	if (total)
	187	ratio = avg / total * 100.0;
	188
	189	color = get_ratio_color(GRC_STALLED_CYCLES_BE, ratio);
	190
140aeadc	191	out->print_metric(out->ctx, color, "%6.2f%%", "backend cycles idle", ratio);
f87027b9 JO	192	}
f87027b9 JO	193
140aeadc	194	static void print_branch_misses(int cpu,
b8f8eb84	195	struct perf_evsel *evsel,
140aeadc AK	196	double avg,
140aeadc AK	197	struct perf_stat_output_ctx *out)
f87027b9 JO	198	{
	199	double total, ratio = 0.0;
	200	const char *color;
	201	int ctx = evsel_context(evsel);
	202
	203	total = avg_stats(&runtime_branches_stats[ctx][cpu]);
	204
	205	if (total)
	206	ratio = avg / total * 100.0;
	207
	208	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	209
140aeadc	210	out->print_metric(out->ctx, color, "%7.2f%%", "of all branches", ratio);
f87027b9 JO	211	}
f87027b9 JO	212
140aeadc	213	static void print_l1_dcache_misses(int cpu,
b8f8eb84	214	struct perf_evsel *evsel,
140aeadc AK	215	double avg,
140aeadc AK	216	struct perf_stat_output_ctx *out)
f87027b9 JO	217	{
	218	double total, ratio = 0.0;
	219	const char *color;
	220	int ctx = evsel_context(evsel);
	221
	222	total = avg_stats(&runtime_l1_dcache_stats[ctx][cpu]);
	223
	224	if (total)
	225	ratio = avg / total * 100.0;
	226
	227	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
	228
140aeadc	229	out->print_metric(out->ctx, color, "%7.2f%%", "of all L1-dcache hits", ratio);
f87027b9 JO	230	}
f87027b9 JO	231
140aeadc	232	static void print_l1_icache_misses(int cpu,
b8f8eb84	233	struct perf_evsel *evsel,
140aeadc AK	234	double avg,
140aeadc AK	235	struct perf_stat_output_ctx *out)
f87027b9 JO	236	{
	237	double total, ratio = 0.0;
	238	const char *color;
	239	int ctx = evsel_context(evsel);
	240
	241	total = avg_stats(&runtime_l1_icache_stats[ctx][cpu]);
	242
	243	if (total)
	244	ratio = avg / total * 100.0;
	245
	246	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
140aeadc	247	out->print_metric(out->ctx, color, "%7.2f%%", "of all L1-icache hits", ratio);
f87027b9 JO	248	}
f87027b9 JO	249
140aeadc	250	static void print_dtlb_cache_misses(int cpu,
b8f8eb84	251	struct perf_evsel *evsel,
140aeadc AK	252	double avg,
140aeadc AK	253	struct perf_stat_output_ctx *out)
f87027b9 JO	254	{
	255	double total, ratio = 0.0;
	256	const char *color;
	257	int ctx = evsel_context(evsel);
	258
	259	total = avg_stats(&runtime_dtlb_cache_stats[ctx][cpu]);
	260
	261	if (total)
	262	ratio = avg / total * 100.0;
	263
	264	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
140aeadc	265	out->print_metric(out->ctx, color, "%7.2f%%", "of all dTLB cache hits", ratio);
f87027b9 JO	266	}
f87027b9 JO	267
140aeadc	268	static void print_itlb_cache_misses(int cpu,
b8f8eb84	269	struct perf_evsel *evsel,
140aeadc AK	270	double avg,
140aeadc AK	271	struct perf_stat_output_ctx *out)
f87027b9 JO	272	{
	273	double total, ratio = 0.0;
	274	const char *color;
	275	int ctx = evsel_context(evsel);
	276
	277	total = avg_stats(&runtime_itlb_cache_stats[ctx][cpu]);
	278
	279	if (total)
	280	ratio = avg / total * 100.0;
	281
	282	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
140aeadc	283	out->print_metric(out->ctx, color, "%7.2f%%", "of all iTLB cache hits", ratio);
f87027b9 JO	284	}
f87027b9 JO	285
140aeadc	286	static void print_ll_cache_misses(int cpu,
b8f8eb84	287	struct perf_evsel *evsel,
140aeadc AK	288	double avg,
140aeadc AK	289	struct perf_stat_output_ctx *out)
f87027b9 JO	290	{
	291	double total, ratio = 0.0;
	292	const char *color;
	293	int ctx = evsel_context(evsel);
	294
	295	total = avg_stats(&runtime_ll_cache_stats[ctx][cpu]);
	296
	297	if (total)
	298	ratio = avg / total * 100.0;
	299
	300	color = get_ratio_color(GRC_CACHE_MISSES, ratio);
140aeadc	301	out->print_metric(out->ctx, color, "%7.2f%%", "of all LL-cache hits", ratio);
f87027b9 JO	302	}
f87027b9 JO	303
140aeadc AK	304	void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
	305	double avg, int cpu,
	306	struct perf_stat_output_ctx *out)
f87027b9	307	{
140aeadc AK	308	void *ctxp = out->ctx;
140aeadc AK	309	print_metric_t print_metric = out->print_metric;
f87027b9 JO	310	double total, ratio = 0.0, total2;
	311	int ctx = evsel_context(evsel);
	312
	313	if (perf_evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) {
	314	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
	315	if (total) {
	316	ratio = avg / total;
140aeadc AK	317	print_metric(ctxp, NULL, "%7.2f ",
140aeadc AK	318	"insn per cycle", ratio);
f87027b9	319	} else {
140aeadc	320	print_metric(ctxp, NULL, NULL, "insn per cycle", 0);
f87027b9 JO	321	}
	322	total = avg_stats(&runtime_stalled_cycles_front_stats[ctx][cpu]);
	323	total = max(total, avg_stats(&runtime_stalled_cycles_back_stats[ctx][cpu]));
	324
	325	if (total && avg) {
92a61f64	326	out->new_line(ctxp);
f87027b9	327	ratio = total / avg;
140aeadc AK	328	print_metric(ctxp, NULL, "%7.2f ",
	329	"stalled cycles per insn",
	330	ratio);
fb4605ba	331	} else if (have_frontend_stalled) {
140aeadc AK	332	print_metric(ctxp, NULL, NULL,
140aeadc AK	333	"stalled cycles per insn", 0);
f87027b9	334	}
140aeadc AK	335	} else if (perf_evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) {
	336	if (runtime_branches_stats[ctx][cpu].n != 0)
	337	print_branch_misses(cpu, evsel, avg, out);
	338	else
	339	print_metric(ctxp, NULL, NULL, "of all branches", 0);
f87027b9 JO	340	} else if (
	341	evsel->attr.type == PERF_TYPE_HW_CACHE &&
	342	evsel->attr.config == ( PERF_COUNT_HW_CACHE_L1D \|
	343	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
140aeadc AK	344	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
	345	if (runtime_l1_dcache_stats[ctx][cpu].n != 0)
	346	print_l1_dcache_misses(cpu, evsel, avg, out);
	347	else
	348	print_metric(ctxp, NULL, NULL, "of all L1-dcache hits", 0);
f87027b9 JO	349	} else if (
	350	evsel->attr.type == PERF_TYPE_HW_CACHE &&
	351	evsel->attr.config == ( PERF_COUNT_HW_CACHE_L1I \|
	352	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
140aeadc AK	353	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
	354	if (runtime_l1_icache_stats[ctx][cpu].n != 0)
	355	print_l1_icache_misses(cpu, evsel, avg, out);
	356	else
	357	print_metric(ctxp, NULL, NULL, "of all L1-icache hits", 0);
f87027b9 JO	358	} else if (
	359	evsel->attr.type == PERF_TYPE_HW_CACHE &&
	360	evsel->attr.config == ( PERF_COUNT_HW_CACHE_DTLB \|
	361	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
140aeadc AK	362	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
	363	if (runtime_dtlb_cache_stats[ctx][cpu].n != 0)
	364	print_dtlb_cache_misses(cpu, evsel, avg, out);
	365	else
	366	print_metric(ctxp, NULL, NULL, "of all dTLB cache hits", 0);
f87027b9 JO	367	} else if (
	368	evsel->attr.type == PERF_TYPE_HW_CACHE &&
	369	evsel->attr.config == ( PERF_COUNT_HW_CACHE_ITLB \|
	370	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
140aeadc AK	371	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
	372	if (runtime_itlb_cache_stats[ctx][cpu].n != 0)
	373	print_itlb_cache_misses(cpu, evsel, avg, out);
	374	else
	375	print_metric(ctxp, NULL, NULL, "of all iTLB cache hits", 0);
f87027b9 JO	376	} else if (
	377	evsel->attr.type == PERF_TYPE_HW_CACHE &&
	378	evsel->attr.config == ( PERF_COUNT_HW_CACHE_LL \|
	379	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
140aeadc AK	380	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
	381	if (runtime_ll_cache_stats[ctx][cpu].n != 0)
	382	print_ll_cache_misses(cpu, evsel, avg, out);
	383	else
	384	print_metric(ctxp, NULL, NULL, "of all LL-cache hits", 0);
	385	} else if (perf_evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {
f87027b9 JO	386	total = avg_stats(&runtime_cacherefs_stats[ctx][cpu]);
	387
	388	if (total)
	389	ratio = avg * 100 / total;
	390
140aeadc AK	391	if (runtime_cacherefs_stats[ctx][cpu].n != 0)
	392	print_metric(ctxp, NULL, "%8.3f %%",
	393	"of all cache refs", ratio);
	394	else
	395	print_metric(ctxp, NULL, NULL, "of all cache refs", 0);
f87027b9	396	} else if (perf_evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) {
140aeadc	397	print_stalled_cycles_frontend(cpu, evsel, avg, out);
f87027b9	398	} else if (perf_evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) {
140aeadc	399	print_stalled_cycles_backend(cpu, evsel, avg, out);
f87027b9 JO	400	} else if (perf_evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) {
	401	total = avg_stats(&runtime_nsecs_stats[cpu]);
	402
	403	if (total) {
	404	ratio = avg / total;
140aeadc	405	print_metric(ctxp, NULL, "%8.3f", "GHz", ratio);
f87027b9	406	} else {
140aeadc	407	print_metric(ctxp, NULL, NULL, "Ghz", 0);
f87027b9 JO	408	}
	409	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX)) {
	410	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
	411	if (total)
140aeadc AK	412	print_metric(ctxp, NULL,
	413	"%7.2f%%", "transactional cycles",
	414	100.0 * (avg / total));
	415	else
	416	print_metric(ctxp, NULL, NULL, "transactional cycles",
	417	0);
f87027b9 JO	418	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX_CP)) {
	419	total = avg_stats(&runtime_cycles_stats[ctx][cpu]);
	420	total2 = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);
	421	if (total2 < avg)
	422	total2 = avg;
	423	if (total)
140aeadc	424	print_metric(ctxp, NULL, "%7.2f%%", "aborted cycles",
f87027b9	425	100.0 * ((total2-avg) / total));
140aeadc AK	426	else
	427	print_metric(ctxp, NULL, NULL, "aborted cycles", 0);
	428	} else if (perf_stat_evsel__is(evsel, TRANSACTION_START)) {
f87027b9 JO	429	total = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);
f87027b9 JO	430
54976285	431	if (avg)
f87027b9 JO	432	ratio = total / avg;
f87027b9 JO	433
140aeadc AK	434	if (runtime_cycles_in_tx_stats[ctx][cpu].n != 0)
	435	print_metric(ctxp, NULL, "%8.0f",
	436	"cycles / transaction", ratio);
	437	else
	438	print_metric(ctxp, NULL, NULL, "cycles / transaction",
	439	0);
	440	} else if (perf_stat_evsel__is(evsel, ELISION_START)) {
f87027b9 JO	441	total = avg_stats(&runtime_cycles_in_tx_stats[ctx][cpu]);
f87027b9 JO	442
54976285	443	if (avg)
f87027b9 JO	444	ratio = total / avg;
f87027b9 JO	445
140aeadc	446	print_metric(ctxp, NULL, "%8.0f", "cycles / elision", ratio);
4579ecc8 AK	447	} else if (perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK)) {
4579ecc8 AK	448	if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0)
140aeadc AK	449	print_metric(ctxp, NULL, "%8.3f", "CPUs utilized",
140aeadc AK	450	avg / ratio);
4579ecc8	451	else
140aeadc	452	print_metric(ctxp, NULL, NULL, "CPUs utilized", 0);
f87027b9 JO	453	} else if (runtime_nsecs_stats[cpu].n != 0) {
f87027b9 JO	454	char unit = 'M';
140aeadc	455	char unit_buf[10];
f87027b9 JO	456
	457	total = avg_stats(&runtime_nsecs_stats[cpu]);
	458
	459	if (total)
	460	ratio = 1000.0 * avg / total;
	461	if (ratio < 0.001) {
	462	ratio *= 1000;
	463	unit = 'K';
	464	}
140aeadc AK	465	snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit);
140aeadc AK	466	print_metric(ctxp, NULL, "%8.3f", unit_buf, ratio);
f87027b9	467	} else {
140aeadc	468	print_metric(ctxp, NULL, NULL, NULL, 0);
f87027b9 JO	469	}
f87027b9 JO	470	}