[deliverable/linux.git] / virt / kvm / arm / vgic-v2.c

/*
 * Copyright (C) 2012,2013 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/cpu.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>

#include <asm/kvm_emulate.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_mmu.h>

static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
{
	struct vgic_lr lr_desc;
	u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];

	lr_desc.irq	= val & GICH_LR_VIRTUALID;
	if (lr_desc.irq <= 15)
		lr_desc.source	= (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
	else
		lr_desc.source = 0;
	lr_desc.state	= 0;

	if (val & GICH_LR_PENDING_BIT)
		lr_desc.state |= LR_STATE_PENDING;
	if (val & GICH_LR_ACTIVE_BIT)
		lr_desc.state |= LR_STATE_ACTIVE;
	if (val & GICH_LR_EOI)
		lr_desc.state |= LR_EOI_INT;
	if (val & GICH_LR_HW) {
		lr_desc.state |= LR_HW;
		lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
	}

	return lr_desc;
}

static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
			   struct vgic_lr lr_desc)
{
	u32 lr_val;

	lr_val = lr_desc.irq;

	if (lr_desc.state & LR_STATE_PENDING)
		lr_val |= GICH_LR_PENDING_BIT;
	if (lr_desc.state & LR_STATE_ACTIVE)
		lr_val |= GICH_LR_ACTIVE_BIT;
	if (lr_desc.state & LR_EOI_INT)
		lr_val |= GICH_LR_EOI;

	if (lr_desc.state & LR_HW) {
		lr_val |= GICH_LR_HW;
		lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
	}

	if (lr_desc.irq < VGIC_NR_SGIS)
		lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);

	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;

	if (!(lr_desc.state & LR_STATE_MASK))
		vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr |= (1ULL << lr);
	else
		vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr &= ~(1ULL << lr);
}

static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
}

static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
}

static void vgic_v2_clear_eisr(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr = 0;
}

static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
{
	u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
	u32 ret = 0;

	if (misr & GICH_MISR_EOI)
		ret |= INT_STATUS_EOI;
	if (misr & GICH_MISR_U)
		ret |= INT_STATUS_UNDERFLOW;

	return ret;
}

static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr |= GICH_HCR_UIE;
}

static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
}

static void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;

	vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT;
	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT;
	vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT;
}

static void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
	vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK;
	vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK;
	vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;

	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
}

static void vgic_v2_enable(struct kvm_vcpu *vcpu)
{
	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;

	/* Get the show on the road... */
	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
}

static const struct vgic_ops vgic_v2_ops = {
	.get_lr			= vgic_v2_get_lr,
	.set_lr			= vgic_v2_set_lr,
	.get_elrsr		= vgic_v2_get_elrsr,
	.get_eisr		= vgic_v2_get_eisr,
	.clear_eisr		= vgic_v2_clear_eisr,
	.get_interrupt_status	= vgic_v2_get_interrupt_status,
	.enable_underflow	= vgic_v2_enable_underflow,
	.disable_underflow	= vgic_v2_disable_underflow,
	.get_vmcr		= vgic_v2_get_vmcr,
	.set_vmcr		= vgic_v2_set_vmcr,
	.enable			= vgic_v2_enable,
};

struct vgic_params __section(.hyp.text) vgic_v2_params;

static void vgic_cpu_init_lrs(void *params)
{
	struct vgic_params *vgic = params;
	int i;

	for (i = 0; i < vgic->nr_lr; i++)
		writel_relaxed(0, vgic->vctrl_base + GICH_LR0 + (i * 4));
}

/**
 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller
 * @gic_kvm_info:	pointer to the GIC description
 * @ops:		address of a pointer to the GICv2 operations
 * @params:		address of a pointer to HW-specific parameters
 *
 * Returns 0 if a GICv2 has been found, with the low level operations
 * in *ops and the HW parameters in *params. Returns an error code
 * otherwise.
 */
int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
		   const struct vgic_ops **ops,
		   const struct vgic_params **params)
{
	int ret;
	struct vgic_params *vgic = &vgic_v2_params;
	const struct resource *vctrl_res = &gic_kvm_info->vctrl;
	const struct resource *vcpu_res = &gic_kvm_info->vcpu;

	memset(vgic, 0, sizeof(*vgic));

	if (!gic_kvm_info->maint_irq) {
		kvm_err("error getting vgic maintenance irq\n");
		ret = -ENXIO;
		goto out;
	}
	vgic->maint_irq = gic_kvm_info->maint_irq;

	if (!gic_kvm_info->vctrl.start) {
		kvm_err("GICH not present in the firmware table\n");
		ret = -ENXIO;
		goto out;
	}

	vgic->vctrl_base = ioremap(gic_kvm_info->vctrl.start,
				   resource_size(&gic_kvm_info->vctrl));
	if (!vgic->vctrl_base) {
		kvm_err("Cannot ioremap GICH\n");
		ret = -ENOMEM;
		goto out;
	}

	vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
	vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;

	ret = create_hyp_io_mappings(vgic->vctrl_base,
				     vgic->vctrl_base + resource_size(vctrl_res),
				     vctrl_res->start);
	if (ret) {
		kvm_err("Cannot map VCTRL into hyp\n");
		goto out_unmap;
	}

	if (!PAGE_ALIGNED(vcpu_res->start)) {
		kvm_err("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)vcpu_res->start);
		ret = -ENXIO;
		goto out_unmap;
	}

	if (!PAGE_ALIGNED(resource_size(vcpu_res))) {
		kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(vcpu_res),
			PAGE_SIZE);
		ret = -ENXIO;
		goto out_unmap;
	}

	vgic->can_emulate_gicv2 = true;
	kvm_register_device_ops(&kvm_arm_vgic_v2_ops, KVM_DEV_TYPE_ARM_VGIC_V2);

	vgic->vcpu_base = vcpu_res->start;

	kvm_info("GICH base=0x%llx, GICV base=0x%llx, IRQ=%d\n",
		 gic_kvm_info->vctrl.start, vgic->vcpu_base, vgic->maint_irq);

	vgic->type = VGIC_V2;
	vgic->max_gic_vcpus = VGIC_V2_MAX_CPUS;

	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);

	*ops = &vgic_v2_ops;
	*params = vgic;
	goto out;

out_unmap:
	iounmap(vgic->vctrl_base);
out:
	return ret;
}
Commit	Line	Data
8f186d52 MZ	1	/*
	2	* Copyright (C) 2012,2013 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/cpu.h>
	19	#include <linux/kvm.h>
	20	#include <linux/kvm_host.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
8f186d52 MZ	23
	24	#include <linux/irqchip/arm-gic.h>
	25
	26	#include <asm/kvm_emulate.h>
	27	#include <asm/kvm_arm.h>
	28	#include <asm/kvm_mmu.h>
	29
	30	static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
	31	{
	32	struct vgic_lr lr_desc;
	33	u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
	34
	35	lr_desc.irq = val & GICH_LR_VIRTUALID;
	36	if (lr_desc.irq <= 15)
	37	lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
	38	else
	39	lr_desc.source = 0;
	40	lr_desc.state = 0;
	41
	42	if (val & GICH_LR_PENDING_BIT)
	43	lr_desc.state \|= LR_STATE_PENDING;
	44	if (val & GICH_LR_ACTIVE_BIT)
	45	lr_desc.state \|= LR_STATE_ACTIVE;
	46	if (val & GICH_LR_EOI)
	47	lr_desc.state \|= LR_EOI_INT;
fb182cf8 MZ	48	if (val & GICH_LR_HW) {
	49	lr_desc.state \|= LR_HW;
	50	lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
	51	}
8f186d52 MZ	52
	53	return lr_desc;
	54	}
	55
	56	static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
	57	struct vgic_lr lr_desc)
	58	{
fb182cf8 MZ	59	u32 lr_val;
	60
	61	lr_val = lr_desc.irq;
8f186d52 MZ	62
	63	if (lr_desc.state & LR_STATE_PENDING)
	64	lr_val \|= GICH_LR_PENDING_BIT;
	65	if (lr_desc.state & LR_STATE_ACTIVE)
	66	lr_val \|= GICH_LR_ACTIVE_BIT;
	67	if (lr_desc.state & LR_EOI_INT)
	68	lr_val \|= GICH_LR_EOI;
	69
fb182cf8 MZ	70	if (lr_desc.state & LR_HW) {
	71	lr_val \|= GICH_LR_HW;
	72	lr_val \|= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
	73	}
	74
	75	if (lr_desc.irq < VGIC_NR_SGIS)
	76	lr_val \|= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);
	77
8f186d52	78	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
8f186d52	79
8f186d52	80	if (!(lr_desc.state & LR_STATE_MASK))
2df36a5d	81	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr \|= (1ULL << lr);
ae705930 CD	82	else
ae705930 CD	83	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr &= ~(1ULL << lr);
8f186d52 MZ	84	}
	85
	86	static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
	87	{
2df36a5d	88	return vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
8f186d52 MZ	89	}
	90
	91	static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
	92	{
2df36a5d	93	return vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
8f186d52 MZ	94	}
8f186d52 MZ	95
ae705930 CD	96	static void vgic_v2_clear_eisr(struct kvm_vcpu *vcpu)
	97	{
	98	vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr = 0;
	99	}
	100
8f186d52 MZ	101	static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
	102	{
	103	u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
	104	u32 ret = 0;
	105
	106	if (misr & GICH_MISR_EOI)
	107	ret \|= INT_STATUS_EOI;
	108	if (misr & GICH_MISR_U)
	109	ret \|= INT_STATUS_UNDERFLOW;
	110
	111	return ret;
	112	}
	113
	114	static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu)
	115	{
	116	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr \|= GICH_HCR_UIE;
	117	}
	118
	119	static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu)
	120	{
	121	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
	122	}
	123
	124	static void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	125	{
	126	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
	127
	128	vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT;
	129	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT;
	130	vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT;
	131	vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT;
	132	}
	133
	134	static void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	135	{
	136	u32 vmcr;
	137
	138	vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
	139	vmcr \|= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK;
	140	vmcr \|= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK;
	141	vmcr \|= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
	142
	143	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
	144	}
	145
	146	static void vgic_v2_enable(struct kvm_vcpu *vcpu)
	147	{
	148	/*
	149	* By forcing VMCR to zero, the GIC will restore the binary
	150	* points to their reset values. Anything else resets to zero
	151	* anyway.
	152	*/
	153	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
c4cd4c16	154	vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
8f186d52 MZ	155
	156	/* Get the show on the road... */
	157	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
	158	}
	159
	160	static const struct vgic_ops vgic_v2_ops = {
	161	.get_lr = vgic_v2_get_lr,
	162	.set_lr = vgic_v2_set_lr,
8f186d52 MZ	163	.get_elrsr = vgic_v2_get_elrsr,
8f186d52 MZ	164	.get_eisr = vgic_v2_get_eisr,
ae705930	165	.clear_eisr = vgic_v2_clear_eisr,
8f186d52 MZ	166	.get_interrupt_status = vgic_v2_get_interrupt_status,
	167	.enable_underflow = vgic_v2_enable_underflow,
	168	.disable_underflow = vgic_v2_disable_underflow,
	169	.get_vmcr = vgic_v2_get_vmcr,
	170	.set_vmcr = vgic_v2_set_vmcr,
	171	.enable = vgic_v2_enable,
	172	};
	173
2db4c104	174	struct vgic_params __section(.hyp.text) vgic_v2_params;
8f186d52	175
d6400d77 MZ	176	static void vgic_cpu_init_lrs(void *params)
	177	{
	178	struct vgic_params *vgic = params;
	179	int i;
	180
	181	for (i = 0; i < vgic->nr_lr; i++)
	182	writel_relaxed(0, vgic->vctrl_base + GICH_LR0 + (i * 4));
	183	}
	184
8f186d52	185	/**
503a6286 JG	186	* vgic_v2_probe - probe for a GICv2 compatible interrupt controller
	187	* @gic_kvm_info: pointer to the GIC description
	188	* @ops: address of a pointer to the GICv2 operations
	189	* @params: address of a pointer to HW-specific parameters
8f186d52 MZ	190	*
	191	* Returns 0 if a GICv2 has been found, with the low level operations
	192	* in ops and the HW parameters in params. Returns an error code
	193	* otherwise.
	194	*/
503a6286 JG	195	int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
	196	const struct vgic_ops **ops,
	197	const struct vgic_params **params)
8f186d52 MZ	198	{
8f186d52 MZ	199	int ret;
8f186d52	200	struct vgic_params *vgic = &vgic_v2_params;
503a6286 JG	201	const struct resource *vctrl_res = &gic_kvm_info->vctrl;
503a6286 JG	202	const struct resource *vcpu_res = &gic_kvm_info->vcpu;
8f186d52	203
2db4c104 CD	204	memset(vgic, 0, sizeof(*vgic));
2db4c104 CD	205
503a6286 JG	206	if (!gic_kvm_info->maint_irq) {
503a6286 JG	207	kvm_err("error getting vgic maintenance irq\n");
8f186d52 MZ	208	ret = -ENXIO;
	209	goto out;
	210	}
503a6286	211	vgic->maint_irq = gic_kvm_info->maint_irq;
8f186d52	212
503a6286 JG	213	if (!gic_kvm_info->vctrl.start) {
	214	kvm_err("GICH not present in the firmware table\n");
	215	ret = -ENXIO;
8f186d52 MZ	216	goto out;
	217	}
	218
503a6286 JG	219	vgic->vctrl_base = ioremap(gic_kvm_info->vctrl.start,
503a6286 JG	220	resource_size(&gic_kvm_info->vctrl));
8f186d52 MZ	221	if (!vgic->vctrl_base) {
	222	kvm_err("Cannot ioremap GICH\n");
	223	ret = -ENOMEM;
	224	goto out;
	225	}
	226
	227	vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
	228	vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;
	229
	230	ret = create_hyp_io_mappings(vgic->vctrl_base,
503a6286 JG	231	vgic->vctrl_base + resource_size(vctrl_res),
503a6286 JG	232	vctrl_res->start);
8f186d52 MZ	233	if (ret) {
	234	kvm_err("Cannot map VCTRL into hyp\n");
	235	goto out_unmap;
	236	}
	237
503a6286	238	if (!PAGE_ALIGNED(vcpu_res->start)) {
5d576866	239	kvm_err("GICV physical address 0x%llx not page aligned\n",
503a6286	240	(unsigned long long)vcpu_res->start);
5d576866 PB	241	ret = -ENXIO;
	242	goto out_unmap;
	243	}
	244
503a6286	245	if (!PAGE_ALIGNED(resource_size(vcpu_res))) {
5d576866	246	kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
503a6286	247	(unsigned long long)resource_size(vcpu_res),
5d576866 PB	248	PAGE_SIZE);
	249	ret = -ENXIO;
	250	goto out_unmap;
	251	}
	252
b5d84ff6	253	vgic->can_emulate_gicv2 = true;
ea2f83a7 AP	254	kvm_register_device_ops(&kvm_arm_vgic_v2_ops, KVM_DEV_TYPE_ARM_VGIC_V2);
ea2f83a7 AP	255
503a6286	256	vgic->vcpu_base = vcpu_res->start;
8f186d52	257
503a6286 JG	258	kvm_info("GICH base=0x%llx, GICV base=0x%llx, IRQ=%d\n",
503a6286 JG	259	gic_kvm_info->vctrl.start, vgic->vcpu_base, vgic->maint_irq);
8f186d52	260
1a9b1305	261	vgic->type = VGIC_V2;
3caa2d8c	262	vgic->max_gic_vcpus = VGIC_V2_MAX_CPUS;
d6400d77 MZ	263
	264	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);
	265
8f186d52 MZ	266	*ops = &vgic_v2_ops;
	267	*params = vgic;
	268	goto out;
	269
	270	out_unmap:
	271	iounmap(vgic->vctrl_base);
	272	out:
8f186d52 MZ	273	return ret;
8f186d52 MZ	274	}