[deliverable/linux.git] / virt / kvm / arm / vgic-v3.c

/*
 * Copyright (C) 2013 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/cpu.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/irqchip/arm-gic-common.h>

#include <asm/kvm_emulate.h>
#include <asm/kvm_arm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_mmu.h>

static u32 ich_vtr_el2;

static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
{
	struct vgic_lr lr_desc;
	u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];

	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
		lr_desc.irq = val & ICH_LR_VIRTUAL_ID_MASK;
	else
		lr_desc.irq = val & GICH_LR_VIRTUALID;

	lr_desc.source = 0;
	if (lr_desc.irq <= 15 &&
	    vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
		lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;

	lr_desc.state = 0;

	if (val & ICH_LR_PENDING_BIT)
		lr_desc.state |= LR_STATE_PENDING;
	if (val & ICH_LR_ACTIVE_BIT)
		lr_desc.state |= LR_STATE_ACTIVE;
	if (val & ICH_LR_EOI)
		lr_desc.state |= LR_EOI_INT;
	if (val & ICH_LR_HW) {
		lr_desc.state |= LR_HW;
		lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
	}

	return lr_desc;
}

static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
			   struct vgic_lr lr_desc)
{
	u64 lr_val;

	lr_val = lr_desc.irq;

	/*
	 * Currently all guest IRQs are Group1, as Group0 would result
	 * in a FIQ in the guest, which it wouldn't expect.
	 * Eventually we want to make this configurable, so we may revisit
	 * this in the future.
	 */
	switch (vcpu->kvm->arch.vgic.vgic_model) {
	case KVM_DEV_TYPE_ARM_VGIC_V3:
		lr_val |= ICH_LR_GROUP;
		break;
	case  KVM_DEV_TYPE_ARM_VGIC_V2:
		if (lr_desc.irq < VGIC_NR_SGIS)
			lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
		break;
	default:
		BUG();
	}

	if (lr_desc.state & LR_STATE_PENDING)
		lr_val |= ICH_LR_PENDING_BIT;
	if (lr_desc.state & LR_STATE_ACTIVE)
		lr_val |= ICH_LR_ACTIVE_BIT;
	if (lr_desc.state & LR_EOI_INT)
		lr_val |= ICH_LR_EOI;
	if (lr_desc.state & LR_HW) {
		lr_val |= ICH_LR_HW;
		lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
	}

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;

	if (!(lr_desc.state & LR_STATE_MASK))
		vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
	else
		vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
}

static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
}

static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
{
	return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
}

static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
}

static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
{
	u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
	u32 ret = 0;

	if (misr & ICH_MISR_EOI)
		ret |= INT_STATUS_EOI;
	if (misr & ICH_MISR_U)
		ret |= INT_STATUS_UNDERFLOW;

	return ret;
}

static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;

	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
}

static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
}

static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
}

static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
}

static void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
		vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	else
		vgic_v3->vgic_sre = 0;

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
}

static const struct vgic_ops vgic_v3_ops = {
	.get_lr			= vgic_v3_get_lr,
	.set_lr			= vgic_v3_set_lr,
	.get_elrsr		= vgic_v3_get_elrsr,
	.get_eisr		= vgic_v3_get_eisr,
	.clear_eisr		= vgic_v3_clear_eisr,
	.get_interrupt_status	= vgic_v3_get_interrupt_status,
	.enable_underflow	= vgic_v3_enable_underflow,
	.disable_underflow	= vgic_v3_disable_underflow,
	.get_vmcr		= vgic_v3_get_vmcr,
	.set_vmcr		= vgic_v3_set_vmcr,
	.enable			= vgic_v3_enable,
};

static struct vgic_params vgic_v3_params;

static void vgic_cpu_init_lrs(void *params)
{
	kvm_call_hyp(__vgic_v3_init_lrs);
}

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller
 * @gic_kvm_info:	pointer to the GIC description
 * @ops:		address of a pointer to the GICv3 operations
 * @params:		address of a pointer to HW-specific parameters
 *
 * Returns 0 if a GICv3 has been found, with the low level operations
 * in *ops and the HW parameters in *params. Returns an error code
 * otherwise.
 */
int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params)
{
	int ret = 0;
	struct vgic_params *vgic = &vgic_v3_params;
	const struct resource *vcpu_res = &gic_kvm_info->vcpu;

	vgic->maint_irq = gic_kvm_info->maint_irq;

	ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
	vgic->can_emulate_gicv2 = false;

	if (!vcpu_res->start) {
		kvm_info("GICv3: no GICV resource entry\n");
		vgic->vcpu_base = 0;
	} else if (!PAGE_ALIGNED(vcpu_res->start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)vcpu_res->start);
		vgic->vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(vcpu_res))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(vcpu_res),
			PAGE_SIZE);
	} else {
		vgic->vcpu_base = vcpu_res->start;
		vgic->can_emulate_gicv2 = true;
		kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
					KVM_DEV_TYPE_ARM_VGIC_V2);
	}
	if (vgic->vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");
	kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);

	vgic->vctrl_base = NULL;
	vgic->type = VGIC_V3;
	vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;

	kvm_info("GICV base=0x%llx, IRQ=%d\n",
		 vgic->vcpu_base, vgic->maint_irq);

	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);

	*ops = &vgic_v3_ops;
	*params = vgic;

	return ret;
}
Commit	Line	Data
b2fb1c0d MZ	1	/*
	2	* Copyright (C) 2013 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/cpu.h>
	19	#include <linux/kvm.h>
	20	#include <linux/kvm_host.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
b2fb1c0d MZ	23
b2fb1c0d MZ	24	#include <linux/irqchip/arm-gic-v3.h>
503a6286	25	#include <linux/irqchip/arm-gic-common.h>
b2fb1c0d MZ	26
	27	#include <asm/kvm_emulate.h>
	28	#include <asm/kvm_arm.h>
9d8415d6	29	#include <asm/kvm_asm.h>
b2fb1c0d MZ	30	#include <asm/kvm_mmu.h>
b2fb1c0d MZ	31
b2fb1c0d MZ	32	static u32 ich_vtr_el2;
	33
	34	static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
	35	{
	36	struct vgic_lr lr_desc;
1b8e83c0	37	u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr];
b2fb1c0d	38
b5d84ff6	39	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
44bfc42e	40	lr_desc.irq = val & ICH_LR_VIRTUAL_ID_MASK;
b2fb1c0d	41	else
b5d84ff6 AP	42	lr_desc.irq = val & GICH_LR_VIRTUALID;
	43
	44	lr_desc.source = 0;
	45	if (lr_desc.irq <= 15 &&
	46	vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
	47	lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
	48
	49	lr_desc.state = 0;
b2fb1c0d MZ	50
	51	if (val & ICH_LR_PENDING_BIT)
	52	lr_desc.state \|= LR_STATE_PENDING;
	53	if (val & ICH_LR_ACTIVE_BIT)
	54	lr_desc.state \|= LR_STATE_ACTIVE;
	55	if (val & ICH_LR_EOI)
	56	lr_desc.state \|= LR_EOI_INT;
fb182cf8 MZ	57	if (val & ICH_LR_HW) {
	58	lr_desc.state \|= LR_HW;
	59	lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
	60	}
b2fb1c0d MZ	61
	62	return lr_desc;
	63	}
	64
	65	static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
	66	struct vgic_lr lr_desc)
	67	{
b5d84ff6 AP	68	u64 lr_val;
	69
	70	lr_val = lr_desc.irq;
	71
	72	/*
	73	* Currently all guest IRQs are Group1, as Group0 would result
	74	* in a FIQ in the guest, which it wouldn't expect.
	75	* Eventually we want to make this configurable, so we may revisit
	76	* this in the future.
	77	*/
fb182cf8 MZ	78	switch (vcpu->kvm->arch.vgic.vgic_model) {
fb182cf8 MZ	79	case KVM_DEV_TYPE_ARM_VGIC_V3:
b5d84ff6	80	lr_val \|= ICH_LR_GROUP;
fb182cf8 MZ	81	break;
	82	case KVM_DEV_TYPE_ARM_VGIC_V2:
	83	if (lr_desc.irq < VGIC_NR_SGIS)
	84	lr_val \|= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
	85	break;
	86	default:
	87	BUG();
	88	}
b2fb1c0d MZ	89
	90	if (lr_desc.state & LR_STATE_PENDING)
	91	lr_val \|= ICH_LR_PENDING_BIT;
	92	if (lr_desc.state & LR_STATE_ACTIVE)
	93	lr_val \|= ICH_LR_ACTIVE_BIT;
	94	if (lr_desc.state & LR_EOI_INT)
	95	lr_val \|= ICH_LR_EOI;
fb182cf8 MZ	96	if (lr_desc.state & LR_HW) {
	97	lr_val \|= ICH_LR_HW;
	98	lr_val \|= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
	99	}
b2fb1c0d	100
1b8e83c0	101	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = lr_val;
b2fb1c0d	102
b2fb1c0d MZ	103	if (!(lr_desc.state & LR_STATE_MASK))
b2fb1c0d MZ	104	vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr \|= (1U << lr);
ae705930 CD	105	else
ae705930 CD	106	vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
b2fb1c0d MZ	107	}
	108
	109	static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
	110	{
	111	return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
	112	}
	113
	114	static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
	115	{
	116	return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
	117	}
	118
ae705930 CD	119	static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
	120	{
	121	vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
	122	}
	123
b2fb1c0d MZ	124	static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
	125	{
	126	u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
	127	u32 ret = 0;
	128
	129	if (misr & ICH_MISR_EOI)
	130	ret \|= INT_STATUS_EOI;
	131	if (misr & ICH_MISR_U)
	132	ret \|= INT_STATUS_UNDERFLOW;
	133
	134	return ret;
	135	}
	136
	137	static void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	138	{
	139	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
	140
	141	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	142	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	143	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	144	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	145	}
	146
	147	static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
	148	{
	149	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr \|= ICH_HCR_UIE;
	150	}
	151
	152	static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
	153	{
	154	vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
	155	}
	156
	157	static void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	158	{
	159	u32 vmcr;
	160
	161	vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	162	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	163	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	164	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	165
	166	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
	167	}
	168
	169	static void vgic_v3_enable(struct kvm_vcpu *vcpu)
	170	{
2f5fa41a AP	171	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
2f5fa41a AP	172
b2fb1c0d MZ	173	/*
	174	* By forcing VMCR to zero, the GIC will restore the binary
	175	* points to their reset values. Anything else resets to zero
	176	* anyway.
	177	*/
2f5fa41a	178	vgic_v3->vgic_vmcr = 0;
c4cd4c16	179	vgic_v3->vgic_elrsr = ~0;
2f5fa41a	180
b5d84ff6 AP	181	/*
	182	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	183	* way, so we force SRE to 1 to demonstrate this to the guest.
	184	* This goes with the spec allowing the value to be RAO/WI.
	185	*/
	186	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
	187	vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
	188	else
	189	vgic_v3->vgic_sre = 0;
b2fb1c0d MZ	190
b2fb1c0d MZ	191	/* Get the show on the road... */
2f5fa41a	192	vgic_v3->vgic_hcr = ICH_HCR_EN;
b2fb1c0d MZ	193	}
	194
	195	static const struct vgic_ops vgic_v3_ops = {
	196	.get_lr = vgic_v3_get_lr,
	197	.set_lr = vgic_v3_set_lr,
b2fb1c0d MZ	198	.get_elrsr = vgic_v3_get_elrsr,
b2fb1c0d MZ	199	.get_eisr = vgic_v3_get_eisr,
ae705930	200	.clear_eisr = vgic_v3_clear_eisr,
b2fb1c0d MZ	201	.get_interrupt_status = vgic_v3_get_interrupt_status,
	202	.enable_underflow = vgic_v3_enable_underflow,
	203	.disable_underflow = vgic_v3_disable_underflow,
	204	.get_vmcr = vgic_v3_get_vmcr,
	205	.set_vmcr = vgic_v3_set_vmcr,
	206	.enable = vgic_v3_enable,
	207	};
	208
	209	static struct vgic_params vgic_v3_params;
	210
0d98d00b MZ	211	static void vgic_cpu_init_lrs(void *params)
	212	{
	213	kvm_call_hyp(__vgic_v3_init_lrs);
	214	}
	215
b2fb1c0d	216	/**
503a6286 JG	217	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller
	218	* @gic_kvm_info: pointer to the GIC description
	219	* @ops: address of a pointer to the GICv3 operations
	220	* @params: address of a pointer to HW-specific parameters
b2fb1c0d MZ	221	*
	222	* Returns 0 if a GICv3 has been found, with the low level operations
	223	* in ops and the HW parameters in params. Returns an error code
	224	* otherwise.
	225	*/
503a6286	226	int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
b2fb1c0d MZ	227	const struct vgic_ops **ops,
	228	const struct vgic_params **params)
	229	{
	230	int ret = 0;
b2fb1c0d	231	struct vgic_params *vgic = &vgic_v3_params;
503a6286	232	const struct resource *vcpu_res = &gic_kvm_info->vcpu;
b2fb1c0d	233
503a6286	234	vgic->maint_irq = gic_kvm_info->maint_irq;
b2fb1c0d MZ	235
	236	ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	237
	238	/*
	239	* The ListRegs field is 5 bits, but there is a architectural
	240	* maximum of 16 list registers. Just ignore bit 4...
	241	*/
	242	vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
b5d84ff6	243	vgic->can_emulate_gicv2 = false;
b2fb1c0d	244
503a6286	245	if (!vcpu_res->start) {
b5d84ff6 AP	246	kvm_info("GICv3: no GICV resource entry\n");
b5d84ff6 AP	247	vgic->vcpu_base = 0;
503a6286	248	} else if (!PAGE_ALIGNED(vcpu_res->start)) {
b5d84ff6	249	pr_warn("GICV physical address 0x%llx not page aligned\n",
503a6286	250	(unsigned long long)vcpu_res->start);
b5d84ff6	251	vgic->vcpu_base = 0;
503a6286	252	} else if (!PAGE_ALIGNED(resource_size(vcpu_res))) {
b5d84ff6	253	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
503a6286	254	(unsigned long long)resource_size(vcpu_res),
fb3ec679	255	PAGE_SIZE);
b5d84ff6	256	} else {
503a6286	257	vgic->vcpu_base = vcpu_res->start;
b5d84ff6 AP	258	vgic->can_emulate_gicv2 = true;
	259	kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
	260	KVM_DEV_TYPE_ARM_VGIC_V2);
fb3ec679	261	}
b5d84ff6 AP	262	if (vgic->vcpu_base == 0)
	263	kvm_info("disabling GICv2 emulation\n");
	264	kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
fb3ec679	265
b2fb1c0d MZ	266	vgic->vctrl_base = NULL;
b2fb1c0d MZ	267	vgic->type = VGIC_V3;
ef748917	268	vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
b2fb1c0d	269
503a6286 JG	270	kvm_info("GICV base=0x%llx, IRQ=%d\n",
503a6286 JG	271	vgic->vcpu_base, vgic->maint_irq);
b2fb1c0d	272
0d98d00b MZ	273	on_each_cpu(vgic_cpu_init_lrs, vgic, 1);
0d98d00b MZ	274
b2fb1c0d MZ	275	*ops = &vgic_v3_ops;
	276	*params = vgic;
	277
b2fb1c0d MZ	278	return ret;
b2fb1c0d MZ	279	}