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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
7e362919 CD |
39 | * something is pending on the CPU interface. |
40 | * - Interrupts that are pending on the distributor are stored on the | |
41 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land | |
42 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers). | |
b47ef92a MZ |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
48 | * - PPI: dist->irq_pending & dist->irq_enable |
49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
7e362919 | 50 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
b47ef92a MZ |
51 | * registers, stored on each vcpu. We only keep one bit of |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
7e362919 | 54 | * - If any of the above state changes, we must recalculate the oracle. |
b47ef92a MZ |
55 | * - The same is true when injecting an interrupt, except that we only |
56 | * consider a single interrupt at a time. The irq_spi_cpu array | |
57 | * contains the target CPU for each SPI. | |
58 | * | |
59 | * The handling of level interrupts adds some extra complexity. We | |
60 | * need to track when the interrupt has been EOIed, so we can sample | |
61 | * the 'line' again. This is achieved as such: | |
62 | * | |
63 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 64 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
65 | * will be ignored for further interrupts. The interrupt is injected |
66 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
67 | * maintenance interrupt on EOI). | |
68 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 69 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 70 | * interrupt line to be sampled again. |
faa1b46c CD |
71 | * - Note that level-triggered interrupts can also be set to pending from |
72 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
73 | * cause the interrupt to become inactive in such a situation. | |
74 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
75 | * inactive as long as the external input line is held high. | |
b47ef92a MZ |
76 | */ |
77 | ||
330690cd CD |
78 | #define VGIC_ADDR_UNDEF (-1) |
79 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) | |
80 | ||
fa20f5ae CD |
81 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
82 | #define IMPLEMENTER_ARM 0x43b | |
83 | #define GICC_ARCH_VERSION_V2 0x2 | |
84 | ||
1a89dd91 MZ |
85 | #define ACCESS_READ_VALUE (1 << 0) |
86 | #define ACCESS_READ_RAZ (0 << 0) | |
87 | #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) | |
88 | #define ACCESS_WRITE_IGNORED (0 << 1) | |
89 | #define ACCESS_WRITE_SETBIT (1 << 1) | |
90 | #define ACCESS_WRITE_CLEARBIT (2 << 1) | |
91 | #define ACCESS_WRITE_VALUE (3 << 1) | |
92 | #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) | |
93 | ||
6d3cfbe2 | 94 | static int vgic_init(struct kvm *kvm); |
a1fcb44e | 95 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 96 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
b47ef92a | 97 | static void vgic_update_state(struct kvm *kvm); |
5863c2ce | 98 | static void vgic_kick_vcpus(struct kvm *kvm); |
c1bfb577 | 99 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi); |
b47ef92a | 100 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
8d5c6b06 MZ |
101 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
102 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
beee38b9 MZ |
103 | static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
104 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
01ac5e34 | 105 | |
8f186d52 MZ |
106 | static const struct vgic_ops *vgic_ops; |
107 | static const struct vgic_params *vgic; | |
b47ef92a | 108 | |
9662fb48 | 109 | /* |
c1bfb577 MZ |
110 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
111 | * extracts u32s out of them. | |
9662fb48 VK |
112 | * |
113 | * This does not work on 64-bit BE systems, because the bitmap access | |
114 | * will store two consecutive 32-bit words with the higher-addressed | |
115 | * register's bits at the lower index and the lower-addressed register's | |
116 | * bits at the higher index. | |
117 | * | |
118 | * Therefore, swizzle the register index when accessing the 32-bit word | |
119 | * registers to access the right register's value. | |
120 | */ | |
121 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
122 | #define REG_OFFSET_SWIZZLE 1 | |
123 | #else | |
124 | #define REG_OFFSET_SWIZZLE 0 | |
125 | #endif | |
b47ef92a | 126 | |
c1bfb577 MZ |
127 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
128 | { | |
129 | int nr_longs; | |
130 | ||
131 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); | |
132 | ||
133 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); | |
134 | if (!b->private) | |
135 | return -ENOMEM; | |
136 | ||
137 | b->shared = b->private + nr_cpus; | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static void vgic_free_bitmap(struct vgic_bitmap *b) | |
143 | { | |
144 | kfree(b->private); | |
145 | b->private = NULL; | |
146 | b->shared = NULL; | |
147 | } | |
148 | ||
2df36a5d CD |
149 | /* |
150 | * Call this function to convert a u64 value to an unsigned long * bitmask | |
151 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. | |
152 | * | |
153 | * Warning: Calling this function may modify *val. | |
154 | */ | |
155 | static unsigned long *u64_to_bitmask(u64 *val) | |
156 | { | |
157 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 | |
158 | *val = (*val >> 32) | (*val << 32); | |
159 | #endif | |
160 | return (unsigned long *)val; | |
161 | } | |
162 | ||
b47ef92a MZ |
163 | static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, |
164 | int cpuid, u32 offset) | |
165 | { | |
166 | offset >>= 2; | |
167 | if (!offset) | |
c1bfb577 | 168 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
b47ef92a | 169 | else |
c1bfb577 | 170 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
171 | } |
172 | ||
173 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
174 | int cpuid, int irq) | |
175 | { | |
176 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
c1bfb577 | 177 | return test_bit(irq, x->private + cpuid); |
b47ef92a | 178 | |
c1bfb577 | 179 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
b47ef92a MZ |
180 | } |
181 | ||
182 | static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, | |
183 | int irq, int val) | |
184 | { | |
185 | unsigned long *reg; | |
186 | ||
187 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
c1bfb577 | 188 | reg = x->private + cpuid; |
b47ef92a | 189 | } else { |
c1bfb577 | 190 | reg = x->shared; |
b47ef92a MZ |
191 | irq -= VGIC_NR_PRIVATE_IRQS; |
192 | } | |
193 | ||
194 | if (val) | |
195 | set_bit(irq, reg); | |
196 | else | |
197 | clear_bit(irq, reg); | |
198 | } | |
199 | ||
200 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
201 | { | |
c1bfb577 | 202 | return x->private + cpuid; |
b47ef92a MZ |
203 | } |
204 | ||
205 | static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) | |
206 | { | |
c1bfb577 MZ |
207 | return x->shared; |
208 | } | |
209 | ||
210 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) | |
211 | { | |
212 | int size; | |
213 | ||
214 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; | |
215 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
216 | ||
217 | x->private = kzalloc(size, GFP_KERNEL); | |
218 | if (!x->private) | |
219 | return -ENOMEM; | |
220 | ||
221 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static void vgic_free_bytemap(struct vgic_bytemap *b) | |
226 | { | |
227 | kfree(b->private); | |
228 | b->private = NULL; | |
229 | b->shared = NULL; | |
b47ef92a MZ |
230 | } |
231 | ||
232 | static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) | |
233 | { | |
c1bfb577 MZ |
234 | u32 *reg; |
235 | ||
236 | if (offset < VGIC_NR_PRIVATE_IRQS) { | |
237 | reg = x->private; | |
238 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; | |
239 | } else { | |
240 | reg = x->shared; | |
241 | offset -= VGIC_NR_PRIVATE_IRQS; | |
242 | } | |
243 | ||
244 | return reg + (offset / sizeof(u32)); | |
b47ef92a MZ |
245 | } |
246 | ||
247 | #define VGIC_CFG_LEVEL 0 | |
248 | #define VGIC_CFG_EDGE 1 | |
249 | ||
250 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
251 | { | |
252 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
253 | int irq_val; | |
254 | ||
255 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
256 | return irq_val == VGIC_CFG_EDGE; | |
257 | } | |
258 | ||
259 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
260 | { | |
261 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
262 | ||
263 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
264 | } | |
265 | ||
dbf20f9d | 266 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
267 | { |
268 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
269 | ||
dbf20f9d | 270 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
271 | } |
272 | ||
dbf20f9d | 273 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
274 | { |
275 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
276 | ||
dbf20f9d | 277 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
278 | } |
279 | ||
dbf20f9d | 280 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
281 | { |
282 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
283 | ||
dbf20f9d | 284 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
285 | } |
286 | ||
faa1b46c CD |
287 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
288 | { | |
289 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
290 | ||
291 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
292 | } | |
293 | ||
294 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
295 | { | |
296 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
297 | ||
298 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
299 | } | |
300 | ||
301 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
302 | { | |
303 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
304 | ||
305 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
306 | } | |
307 | ||
308 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
309 | { | |
310 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
311 | ||
312 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
313 | } | |
314 | ||
315 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
316 | { | |
317 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
318 | ||
319 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
320 | } | |
321 | ||
9d949dce MZ |
322 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
323 | { | |
324 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
325 | ||
227844f5 | 326 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
327 | } |
328 | ||
227844f5 | 329 | static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
330 | { |
331 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
332 | ||
227844f5 | 333 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
334 | } |
335 | ||
227844f5 | 336 | static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
337 | { |
338 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
339 | ||
227844f5 | 340 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
341 | } |
342 | ||
343 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
344 | { | |
345 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
346 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
347 | else | |
348 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
349 | vcpu->arch.vgic_cpu.pending_shared); | |
350 | } | |
351 | ||
352 | static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
353 | { | |
354 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
355 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
356 | else | |
357 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
358 | vcpu->arch.vgic_cpu.pending_shared); | |
359 | } | |
360 | ||
dbf20f9d CD |
361 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
362 | { | |
363 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
364 | } | |
365 | ||
1a89dd91 MZ |
366 | static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) |
367 | { | |
1c9f0471 | 368 | return le32_to_cpu(*((u32 *)mmio->data)) & mask; |
1a89dd91 MZ |
369 | } |
370 | ||
371 | static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) | |
372 | { | |
1c9f0471 | 373 | *((u32 *)mmio->data) = cpu_to_le32(value) & mask; |
1a89dd91 MZ |
374 | } |
375 | ||
376 | /** | |
377 | * vgic_reg_access - access vgic register | |
378 | * @mmio: pointer to the data describing the mmio access | |
379 | * @reg: pointer to the virtual backing of vgic distributor data | |
380 | * @offset: least significant 2 bits used for word offset | |
381 | * @mode: ACCESS_ mode (see defines above) | |
382 | * | |
383 | * Helper to make vgic register access easier using one of the access | |
384 | * modes defined for vgic register access | |
385 | * (read,raz,write-ignored,setbit,clearbit,write) | |
386 | */ | |
387 | static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, | |
388 | phys_addr_t offset, int mode) | |
389 | { | |
390 | int word_offset = (offset & 3) * 8; | |
391 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
392 | u32 regval; | |
393 | ||
394 | /* | |
395 | * Any alignment fault should have been delivered to the guest | |
396 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
397 | */ | |
398 | ||
399 | if (reg) { | |
400 | regval = *reg; | |
401 | } else { | |
402 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
403 | regval = 0; | |
404 | } | |
405 | ||
406 | if (mmio->is_write) { | |
407 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
408 | switch (ACCESS_WRITE_MASK(mode)) { | |
409 | case ACCESS_WRITE_IGNORED: | |
410 | return; | |
411 | ||
412 | case ACCESS_WRITE_SETBIT: | |
413 | regval |= data; | |
414 | break; | |
415 | ||
416 | case ACCESS_WRITE_CLEARBIT: | |
417 | regval &= ~data; | |
418 | break; | |
419 | ||
420 | case ACCESS_WRITE_VALUE: | |
421 | regval = (regval & ~(mask << word_offset)) | data; | |
422 | break; | |
423 | } | |
424 | *reg = regval; | |
425 | } else { | |
426 | switch (ACCESS_READ_MASK(mode)) { | |
427 | case ACCESS_READ_RAZ: | |
428 | regval = 0; | |
429 | /* fall through */ | |
430 | ||
431 | case ACCESS_READ_VALUE: | |
432 | mmio_data_write(mmio, mask, regval >> word_offset); | |
433 | } | |
434 | } | |
435 | } | |
436 | ||
b47ef92a MZ |
437 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
438 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
439 | { | |
440 | u32 reg; | |
441 | u32 word_offset = offset & 3; | |
442 | ||
443 | switch (offset & ~3) { | |
fa20f5ae | 444 | case 0: /* GICD_CTLR */ |
b47ef92a MZ |
445 | reg = vcpu->kvm->arch.vgic.enabled; |
446 | vgic_reg_access(mmio, ®, word_offset, | |
447 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
448 | if (mmio->is_write) { | |
449 | vcpu->kvm->arch.vgic.enabled = reg & 1; | |
450 | vgic_update_state(vcpu->kvm); | |
451 | return true; | |
452 | } | |
453 | break; | |
454 | ||
fa20f5ae | 455 | case 4: /* GICD_TYPER */ |
b47ef92a | 456 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
5fb66da6 | 457 | reg |= (vcpu->kvm->arch.vgic.nr_irqs >> 5) - 1; |
b47ef92a MZ |
458 | vgic_reg_access(mmio, ®, word_offset, |
459 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
460 | break; | |
461 | ||
fa20f5ae CD |
462 | case 8: /* GICD_IIDR */ |
463 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
b47ef92a MZ |
464 | vgic_reg_access(mmio, ®, word_offset, |
465 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
466 | break; | |
467 | } | |
468 | ||
469 | return false; | |
470 | } | |
471 | ||
472 | static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, | |
473 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
474 | { | |
475 | vgic_reg_access(mmio, NULL, offset, | |
476 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
477 | return false; | |
478 | } | |
479 | ||
480 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, | |
481 | struct kvm_exit_mmio *mmio, | |
482 | phys_addr_t offset) | |
483 | { | |
484 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
485 | vcpu->vcpu_id, offset); | |
486 | vgic_reg_access(mmio, reg, offset, | |
487 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
488 | if (mmio->is_write) { | |
489 | vgic_update_state(vcpu->kvm); | |
490 | return true; | |
491 | } | |
492 | ||
493 | return false; | |
494 | } | |
495 | ||
496 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, | |
497 | struct kvm_exit_mmio *mmio, | |
498 | phys_addr_t offset) | |
499 | { | |
500 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
501 | vcpu->vcpu_id, offset); | |
502 | vgic_reg_access(mmio, reg, offset, | |
503 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
504 | if (mmio->is_write) { | |
505 | if (offset < 4) /* Force SGI enabled */ | |
506 | *reg |= 0xffff; | |
a1fcb44e | 507 | vgic_retire_disabled_irqs(vcpu); |
b47ef92a MZ |
508 | vgic_update_state(vcpu->kvm); |
509 | return true; | |
510 | } | |
511 | ||
512 | return false; | |
513 | } | |
514 | ||
515 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, | |
516 | struct kvm_exit_mmio *mmio, | |
517 | phys_addr_t offset) | |
518 | { | |
9da48b55 | 519 | u32 *reg, orig; |
faa1b46c CD |
520 | u32 level_mask; |
521 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
522 | ||
523 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset); | |
524 | level_mask = (~(*reg)); | |
525 | ||
526 | /* Mark both level and edge triggered irqs as pending */ | |
527 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 528 | orig = *reg; |
b47ef92a MZ |
529 | vgic_reg_access(mmio, reg, offset, |
530 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
faa1b46c | 531 | |
b47ef92a | 532 | if (mmio->is_write) { |
faa1b46c CD |
533 | /* Set the soft-pending flag only for level-triggered irqs */ |
534 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
535 | vcpu->vcpu_id, offset); | |
536 | vgic_reg_access(mmio, reg, offset, | |
537 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
538 | *reg &= level_mask; | |
539 | ||
9da48b55 CD |
540 | /* Ignore writes to SGIs */ |
541 | if (offset < 2) { | |
542 | *reg &= ~0xffff; | |
543 | *reg |= orig & 0xffff; | |
544 | } | |
545 | ||
b47ef92a MZ |
546 | vgic_update_state(vcpu->kvm); |
547 | return true; | |
548 | } | |
549 | ||
550 | return false; | |
551 | } | |
552 | ||
553 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, | |
554 | struct kvm_exit_mmio *mmio, | |
555 | phys_addr_t offset) | |
556 | { | |
faa1b46c | 557 | u32 *level_active; |
9da48b55 | 558 | u32 *reg, orig; |
faa1b46c CD |
559 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
560 | ||
561 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 562 | orig = *reg; |
b47ef92a MZ |
563 | vgic_reg_access(mmio, reg, offset, |
564 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
565 | if (mmio->is_write) { | |
faa1b46c CD |
566 | /* Re-set level triggered level-active interrupts */ |
567 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
568 | vcpu->vcpu_id, offset); | |
569 | reg = vgic_bitmap_get_reg(&dist->irq_pending, | |
570 | vcpu->vcpu_id, offset); | |
571 | *reg |= *level_active; | |
572 | ||
9da48b55 CD |
573 | /* Ignore writes to SGIs */ |
574 | if (offset < 2) { | |
575 | *reg &= ~0xffff; | |
576 | *reg |= orig & 0xffff; | |
577 | } | |
578 | ||
faa1b46c CD |
579 | /* Clear soft-pending flags */ |
580 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
581 | vcpu->vcpu_id, offset); | |
582 | vgic_reg_access(mmio, reg, offset, | |
583 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
584 | ||
b47ef92a MZ |
585 | vgic_update_state(vcpu->kvm); |
586 | return true; | |
587 | } | |
588 | ||
589 | return false; | |
590 | } | |
591 | ||
592 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, | |
593 | struct kvm_exit_mmio *mmio, | |
594 | phys_addr_t offset) | |
595 | { | |
596 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, | |
597 | vcpu->vcpu_id, offset); | |
598 | vgic_reg_access(mmio, reg, offset, | |
599 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
600 | return false; | |
601 | } | |
602 | ||
603 | #define GICD_ITARGETSR_SIZE 32 | |
604 | #define GICD_CPUTARGETS_BITS 8 | |
605 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) | |
606 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) | |
607 | { | |
608 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986af8e0 | 609 | int i; |
b47ef92a MZ |
610 | u32 val = 0; |
611 | ||
612 | irq -= VGIC_NR_PRIVATE_IRQS; | |
613 | ||
986af8e0 MZ |
614 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
615 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); | |
b47ef92a MZ |
616 | |
617 | return val; | |
618 | } | |
619 | ||
620 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) | |
621 | { | |
622 | struct vgic_dist *dist = &kvm->arch.vgic; | |
623 | struct kvm_vcpu *vcpu; | |
624 | int i, c; | |
625 | unsigned long *bmap; | |
626 | u32 target; | |
627 | ||
628 | irq -= VGIC_NR_PRIVATE_IRQS; | |
629 | ||
630 | /* | |
631 | * Pick the LSB in each byte. This ensures we target exactly | |
632 | * one vcpu per IRQ. If the byte is null, assume we target | |
633 | * CPU0. | |
634 | */ | |
635 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { | |
636 | int shift = i * GICD_CPUTARGETS_BITS; | |
637 | target = ffs((val >> shift) & 0xffU); | |
638 | target = target ? (target - 1) : 0; | |
639 | dist->irq_spi_cpu[irq + i] = target; | |
640 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
641 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); | |
642 | if (c == target) | |
643 | set_bit(irq + i, bmap); | |
644 | else | |
645 | clear_bit(irq + i, bmap); | |
646 | } | |
647 | } | |
648 | } | |
649 | ||
650 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, | |
651 | struct kvm_exit_mmio *mmio, | |
652 | phys_addr_t offset) | |
653 | { | |
654 | u32 reg; | |
655 | ||
656 | /* We treat the banked interrupts targets as read-only */ | |
657 | if (offset < 32) { | |
658 | u32 roreg = 1 << vcpu->vcpu_id; | |
659 | roreg |= roreg << 8; | |
660 | roreg |= roreg << 16; | |
661 | ||
662 | vgic_reg_access(mmio, &roreg, offset, | |
663 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
664 | return false; | |
665 | } | |
666 | ||
667 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); | |
668 | vgic_reg_access(mmio, ®, offset, | |
669 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
670 | if (mmio->is_write) { | |
671 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); | |
672 | vgic_update_state(vcpu->kvm); | |
673 | return true; | |
674 | } | |
675 | ||
676 | return false; | |
677 | } | |
678 | ||
679 | static u32 vgic_cfg_expand(u16 val) | |
680 | { | |
681 | u32 res = 0; | |
682 | int i; | |
683 | ||
684 | /* | |
685 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
686 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
687 | */ | |
688 | for (i = 0; i < 16; i++) | |
689 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
690 | ||
691 | return res; | |
692 | } | |
693 | ||
694 | static u16 vgic_cfg_compress(u32 val) | |
695 | { | |
696 | u16 res = 0; | |
697 | int i; | |
698 | ||
699 | /* | |
700 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
701 | * abcd...mnop which is what we really care about. | |
702 | */ | |
703 | for (i = 0; i < 16; i++) | |
704 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
705 | ||
706 | return res; | |
707 | } | |
708 | ||
709 | /* | |
710 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
711 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
712 | * two above functions to compress/expand the bits | |
713 | */ | |
714 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, | |
715 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
716 | { | |
717 | u32 val; | |
6545eae3 MZ |
718 | u32 *reg; |
719 | ||
6545eae3 | 720 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
f2ae85b2 | 721 | vcpu->vcpu_id, offset >> 1); |
6545eae3 | 722 | |
f2ae85b2 | 723 | if (offset & 4) |
b47ef92a MZ |
724 | val = *reg >> 16; |
725 | else | |
726 | val = *reg & 0xffff; | |
727 | ||
728 | val = vgic_cfg_expand(val); | |
729 | vgic_reg_access(mmio, &val, offset, | |
730 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
731 | if (mmio->is_write) { | |
f2ae85b2 | 732 | if (offset < 8) { |
b47ef92a MZ |
733 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
734 | return false; | |
735 | } | |
736 | ||
737 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 738 | if (offset & 4) { |
b47ef92a MZ |
739 | *reg &= 0xffff; |
740 | *reg |= val << 16; | |
741 | } else { | |
742 | *reg &= 0xffff << 16; | |
743 | *reg |= val; | |
744 | } | |
745 | } | |
746 | ||
747 | return false; | |
748 | } | |
749 | ||
750 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, | |
751 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
752 | { | |
753 | u32 reg; | |
754 | vgic_reg_access(mmio, ®, offset, | |
755 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); | |
756 | if (mmio->is_write) { | |
757 | vgic_dispatch_sgi(vcpu, reg); | |
758 | vgic_update_state(vcpu->kvm); | |
759 | return true; | |
760 | } | |
761 | ||
762 | return false; | |
763 | } | |
764 | ||
cbd333a4 CD |
765 | /** |
766 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
767 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
768 | * | |
769 | * Move any pending IRQs that have already been assigned to LRs back to the | |
770 | * emulated distributor state so that the complete emulated state can be read | |
771 | * from the main emulation structures without investigating the LRs. | |
772 | * | |
773 | * Note that IRQs in the active state in the LRs get their pending state moved | |
774 | * to the distributor but the active state stays in the LRs, because we don't | |
775 | * track the active state on the distributor side. | |
776 | */ | |
777 | static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) | |
778 | { | |
779 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
780 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
781 | int vcpu_id = vcpu->vcpu_id; | |
8d5c6b06 | 782 | int i; |
cbd333a4 CD |
783 | |
784 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 785 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
786 | |
787 | /* | |
788 | * There are three options for the state bits: | |
789 | * | |
790 | * 01: pending | |
791 | * 10: active | |
792 | * 11: pending and active | |
793 | * | |
794 | * If the LR holds only an active interrupt (not pending) then | |
795 | * just leave it alone. | |
796 | */ | |
8d5c6b06 | 797 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
798 | continue; |
799 | ||
800 | /* | |
801 | * Reestablish the pending state on the distributor and the | |
802 | * CPU interface. It may have already been pending, but that | |
803 | * is fine, then we are only setting a few bits that were | |
804 | * already set. | |
805 | */ | |
227844f5 | 806 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
8d5c6b06 | 807 | if (lr.irq < VGIC_NR_SGIS) |
c1bfb577 | 808 | *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source; |
8d5c6b06 MZ |
809 | lr.state &= ~LR_STATE_PENDING; |
810 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
811 | |
812 | /* | |
813 | * If there's no state left on the LR (it could still be | |
814 | * active), then the LR does not hold any useful info and can | |
815 | * be marked as free for other use. | |
816 | */ | |
cced50c9 | 817 | if (!(lr.state & LR_STATE_MASK)) { |
8d5c6b06 | 818 | vgic_retire_lr(i, lr.irq, vcpu); |
cced50c9 CD |
819 | vgic_irq_clear_queued(vcpu, lr.irq); |
820 | } | |
cbd333a4 CD |
821 | |
822 | /* Finally update the VGIC state. */ | |
823 | vgic_update_state(vcpu->kvm); | |
824 | } | |
825 | } | |
826 | ||
90a5355e CD |
827 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
828 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, | |
829 | struct kvm_exit_mmio *mmio, | |
830 | phys_addr_t offset) | |
c07a0191 | 831 | { |
90a5355e CD |
832 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
833 | int sgi; | |
0fea6d76 | 834 | int min_sgi = (offset & ~0x3); |
90a5355e CD |
835 | int max_sgi = min_sgi + 3; |
836 | int vcpu_id = vcpu->vcpu_id; | |
837 | u32 reg = 0; | |
838 | ||
839 | /* Copy source SGIs from distributor side */ | |
840 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
841 | int shift = 8 * (sgi - min_sgi); | |
c1bfb577 | 842 | reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift; |
90a5355e CD |
843 | } |
844 | ||
845 | mmio_data_write(mmio, ~0, reg); | |
c07a0191 CD |
846 | return false; |
847 | } | |
848 | ||
90a5355e CD |
849 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
850 | struct kvm_exit_mmio *mmio, | |
851 | phys_addr_t offset, bool set) | |
852 | { | |
853 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
854 | int sgi; | |
0fea6d76 | 855 | int min_sgi = (offset & ~0x3); |
90a5355e CD |
856 | int max_sgi = min_sgi + 3; |
857 | int vcpu_id = vcpu->vcpu_id; | |
858 | u32 reg; | |
859 | bool updated = false; | |
860 | ||
861 | reg = mmio_data_read(mmio, ~0); | |
862 | ||
863 | /* Clear pending SGIs on the distributor */ | |
864 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
865 | u8 mask = reg >> (8 * (sgi - min_sgi)); | |
c1bfb577 | 866 | u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi); |
90a5355e | 867 | if (set) { |
c1bfb577 | 868 | if ((*src & mask) != mask) |
90a5355e | 869 | updated = true; |
c1bfb577 | 870 | *src |= mask; |
90a5355e | 871 | } else { |
c1bfb577 | 872 | if (*src & mask) |
90a5355e | 873 | updated = true; |
c1bfb577 | 874 | *src &= ~mask; |
90a5355e CD |
875 | } |
876 | } | |
877 | ||
878 | if (updated) | |
879 | vgic_update_state(vcpu->kvm); | |
880 | ||
881 | return updated; | |
882 | } | |
883 | ||
c07a0191 CD |
884 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
885 | struct kvm_exit_mmio *mmio, | |
886 | phys_addr_t offset) | |
887 | { | |
90a5355e CD |
888 | if (!mmio->is_write) |
889 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
890 | else | |
891 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); | |
892 | } | |
893 | ||
894 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, | |
895 | struct kvm_exit_mmio *mmio, | |
896 | phys_addr_t offset) | |
897 | { | |
898 | if (!mmio->is_write) | |
899 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
900 | else | |
901 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); | |
c07a0191 CD |
902 | } |
903 | ||
1a89dd91 MZ |
904 | /* |
905 | * I would have liked to use the kvm_bus_io_*() API instead, but it | |
906 | * cannot cope with banked registers (only the VM pointer is passed | |
907 | * around, and we need the vcpu). One of these days, someone please | |
908 | * fix it! | |
909 | */ | |
910 | struct mmio_range { | |
911 | phys_addr_t base; | |
912 | unsigned long len; | |
c3c91836 | 913 | int bits_per_irq; |
1a89dd91 MZ |
914 | bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
915 | phys_addr_t offset); | |
916 | }; | |
917 | ||
1006e8cb | 918 | static const struct mmio_range vgic_dist_ranges[] = { |
b47ef92a MZ |
919 | { |
920 | .base = GIC_DIST_CTRL, | |
921 | .len = 12, | |
c3c91836 | 922 | .bits_per_irq = 0, |
b47ef92a MZ |
923 | .handle_mmio = handle_mmio_misc, |
924 | }, | |
925 | { | |
926 | .base = GIC_DIST_IGROUP, | |
c3c91836 MZ |
927 | .len = VGIC_MAX_IRQS / 8, |
928 | .bits_per_irq = 1, | |
b47ef92a MZ |
929 | .handle_mmio = handle_mmio_raz_wi, |
930 | }, | |
931 | { | |
932 | .base = GIC_DIST_ENABLE_SET, | |
c3c91836 MZ |
933 | .len = VGIC_MAX_IRQS / 8, |
934 | .bits_per_irq = 1, | |
b47ef92a MZ |
935 | .handle_mmio = handle_mmio_set_enable_reg, |
936 | }, | |
937 | { | |
938 | .base = GIC_DIST_ENABLE_CLEAR, | |
c3c91836 MZ |
939 | .len = VGIC_MAX_IRQS / 8, |
940 | .bits_per_irq = 1, | |
b47ef92a MZ |
941 | .handle_mmio = handle_mmio_clear_enable_reg, |
942 | }, | |
943 | { | |
944 | .base = GIC_DIST_PENDING_SET, | |
c3c91836 MZ |
945 | .len = VGIC_MAX_IRQS / 8, |
946 | .bits_per_irq = 1, | |
b47ef92a MZ |
947 | .handle_mmio = handle_mmio_set_pending_reg, |
948 | }, | |
949 | { | |
950 | .base = GIC_DIST_PENDING_CLEAR, | |
c3c91836 MZ |
951 | .len = VGIC_MAX_IRQS / 8, |
952 | .bits_per_irq = 1, | |
b47ef92a MZ |
953 | .handle_mmio = handle_mmio_clear_pending_reg, |
954 | }, | |
955 | { | |
956 | .base = GIC_DIST_ACTIVE_SET, | |
c3c91836 MZ |
957 | .len = VGIC_MAX_IRQS / 8, |
958 | .bits_per_irq = 1, | |
b47ef92a MZ |
959 | .handle_mmio = handle_mmio_raz_wi, |
960 | }, | |
961 | { | |
962 | .base = GIC_DIST_ACTIVE_CLEAR, | |
c3c91836 MZ |
963 | .len = VGIC_MAX_IRQS / 8, |
964 | .bits_per_irq = 1, | |
b47ef92a MZ |
965 | .handle_mmio = handle_mmio_raz_wi, |
966 | }, | |
967 | { | |
968 | .base = GIC_DIST_PRI, | |
c3c91836 MZ |
969 | .len = VGIC_MAX_IRQS, |
970 | .bits_per_irq = 8, | |
b47ef92a MZ |
971 | .handle_mmio = handle_mmio_priority_reg, |
972 | }, | |
973 | { | |
974 | .base = GIC_DIST_TARGET, | |
c3c91836 MZ |
975 | .len = VGIC_MAX_IRQS, |
976 | .bits_per_irq = 8, | |
b47ef92a MZ |
977 | .handle_mmio = handle_mmio_target_reg, |
978 | }, | |
979 | { | |
980 | .base = GIC_DIST_CONFIG, | |
c3c91836 MZ |
981 | .len = VGIC_MAX_IRQS / 4, |
982 | .bits_per_irq = 2, | |
b47ef92a MZ |
983 | .handle_mmio = handle_mmio_cfg_reg, |
984 | }, | |
985 | { | |
986 | .base = GIC_DIST_SOFTINT, | |
987 | .len = 4, | |
988 | .handle_mmio = handle_mmio_sgi_reg, | |
989 | }, | |
c07a0191 CD |
990 | { |
991 | .base = GIC_DIST_SGI_PENDING_CLEAR, | |
992 | .len = VGIC_NR_SGIS, | |
993 | .handle_mmio = handle_mmio_sgi_clear, | |
994 | }, | |
995 | { | |
996 | .base = GIC_DIST_SGI_PENDING_SET, | |
997 | .len = VGIC_NR_SGIS, | |
998 | .handle_mmio = handle_mmio_sgi_set, | |
999 | }, | |
1a89dd91 MZ |
1000 | {} |
1001 | }; | |
1002 | ||
1003 | static const | |
1004 | struct mmio_range *find_matching_range(const struct mmio_range *ranges, | |
1005 | struct kvm_exit_mmio *mmio, | |
1006e8cb | 1006 | phys_addr_t offset) |
1a89dd91 MZ |
1007 | { |
1008 | const struct mmio_range *r = ranges; | |
1a89dd91 MZ |
1009 | |
1010 | while (r->len) { | |
1006e8cb CD |
1011 | if (offset >= r->base && |
1012 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
1013 | return r; |
1014 | r++; | |
1015 | } | |
1016 | ||
1017 | return NULL; | |
1018 | } | |
1019 | ||
c3c91836 MZ |
1020 | static bool vgic_validate_access(const struct vgic_dist *dist, |
1021 | const struct mmio_range *range, | |
1022 | unsigned long offset) | |
1023 | { | |
1024 | int irq; | |
1025 | ||
1026 | if (!range->bits_per_irq) | |
1027 | return true; /* Not an irq-based access */ | |
1028 | ||
1029 | irq = offset * 8 / range->bits_per_irq; | |
1030 | if (irq >= dist->nr_irqs) | |
1031 | return false; | |
1032 | ||
1033 | return true; | |
1034 | } | |
1035 | ||
05bc8aaf AP |
1036 | /* |
1037 | * Call the respective handler function for the given range. | |
1038 | * We split up any 64 bit accesses into two consecutive 32 bit | |
1039 | * handler calls and merge the result afterwards. | |
1040 | * We do this in a little endian fashion regardless of the host's | |
1041 | * or guest's endianness, because the GIC is always LE and the rest of | |
1042 | * the code (vgic_reg_access) also puts it in a LE fashion already. | |
1043 | * At this point we have already identified the handle function, so | |
1044 | * range points to that one entry and offset is relative to this. | |
1045 | */ | |
1046 | static bool call_range_handler(struct kvm_vcpu *vcpu, | |
1047 | struct kvm_exit_mmio *mmio, | |
1048 | unsigned long offset, | |
1049 | const struct mmio_range *range) | |
1050 | { | |
1051 | u32 *data32 = (void *)mmio->data; | |
1052 | struct kvm_exit_mmio mmio32; | |
1053 | bool ret; | |
1054 | ||
1055 | if (likely(mmio->len <= 4)) | |
1056 | return range->handle_mmio(vcpu, mmio, offset); | |
1057 | ||
1058 | /* | |
1059 | * Any access bigger than 4 bytes (that we currently handle in KVM) | |
1060 | * is actually 8 bytes long, caused by a 64-bit access | |
1061 | */ | |
1062 | ||
1063 | mmio32.len = 4; | |
1064 | mmio32.is_write = mmio->is_write; | |
1065 | ||
1066 | mmio32.phys_addr = mmio->phys_addr + 4; | |
1067 | if (mmio->is_write) | |
1068 | *(u32 *)mmio32.data = data32[1]; | |
1069 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); | |
1070 | if (!mmio->is_write) | |
1071 | data32[1] = *(u32 *)mmio32.data; | |
1072 | ||
1073 | mmio32.phys_addr = mmio->phys_addr; | |
1074 | if (mmio->is_write) | |
1075 | *(u32 *)mmio32.data = data32[0]; | |
1076 | ret |= range->handle_mmio(vcpu, &mmio32, offset); | |
1077 | if (!mmio->is_write) | |
1078 | data32[0] = *(u32 *)mmio32.data; | |
1079 | ||
1080 | return ret; | |
1081 | } | |
1082 | ||
1a89dd91 | 1083 | /** |
96415257 | 1084 | * vgic_handle_mmio_range - handle an in-kernel MMIO access |
1a89dd91 MZ |
1085 | * @vcpu: pointer to the vcpu performing the access |
1086 | * @run: pointer to the kvm_run structure | |
1087 | * @mmio: pointer to the data describing the access | |
96415257 AP |
1088 | * @ranges: array of MMIO ranges in a given region |
1089 | * @mmio_base: base address of that region | |
1a89dd91 | 1090 | * |
96415257 | 1091 | * returns true if the MMIO access could be performed |
1a89dd91 | 1092 | */ |
96415257 AP |
1093 | static bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, |
1094 | struct kvm_exit_mmio *mmio, | |
1095 | const struct mmio_range *ranges, | |
1096 | unsigned long mmio_base) | |
1a89dd91 | 1097 | { |
b47ef92a MZ |
1098 | const struct mmio_range *range; |
1099 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
b47ef92a MZ |
1100 | bool updated_state; |
1101 | unsigned long offset; | |
1102 | ||
96415257 AP |
1103 | offset = mmio->phys_addr - mmio_base; |
1104 | range = find_matching_range(ranges, mmio, offset); | |
b47ef92a MZ |
1105 | if (unlikely(!range || !range->handle_mmio)) { |
1106 | pr_warn("Unhandled access %d %08llx %d\n", | |
1107 | mmio->is_write, mmio->phys_addr, mmio->len); | |
1108 | return false; | |
1109 | } | |
1110 | ||
1111 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
96415257 | 1112 | offset -= range->base; |
c3c91836 | 1113 | if (vgic_validate_access(dist, range, offset)) { |
05bc8aaf | 1114 | updated_state = call_range_handler(vcpu, mmio, offset, range); |
c3c91836 | 1115 | } else { |
05bc8aaf AP |
1116 | if (!mmio->is_write) |
1117 | memset(mmio->data, 0, mmio->len); | |
c3c91836 MZ |
1118 | updated_state = false; |
1119 | } | |
b47ef92a MZ |
1120 | spin_unlock(&vcpu->kvm->arch.vgic.lock); |
1121 | kvm_prepare_mmio(run, mmio); | |
1122 | kvm_handle_mmio_return(vcpu, run); | |
1123 | ||
5863c2ce MZ |
1124 | if (updated_state) |
1125 | vgic_kick_vcpus(vcpu->kvm); | |
1126 | ||
b47ef92a MZ |
1127 | return true; |
1128 | } | |
1129 | ||
96415257 AP |
1130 | static inline bool is_in_range(phys_addr_t addr, unsigned long len, |
1131 | phys_addr_t baseaddr, unsigned long size) | |
1132 | { | |
1133 | return (addr >= baseaddr) && (addr + len <= baseaddr + size); | |
1134 | } | |
1135 | ||
1136 | static bool vgic_v2_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
1137 | struct kvm_exit_mmio *mmio) | |
1138 | { | |
1139 | unsigned long base = vcpu->kvm->arch.vgic.vgic_dist_base; | |
1140 | ||
1141 | if (!is_in_range(mmio->phys_addr, mmio->len, base, | |
1142 | KVM_VGIC_V2_DIST_SIZE)) | |
1143 | return false; | |
1144 | ||
1145 | /* GICv2 does not support accesses wider than 32 bits */ | |
1146 | if (mmio->len > 4) { | |
1147 | kvm_inject_dabt(vcpu, mmio->phys_addr); | |
1148 | return true; | |
1149 | } | |
1150 | ||
1151 | return vgic_handle_mmio_range(vcpu, run, mmio, vgic_dist_ranges, base); | |
1152 | } | |
1153 | ||
1154 | /** | |
1155 | * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation | |
1156 | * @vcpu: pointer to the vcpu performing the access | |
1157 | * @run: pointer to the kvm_run structure | |
1158 | * @mmio: pointer to the data describing the access | |
1159 | * | |
1160 | * returns true if the MMIO access has been performed in kernel space, | |
1161 | * and false if it needs to be emulated in user space. | |
1162 | */ | |
1163 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
1164 | struct kvm_exit_mmio *mmio) | |
1165 | { | |
1166 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1167 | return false; | |
1168 | ||
1169 | return vgic_v2_handle_mmio(vcpu, run, mmio); | |
1170 | } | |
1171 | ||
c1bfb577 MZ |
1172 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi) |
1173 | { | |
1174 | return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi; | |
1175 | } | |
1176 | ||
b47ef92a MZ |
1177 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) |
1178 | { | |
1179 | struct kvm *kvm = vcpu->kvm; | |
1180 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1181 | int nrcpus = atomic_read(&kvm->online_vcpus); | |
1182 | u8 target_cpus; | |
1183 | int sgi, mode, c, vcpu_id; | |
1184 | ||
1185 | vcpu_id = vcpu->vcpu_id; | |
1186 | ||
1187 | sgi = reg & 0xf; | |
1188 | target_cpus = (reg >> 16) & 0xff; | |
1189 | mode = (reg >> 24) & 3; | |
1190 | ||
1191 | switch (mode) { | |
1192 | case 0: | |
1193 | if (!target_cpus) | |
1194 | return; | |
91021a6c | 1195 | break; |
b47ef92a MZ |
1196 | |
1197 | case 1: | |
1198 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; | |
1199 | break; | |
1200 | ||
1201 | case 2: | |
1202 | target_cpus = 1 << vcpu_id; | |
1203 | break; | |
1204 | } | |
1205 | ||
1206 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1207 | if (target_cpus & 1) { | |
1208 | /* Flag the SGI as pending */ | |
227844f5 | 1209 | vgic_dist_irq_set_pending(vcpu, sgi); |
c1bfb577 | 1210 | *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id; |
b47ef92a MZ |
1211 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); |
1212 | } | |
1213 | ||
1214 | target_cpus >>= 1; | |
1215 | } | |
1216 | } | |
1217 | ||
fb65ab63 MZ |
1218 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
1219 | { | |
1220 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
1221 | } | |
1222 | ||
b47ef92a MZ |
1223 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
1224 | { | |
9d949dce MZ |
1225 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1226 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
1227 | unsigned long pending_private, pending_shared; | |
fb65ab63 | 1228 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
1229 | int vcpu_id; |
1230 | ||
1231 | vcpu_id = vcpu->vcpu_id; | |
1232 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
1233 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
1234 | ||
227844f5 | 1235 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
1236 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
1237 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
1238 | ||
227844f5 | 1239 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce | 1240 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
fb65ab63 | 1241 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
9d949dce MZ |
1242 | bitmap_and(pend_shared, pend_shared, |
1243 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
fb65ab63 | 1244 | nr_shared); |
9d949dce MZ |
1245 | |
1246 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
fb65ab63 | 1247 | pending_shared = find_first_bit(pend_shared, nr_shared); |
9d949dce | 1248 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
fb65ab63 | 1249 | pending_shared < vgic_nr_shared_irqs(dist)); |
b47ef92a MZ |
1250 | } |
1251 | ||
1252 | /* | |
1253 | * Update the interrupt state and determine which CPUs have pending | |
1254 | * interrupts. Must be called with distributor lock held. | |
1255 | */ | |
1256 | static void vgic_update_state(struct kvm *kvm) | |
1257 | { | |
1258 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1259 | struct kvm_vcpu *vcpu; | |
1260 | int c; | |
1261 | ||
1262 | if (!dist->enabled) { | |
c1bfb577 | 1263 | set_bit(0, dist->irq_pending_on_cpu); |
b47ef92a MZ |
1264 | return; |
1265 | } | |
1266 | ||
1267 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1268 | if (compute_pending_for_cpu(vcpu)) { | |
1269 | pr_debug("CPU%d has pending interrupts\n", c); | |
c1bfb577 | 1270 | set_bit(c, dist->irq_pending_on_cpu); |
b47ef92a MZ |
1271 | } |
1272 | } | |
1a89dd91 | 1273 | } |
330690cd | 1274 | |
8d5c6b06 MZ |
1275 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
1276 | { | |
8f186d52 | 1277 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
1278 | } |
1279 | ||
1280 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
1281 | struct vgic_lr vlr) | |
1282 | { | |
8f186d52 | 1283 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
1284 | } |
1285 | ||
69bb2c9f MZ |
1286 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
1287 | struct vgic_lr vlr) | |
1288 | { | |
8f186d52 | 1289 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
1290 | } |
1291 | ||
1292 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
1293 | { | |
8f186d52 | 1294 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
1295 | } |
1296 | ||
8d6a0313 MZ |
1297 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
1298 | { | |
8f186d52 | 1299 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1300 | } |
1301 | ||
495dd859 MZ |
1302 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1303 | { | |
8f186d52 | 1304 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1305 | } |
1306 | ||
909d9b50 MZ |
1307 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1308 | { | |
8f186d52 | 1309 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1310 | } |
1311 | ||
1312 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1313 | { | |
8f186d52 | 1314 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1315 | } |
1316 | ||
beee38b9 MZ |
1317 | static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
1318 | { | |
8f186d52 | 1319 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1320 | } |
1321 | ||
1322 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) | |
1323 | { | |
8f186d52 | 1324 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1325 | } |
1326 | ||
da8dafd1 MZ |
1327 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1328 | { | |
8f186d52 | 1329 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1330 | } |
1331 | ||
8d5c6b06 MZ |
1332 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1333 | { | |
1334 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1335 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1336 | ||
1337 | vlr.state = 0; | |
1338 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1339 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1340 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1341 | } | |
a1fcb44e MZ |
1342 | |
1343 | /* | |
1344 | * An interrupt may have been disabled after being made pending on the | |
1345 | * CPU interface (the classic case is a timer running while we're | |
1346 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1347 | * interface gets enabled, with deadly consequences). | |
1348 | * | |
1349 | * The solution is to examine already active LRs, and check the | |
1350 | * interrupt is still enabled. If not, just retire it. | |
1351 | */ | |
1352 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1353 | { | |
1354 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1355 | int lr; | |
1356 | ||
8f186d52 | 1357 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1358 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1359 | |
8d5c6b06 MZ |
1360 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1361 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1362 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1363 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1364 | } |
1365 | } | |
1366 | } | |
1367 | ||
9d949dce MZ |
1368 | /* |
1369 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1370 | * or false if it wasn't possible to queue it. | |
1371 | */ | |
1372 | static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |
1373 | { | |
1374 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
5fb66da6 | 1375 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
8d5c6b06 | 1376 | struct vgic_lr vlr; |
9d949dce MZ |
1377 | int lr; |
1378 | ||
1379 | /* Sanitize the input... */ | |
1380 | BUG_ON(sgi_source_id & ~7); | |
1381 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
5fb66da6 | 1382 | BUG_ON(irq >= dist->nr_irqs); |
9d949dce MZ |
1383 | |
1384 | kvm_debug("Queue IRQ%d\n", irq); | |
1385 | ||
1386 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1387 | ||
1388 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1389 | if (lr != LR_EMPTY) { |
1390 | vlr = vgic_get_lr(vcpu, lr); | |
1391 | if (vlr.source == sgi_source_id) { | |
1392 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1393 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
1394 | vlr.state |= LR_STATE_PENDING; | |
1395 | vgic_set_lr(vcpu, lr, vlr); | |
1396 | return true; | |
1397 | } | |
9d949dce MZ |
1398 | } |
1399 | ||
1400 | /* Try to use another LR for this interrupt */ | |
1401 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1402 | vgic->nr_lr); |
1403 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1404 | return false; |
1405 | ||
1406 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1407 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1408 | set_bit(lr, vgic_cpu->lr_used); | |
1409 | ||
8d5c6b06 MZ |
1410 | vlr.irq = irq; |
1411 | vlr.source = sgi_source_id; | |
1412 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 1413 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
1414 | vlr.state |= LR_EOI_INT; |
1415 | ||
1416 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1417 | |
1418 | return true; | |
1419 | } | |
1420 | ||
1421 | static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
1422 | { | |
1423 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1424 | unsigned long sources; | |
1425 | int vcpu_id = vcpu->vcpu_id; | |
1426 | int c; | |
1427 | ||
c1bfb577 | 1428 | sources = *vgic_get_sgi_sources(dist, vcpu_id, irq); |
9d949dce | 1429 | |
fc675e35 | 1430 | for_each_set_bit(c, &sources, dist->nr_cpus) { |
9d949dce MZ |
1431 | if (vgic_queue_irq(vcpu, c, irq)) |
1432 | clear_bit(c, &sources); | |
1433 | } | |
1434 | ||
c1bfb577 | 1435 | *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources; |
9d949dce MZ |
1436 | |
1437 | /* | |
1438 | * If the sources bitmap has been cleared it means that we | |
1439 | * could queue all the SGIs onto link registers (see the | |
1440 | * clear_bit above), and therefore we are done with them in | |
1441 | * our emulated gic and can get rid of them. | |
1442 | */ | |
1443 | if (!sources) { | |
227844f5 | 1444 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1445 | vgic_cpu_irq_clear(vcpu, irq); |
1446 | return true; | |
1447 | } | |
1448 | ||
1449 | return false; | |
1450 | } | |
1451 | ||
1452 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) | |
1453 | { | |
dbf20f9d | 1454 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1455 | return true; /* level interrupt, already queued */ |
1456 | ||
1457 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1458 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1459 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1460 | vgic_cpu_irq_clear(vcpu, irq); |
1461 | } else { | |
dbf20f9d | 1462 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1463 | } |
1464 | ||
1465 | return true; | |
1466 | } | |
1467 | ||
1468 | return false; | |
1469 | } | |
1470 | ||
1471 | /* | |
1472 | * Fill the list registers with pending interrupts before running the | |
1473 | * guest. | |
1474 | */ | |
1475 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1476 | { | |
1477 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1478 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1479 | int i, vcpu_id; | |
1480 | int overflow = 0; | |
1481 | ||
1482 | vcpu_id = vcpu->vcpu_id; | |
1483 | ||
1484 | /* | |
1485 | * We may not have any pending interrupt, or the interrupts | |
1486 | * may have been serviced from another vcpu. In all cases, | |
1487 | * move along. | |
1488 | */ | |
1489 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1490 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1491 | goto epilog; | |
1492 | } | |
1493 | ||
1494 | /* SGIs */ | |
1495 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
1496 | if (!vgic_queue_sgi(vcpu, i)) | |
1497 | overflow = 1; | |
1498 | } | |
1499 | ||
1500 | /* PPIs */ | |
1501 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1502 | if (!vgic_queue_hwirq(vcpu, i)) | |
1503 | overflow = 1; | |
1504 | } | |
1505 | ||
1506 | /* SPIs */ | |
fb65ab63 | 1507 | for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) { |
9d949dce MZ |
1508 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
1509 | overflow = 1; | |
1510 | } | |
1511 | ||
1512 | epilog: | |
1513 | if (overflow) { | |
909d9b50 | 1514 | vgic_enable_underflow(vcpu); |
9d949dce | 1515 | } else { |
909d9b50 | 1516 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1517 | /* |
1518 | * We're about to run this VCPU, and we've consumed | |
1519 | * everything the distributor had in store for | |
1520 | * us. Claim we don't have anything pending. We'll | |
1521 | * adjust that if needed while exiting. | |
1522 | */ | |
c1bfb577 | 1523 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1524 | } |
1525 | } | |
1526 | ||
1527 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1528 | { | |
495dd859 | 1529 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1530 | bool level_pending = false; |
1531 | ||
495dd859 | 1532 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1533 | |
495dd859 | 1534 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1535 | /* |
1536 | * Some level interrupts have been EOIed. Clear their | |
1537 | * active bit. | |
1538 | */ | |
8d6a0313 | 1539 | u64 eisr = vgic_get_eisr(vcpu); |
2df36a5d | 1540 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
8d5c6b06 | 1541 | int lr; |
9d949dce | 1542 | |
8f186d52 | 1543 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1544 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1545 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1546 | |
dbf20f9d | 1547 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1548 | WARN_ON(vlr.state & LR_STATE_MASK); |
1549 | vlr.state = 0; | |
1550 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1551 | |
faa1b46c CD |
1552 | /* |
1553 | * If the IRQ was EOIed it was also ACKed and we we | |
1554 | * therefore assume we can clear the soft pending | |
1555 | * state (should it had been set) for this interrupt. | |
1556 | * | |
1557 | * Note: if the IRQ soft pending state was set after | |
1558 | * the IRQ was acked, it actually shouldn't be | |
1559 | * cleared, but we have no way of knowing that unless | |
1560 | * we start trapping ACKs when the soft-pending state | |
1561 | * is set. | |
1562 | */ | |
1563 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1564 | ||
9d949dce | 1565 | /* Any additional pending interrupt? */ |
faa1b46c | 1566 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1567 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1568 | level_pending = true; |
1569 | } else { | |
faa1b46c | 1570 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1571 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1572 | } |
75da01e1 MZ |
1573 | |
1574 | /* | |
1575 | * Despite being EOIed, the LR may not have | |
1576 | * been marked as empty. | |
1577 | */ | |
69bb2c9f | 1578 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1579 | } |
1580 | } | |
1581 | ||
495dd859 | 1582 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1583 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1584 | |
1585 | return level_pending; | |
1586 | } | |
1587 | ||
1588 | /* | |
33c83cb3 MZ |
1589 | * Sync back the VGIC state after a guest run. The distributor lock is |
1590 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1591 | */ |
1592 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1593 | { | |
1594 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1595 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1596 | u64 elrsr; |
1597 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1598 | int lr, pending; |
1599 | bool level_pending; | |
1600 | ||
1601 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f | 1602 | elrsr = vgic_get_elrsr(vcpu); |
2df36a5d | 1603 | elrsr_ptr = u64_to_bitmask(&elrsr); |
9d949dce MZ |
1604 | |
1605 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1606 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1607 | struct vgic_lr vlr; |
9d949dce MZ |
1608 | |
1609 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1610 | continue; | |
1611 | ||
8d5c6b06 | 1612 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1613 | |
5fb66da6 | 1614 | BUG_ON(vlr.irq >= dist->nr_irqs); |
8d5c6b06 | 1615 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
9d949dce MZ |
1616 | } |
1617 | ||
1618 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1619 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1620 | if (level_pending || pending < vgic->nr_lr) | |
c1bfb577 | 1621 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1622 | } |
1623 | ||
1624 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1625 | { | |
1626 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1627 | ||
1628 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1629 | return; | |
1630 | ||
1631 | spin_lock(&dist->lock); | |
1632 | __kvm_vgic_flush_hwstate(vcpu); | |
1633 | spin_unlock(&dist->lock); | |
1634 | } | |
1635 | ||
1636 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1637 | { | |
33c83cb3 MZ |
1638 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1639 | ||
9d949dce MZ |
1640 | if (!irqchip_in_kernel(vcpu->kvm)) |
1641 | return; | |
1642 | ||
33c83cb3 | 1643 | spin_lock(&dist->lock); |
9d949dce | 1644 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1645 | spin_unlock(&dist->lock); |
9d949dce MZ |
1646 | } |
1647 | ||
1648 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1649 | { | |
1650 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1651 | ||
1652 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1653 | return 0; | |
1654 | ||
c1bfb577 | 1655 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1656 | } |
1657 | ||
5863c2ce MZ |
1658 | static void vgic_kick_vcpus(struct kvm *kvm) |
1659 | { | |
1660 | struct kvm_vcpu *vcpu; | |
1661 | int c; | |
1662 | ||
1663 | /* | |
1664 | * We've injected an interrupt, time to find out who deserves | |
1665 | * a good kick... | |
1666 | */ | |
1667 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1668 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1669 | kvm_vcpu_kick(vcpu); | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1674 | { | |
227844f5 | 1675 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1676 | |
1677 | /* | |
1678 | * Only inject an interrupt if: | |
1679 | * - edge triggered and we have a rising edge | |
1680 | * - level triggered and we change level | |
1681 | */ | |
faa1b46c CD |
1682 | if (edge_triggered) { |
1683 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1684 | return level > state; |
faa1b46c CD |
1685 | } else { |
1686 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1687 | return level != state; |
faa1b46c | 1688 | } |
5863c2ce MZ |
1689 | } |
1690 | ||
016ed39c | 1691 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1692 | unsigned int irq_num, bool level) |
1693 | { | |
1694 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1695 | struct kvm_vcpu *vcpu; | |
227844f5 | 1696 | int edge_triggered, level_triggered; |
5863c2ce MZ |
1697 | int enabled; |
1698 | bool ret = true; | |
1699 | ||
1700 | spin_lock(&dist->lock); | |
1701 | ||
1702 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1703 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1704 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1705 | |
1706 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1707 | ret = false; | |
1708 | goto out; | |
1709 | } | |
1710 | ||
1711 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1712 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
1713 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1714 | } | |
1715 | ||
1716 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1717 | ||
faa1b46c CD |
1718 | if (level) { |
1719 | if (level_triggered) | |
1720 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1721 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1722 | } else { |
1723 | if (level_triggered) { | |
1724 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1725 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1726 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
faa1b46c | 1727 | } |
7d39f9e3 | 1728 | |
1729 | ret = false; | |
1730 | goto out; | |
faa1b46c | 1731 | } |
5863c2ce MZ |
1732 | |
1733 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1734 | ||
1735 | if (!enabled) { | |
1736 | ret = false; | |
1737 | goto out; | |
1738 | } | |
1739 | ||
dbf20f9d | 1740 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1741 | /* |
1742 | * Level interrupt in progress, will be picked up | |
1743 | * when EOId. | |
1744 | */ | |
1745 | ret = false; | |
1746 | goto out; | |
1747 | } | |
1748 | ||
1749 | if (level) { | |
1750 | vgic_cpu_irq_set(vcpu, irq_num); | |
c1bfb577 | 1751 | set_bit(cpuid, dist->irq_pending_on_cpu); |
5863c2ce MZ |
1752 | } |
1753 | ||
1754 | out: | |
1755 | spin_unlock(&dist->lock); | |
1756 | ||
016ed39c | 1757 | return ret ? cpuid : -EINVAL; |
5863c2ce MZ |
1758 | } |
1759 | ||
1760 | /** | |
1761 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1762 | * @kvm: The VM structure pointer | |
1763 | * @cpuid: The CPU for PPIs | |
1764 | * @irq_num: The IRQ number that is assigned to the device | |
1765 | * @level: Edge-triggered: true: to trigger the interrupt | |
1766 | * false: to ignore the call | |
1767 | * Level-sensitive true: activates an interrupt | |
1768 | * false: deactivates an interrupt | |
1769 | * | |
1770 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1771 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1772 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1773 | */ | |
1774 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1775 | bool level) | |
1776 | { | |
ca7d9c82 | 1777 | int ret = 0; |
016ed39c | 1778 | int vcpu_id; |
5863c2ce | 1779 | |
ca7d9c82 | 1780 | if (unlikely(!vgic_initialized(kvm))) { |
59892136 AP |
1781 | /* |
1782 | * We only provide the automatic initialization of the VGIC | |
1783 | * for the legacy case of a GICv2. Any other type must | |
1784 | * be explicitly initialized once setup with the respective | |
1785 | * KVM device call. | |
1786 | */ | |
1787 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) { | |
1788 | ret = -EBUSY; | |
1789 | goto out; | |
1790 | } | |
ca7d9c82 CD |
1791 | mutex_lock(&kvm->lock); |
1792 | ret = vgic_init(kvm); | |
1793 | mutex_unlock(&kvm->lock); | |
1794 | ||
1795 | if (ret) | |
1796 | goto out; | |
016ed39c | 1797 | } |
5863c2ce | 1798 | |
ca7d9c82 CD |
1799 | vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level); |
1800 | if (vcpu_id >= 0) { | |
1801 | /* kick the specified vcpu */ | |
1802 | kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id)); | |
1803 | } | |
1804 | ||
1805 | out: | |
1806 | return ret; | |
5863c2ce MZ |
1807 | } |
1808 | ||
01ac5e34 MZ |
1809 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1810 | { | |
1811 | /* | |
1812 | * We cannot rely on the vgic maintenance interrupt to be | |
1813 | * delivered synchronously. This means we can only use it to | |
1814 | * exit the VM, and we perform the handling of EOIed | |
1815 | * interrupts on the exit path (see vgic_process_maintenance). | |
1816 | */ | |
1817 | return IRQ_HANDLED; | |
1818 | } | |
1819 | ||
c1bfb577 MZ |
1820 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
1821 | { | |
1822 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1823 | ||
1824 | kfree(vgic_cpu->pending_shared); | |
1825 | kfree(vgic_cpu->vgic_irq_lr_map); | |
1826 | vgic_cpu->pending_shared = NULL; | |
1827 | vgic_cpu->vgic_irq_lr_map = NULL; | |
1828 | } | |
1829 | ||
1830 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) | |
1831 | { | |
1832 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1833 | ||
1834 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; | |
1835 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); | |
6d3cfbe2 | 1836 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
c1bfb577 MZ |
1837 | |
1838 | if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) { | |
1839 | kvm_vgic_vcpu_destroy(vcpu); | |
1840 | return -ENOMEM; | |
1841 | } | |
1842 | ||
6d3cfbe2 | 1843 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
01ac5e34 MZ |
1844 | |
1845 | /* | |
ca85f623 MZ |
1846 | * Store the number of LRs per vcpu, so we don't have to go |
1847 | * all the way to the distributor structure to find out. Only | |
1848 | * assembly code should use this one. | |
01ac5e34 | 1849 | */ |
8f186d52 | 1850 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1851 | |
6d3cfbe2 | 1852 | return 0; |
01ac5e34 MZ |
1853 | } |
1854 | ||
c1bfb577 MZ |
1855 | void kvm_vgic_destroy(struct kvm *kvm) |
1856 | { | |
1857 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1858 | struct kvm_vcpu *vcpu; | |
1859 | int i; | |
1860 | ||
1861 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1862 | kvm_vgic_vcpu_destroy(vcpu); | |
1863 | ||
1864 | vgic_free_bitmap(&dist->irq_enabled); | |
1865 | vgic_free_bitmap(&dist->irq_level); | |
1866 | vgic_free_bitmap(&dist->irq_pending); | |
1867 | vgic_free_bitmap(&dist->irq_soft_pend); | |
1868 | vgic_free_bitmap(&dist->irq_queued); | |
1869 | vgic_free_bitmap(&dist->irq_cfg); | |
1870 | vgic_free_bytemap(&dist->irq_priority); | |
1871 | if (dist->irq_spi_target) { | |
1872 | for (i = 0; i < dist->nr_cpus; i++) | |
1873 | vgic_free_bitmap(&dist->irq_spi_target[i]); | |
1874 | } | |
1875 | kfree(dist->irq_sgi_sources); | |
1876 | kfree(dist->irq_spi_cpu); | |
1877 | kfree(dist->irq_spi_target); | |
1878 | kfree(dist->irq_pending_on_cpu); | |
1879 | dist->irq_sgi_sources = NULL; | |
1880 | dist->irq_spi_cpu = NULL; | |
1881 | dist->irq_spi_target = NULL; | |
1882 | dist->irq_pending_on_cpu = NULL; | |
1f57be28 | 1883 | dist->nr_cpus = 0; |
c1bfb577 MZ |
1884 | } |
1885 | ||
1886 | /* | |
1887 | * Allocate and initialize the various data structures. Must be called | |
1888 | * with kvm->lock held! | |
1889 | */ | |
6d3cfbe2 | 1890 | static int vgic_init(struct kvm *kvm) |
c1bfb577 MZ |
1891 | { |
1892 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1893 | struct kvm_vcpu *vcpu; | |
1894 | int nr_cpus, nr_irqs; | |
6d3cfbe2 | 1895 | int ret, i, vcpu_id; |
c1bfb577 | 1896 | |
1f57be28 | 1897 | if (vgic_initialized(kvm)) |
4956f2bc MZ |
1898 | return 0; |
1899 | ||
1900 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); | |
1901 | if (!nr_cpus) /* No vcpus? Can't be good... */ | |
66b030e4 | 1902 | return -ENODEV; |
5fb66da6 | 1903 | |
4956f2bc MZ |
1904 | /* |
1905 | * If nobody configured the number of interrupts, use the | |
1906 | * legacy one. | |
1907 | */ | |
5fb66da6 MZ |
1908 | if (!dist->nr_irqs) |
1909 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; | |
1910 | ||
1911 | nr_irqs = dist->nr_irqs; | |
c1bfb577 MZ |
1912 | |
1913 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); | |
1914 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); | |
1915 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); | |
1916 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); | |
1917 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); | |
1918 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); | |
1919 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); | |
1920 | ||
1921 | if (ret) | |
1922 | goto out; | |
1923 | ||
1924 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); | |
1925 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); | |
1926 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, | |
1927 | GFP_KERNEL); | |
1928 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), | |
1929 | GFP_KERNEL); | |
1930 | if (!dist->irq_sgi_sources || | |
1931 | !dist->irq_spi_cpu || | |
1932 | !dist->irq_spi_target || | |
1933 | !dist->irq_pending_on_cpu) { | |
1934 | ret = -ENOMEM; | |
1935 | goto out; | |
1936 | } | |
1937 | ||
1938 | for (i = 0; i < nr_cpus; i++) | |
1939 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], | |
1940 | nr_cpus, nr_irqs); | |
1941 | ||
1942 | if (ret) | |
1943 | goto out; | |
1944 | ||
6d3cfbe2 PM |
1945 | for (i = VGIC_NR_PRIVATE_IRQS; i < dist->nr_irqs; i += 4) |
1946 | vgic_set_target_reg(kvm, 0, i); | |
1947 | ||
1948 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { | |
c1bfb577 MZ |
1949 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
1950 | if (ret) { | |
1951 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); | |
1952 | break; | |
1953 | } | |
c1bfb577 | 1954 | |
6d3cfbe2 PM |
1955 | for (i = 0; i < dist->nr_irqs; i++) { |
1956 | if (i < VGIC_NR_PPIS) | |
1957 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1958 | vcpu->vcpu_id, i, 1); | |
1959 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1960 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1961 | vcpu->vcpu_id, i, | |
1962 | VGIC_CFG_EDGE); | |
1963 | } | |
1964 | ||
1965 | vgic_enable(vcpu); | |
1966 | } | |
4956f2bc | 1967 | |
c1bfb577 MZ |
1968 | out: |
1969 | if (ret) | |
1970 | kvm_vgic_destroy(kvm); | |
1971 | ||
1972 | return ret; | |
1973 | } | |
1974 | ||
e1ba0207 | 1975 | /** |
6d3cfbe2 | 1976 | * kvm_vgic_map_resources - Configure global VGIC state before running any VCPUs |
e1ba0207 CD |
1977 | * @kvm: pointer to the kvm struct |
1978 | * | |
1979 | * Map the virtual CPU interface into the VM before running any VCPUs. We | |
1980 | * can't do this at creation time, because user space must first set the | |
6d3cfbe2 | 1981 | * virtual CPU interface address in the guest physical address space. |
e1ba0207 | 1982 | */ |
6d3cfbe2 | 1983 | int kvm_vgic_map_resources(struct kvm *kvm) |
01ac5e34 | 1984 | { |
6d3cfbe2 | 1985 | int ret = 0; |
01ac5e34 | 1986 | |
e1ba0207 CD |
1987 | if (!irqchip_in_kernel(kvm)) |
1988 | return 0; | |
1989 | ||
01ac5e34 MZ |
1990 | mutex_lock(&kvm->lock); |
1991 | ||
c52edf5f | 1992 | if (vgic_ready(kvm)) |
01ac5e34 MZ |
1993 | goto out; |
1994 | ||
1995 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || | |
1996 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { | |
1997 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
1998 | ret = -ENXIO; | |
1999 | goto out; | |
2000 | } | |
2001 | ||
6d3cfbe2 PM |
2002 | /* |
2003 | * Initialize the vgic if this hasn't already been done on demand by | |
2004 | * accessing the vgic state from userspace. | |
2005 | */ | |
2006 | ret = vgic_init(kvm); | |
4956f2bc MZ |
2007 | if (ret) { |
2008 | kvm_err("Unable to allocate maps\n"); | |
2009 | goto out; | |
2010 | } | |
2011 | ||
01ac5e34 | 2012 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, |
c40f2f8f AB |
2013 | vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE, |
2014 | true); | |
01ac5e34 MZ |
2015 | if (ret) { |
2016 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
2017 | goto out; | |
2018 | } | |
2019 | ||
01ac5e34 MZ |
2020 | kvm->arch.vgic.ready = true; |
2021 | out: | |
4956f2bc MZ |
2022 | if (ret) |
2023 | kvm_vgic_destroy(kvm); | |
01ac5e34 MZ |
2024 | mutex_unlock(&kvm->lock); |
2025 | return ret; | |
2026 | } | |
2027 | ||
59892136 | 2028 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
01ac5e34 | 2029 | { |
6b50f540 | 2030 | int i, vcpu_lock_idx = -1, ret; |
7330672b | 2031 | struct kvm_vcpu *vcpu; |
01ac5e34 MZ |
2032 | |
2033 | mutex_lock(&kvm->lock); | |
2034 | ||
7330672b | 2035 | if (kvm->arch.vgic.vctrl_base) { |
01ac5e34 MZ |
2036 | ret = -EEXIST; |
2037 | goto out; | |
2038 | } | |
2039 | ||
7330672b CD |
2040 | /* |
2041 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
2042 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
2043 | * that no other VCPUs are run while we create the vgic. | |
2044 | */ | |
6b50f540 | 2045 | ret = -EBUSY; |
7330672b CD |
2046 | kvm_for_each_vcpu(i, vcpu, kvm) { |
2047 | if (!mutex_trylock(&vcpu->mutex)) | |
2048 | goto out_unlock; | |
2049 | vcpu_lock_idx = i; | |
2050 | } | |
2051 | ||
2052 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6b50f540 | 2053 | if (vcpu->arch.has_run_once) |
7330672b | 2054 | goto out_unlock; |
7330672b | 2055 | } |
6b50f540 | 2056 | ret = 0; |
7330672b | 2057 | |
01ac5e34 | 2058 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 2059 | kvm->arch.vgic.in_kernel = true; |
59892136 | 2060 | kvm->arch.vgic.vgic_model = type; |
8f186d52 | 2061 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
2062 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
2063 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
2064 | ||
7330672b CD |
2065 | out_unlock: |
2066 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
2067 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
2068 | mutex_unlock(&vcpu->mutex); | |
2069 | } | |
2070 | ||
01ac5e34 MZ |
2071 | out: |
2072 | mutex_unlock(&kvm->lock); | |
2073 | return ret; | |
2074 | } | |
2075 | ||
1fa451bc | 2076 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
2077 | { |
2078 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
2079 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
2080 | ||
2081 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
2082 | return 0; | |
2083 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
2084 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
2085 | return -EBUSY; | |
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
2090 | phys_addr_t addr, phys_addr_t size) | |
2091 | { | |
2092 | int ret; | |
2093 | ||
ce01e4e8 CD |
2094 | if (addr & ~KVM_PHYS_MASK) |
2095 | return -E2BIG; | |
2096 | ||
2097 | if (addr & (SZ_4K - 1)) | |
2098 | return -EINVAL; | |
2099 | ||
330690cd CD |
2100 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
2101 | return -EEXIST; | |
2102 | if (addr + size < addr) | |
2103 | return -EINVAL; | |
2104 | ||
30c21170 | 2105 | *ioaddr = addr; |
330690cd CD |
2106 | ret = vgic_ioaddr_overlap(kvm); |
2107 | if (ret) | |
30c21170 HW |
2108 | *ioaddr = VGIC_ADDR_UNDEF; |
2109 | ||
330690cd CD |
2110 | return ret; |
2111 | } | |
2112 | ||
ce01e4e8 CD |
2113 | /** |
2114 | * kvm_vgic_addr - set or get vgic VM base addresses | |
2115 | * @kvm: pointer to the vm struct | |
2116 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX | |
2117 | * @addr: pointer to address value | |
2118 | * @write: if true set the address in the VM address space, if false read the | |
2119 | * address | |
2120 | * | |
2121 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
2122 | * interface in the VM physical address space. These addresses are properties | |
2123 | * of the emulated core/SoC and therefore user space initially knows this | |
2124 | * information. | |
2125 | */ | |
2126 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
2127 | { |
2128 | int r = 0; | |
2129 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
2130 | ||
330690cd CD |
2131 | mutex_lock(&kvm->lock); |
2132 | switch (type) { | |
2133 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ce01e4e8 CD |
2134 | if (write) { |
2135 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, | |
2136 | *addr, KVM_VGIC_V2_DIST_SIZE); | |
2137 | } else { | |
2138 | *addr = vgic->vgic_dist_base; | |
2139 | } | |
330690cd CD |
2140 | break; |
2141 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ce01e4e8 CD |
2142 | if (write) { |
2143 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, | |
2144 | *addr, KVM_VGIC_V2_CPU_SIZE); | |
2145 | } else { | |
2146 | *addr = vgic->vgic_cpu_base; | |
2147 | } | |
330690cd CD |
2148 | break; |
2149 | default: | |
2150 | r = -ENODEV; | |
2151 | } | |
2152 | ||
2153 | mutex_unlock(&kvm->lock); | |
2154 | return r; | |
2155 | } | |
7330672b | 2156 | |
c07a0191 CD |
2157 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
2158 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
2159 | { | |
fa20f5ae | 2160 | bool updated = false; |
beee38b9 MZ |
2161 | struct vgic_vmcr vmcr; |
2162 | u32 *vmcr_field; | |
2163 | u32 reg; | |
2164 | ||
2165 | vgic_get_vmcr(vcpu, &vmcr); | |
fa20f5ae CD |
2166 | |
2167 | switch (offset & ~0x3) { | |
2168 | case GIC_CPU_CTRL: | |
beee38b9 | 2169 | vmcr_field = &vmcr.ctlr; |
fa20f5ae CD |
2170 | break; |
2171 | case GIC_CPU_PRIMASK: | |
beee38b9 | 2172 | vmcr_field = &vmcr.pmr; |
fa20f5ae CD |
2173 | break; |
2174 | case GIC_CPU_BINPOINT: | |
beee38b9 | 2175 | vmcr_field = &vmcr.bpr; |
fa20f5ae CD |
2176 | break; |
2177 | case GIC_CPU_ALIAS_BINPOINT: | |
beee38b9 | 2178 | vmcr_field = &vmcr.abpr; |
fa20f5ae | 2179 | break; |
beee38b9 MZ |
2180 | default: |
2181 | BUG(); | |
fa20f5ae CD |
2182 | } |
2183 | ||
2184 | if (!mmio->is_write) { | |
beee38b9 | 2185 | reg = *vmcr_field; |
fa20f5ae CD |
2186 | mmio_data_write(mmio, ~0, reg); |
2187 | } else { | |
2188 | reg = mmio_data_read(mmio, ~0); | |
beee38b9 MZ |
2189 | if (reg != *vmcr_field) { |
2190 | *vmcr_field = reg; | |
2191 | vgic_set_vmcr(vcpu, &vmcr); | |
fa20f5ae | 2192 | updated = true; |
beee38b9 | 2193 | } |
fa20f5ae CD |
2194 | } |
2195 | return updated; | |
2196 | } | |
2197 | ||
2198 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, | |
2199 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
2200 | { | |
2201 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); | |
c07a0191 CD |
2202 | } |
2203 | ||
fa20f5ae CD |
2204 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
2205 | struct kvm_exit_mmio *mmio, | |
2206 | phys_addr_t offset) | |
2207 | { | |
2208 | u32 reg; | |
2209 | ||
2210 | if (mmio->is_write) | |
2211 | return false; | |
2212 | ||
2213 | /* GICC_IIDR */ | |
2214 | reg = (PRODUCT_ID_KVM << 20) | | |
2215 | (GICC_ARCH_VERSION_V2 << 16) | | |
2216 | (IMPLEMENTER_ARM << 0); | |
2217 | mmio_data_write(mmio, ~0, reg); | |
2218 | return false; | |
2219 | } | |
2220 | ||
2221 | /* | |
2222 | * CPU Interface Register accesses - these are not accessed by the VM, but by | |
2223 | * user space for saving and restoring VGIC state. | |
2224 | */ | |
c07a0191 CD |
2225 | static const struct mmio_range vgic_cpu_ranges[] = { |
2226 | { | |
2227 | .base = GIC_CPU_CTRL, | |
2228 | .len = 12, | |
2229 | .handle_mmio = handle_cpu_mmio_misc, | |
2230 | }, | |
2231 | { | |
2232 | .base = GIC_CPU_ALIAS_BINPOINT, | |
2233 | .len = 4, | |
fa20f5ae | 2234 | .handle_mmio = handle_mmio_abpr, |
c07a0191 CD |
2235 | }, |
2236 | { | |
2237 | .base = GIC_CPU_ACTIVEPRIO, | |
2238 | .len = 16, | |
fa20f5ae | 2239 | .handle_mmio = handle_mmio_raz_wi, |
c07a0191 CD |
2240 | }, |
2241 | { | |
2242 | .base = GIC_CPU_IDENT, | |
2243 | .len = 4, | |
fa20f5ae | 2244 | .handle_mmio = handle_cpu_mmio_ident, |
c07a0191 CD |
2245 | }, |
2246 | }; | |
2247 | ||
2248 | static int vgic_attr_regs_access(struct kvm_device *dev, | |
2249 | struct kvm_device_attr *attr, | |
2250 | u32 *reg, bool is_write) | |
2251 | { | |
2252 | const struct mmio_range *r = NULL, *ranges; | |
2253 | phys_addr_t offset; | |
2254 | int ret, cpuid, c; | |
2255 | struct kvm_vcpu *vcpu, *tmp_vcpu; | |
2256 | struct vgic_dist *vgic; | |
2257 | struct kvm_exit_mmio mmio; | |
2258 | ||
2259 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2260 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> | |
2261 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; | |
2262 | ||
2263 | mutex_lock(&dev->kvm->lock); | |
2264 | ||
6d3cfbe2 | 2265 | ret = vgic_init(dev->kvm); |
4956f2bc MZ |
2266 | if (ret) |
2267 | goto out; | |
2268 | ||
c07a0191 CD |
2269 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { |
2270 | ret = -EINVAL; | |
2271 | goto out; | |
2272 | } | |
2273 | ||
2274 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); | |
2275 | vgic = &dev->kvm->arch.vgic; | |
2276 | ||
2277 | mmio.len = 4; | |
2278 | mmio.is_write = is_write; | |
2279 | if (is_write) | |
2280 | mmio_data_write(&mmio, ~0, *reg); | |
2281 | switch (attr->group) { | |
2282 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2283 | mmio.phys_addr = vgic->vgic_dist_base + offset; | |
2284 | ranges = vgic_dist_ranges; | |
2285 | break; | |
2286 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2287 | mmio.phys_addr = vgic->vgic_cpu_base + offset; | |
2288 | ranges = vgic_cpu_ranges; | |
2289 | break; | |
2290 | default: | |
2291 | BUG(); | |
2292 | } | |
2293 | r = find_matching_range(ranges, &mmio, offset); | |
2294 | ||
2295 | if (unlikely(!r || !r->handle_mmio)) { | |
2296 | ret = -ENXIO; | |
2297 | goto out; | |
2298 | } | |
2299 | ||
2300 | ||
2301 | spin_lock(&vgic->lock); | |
2302 | ||
2303 | /* | |
2304 | * Ensure that no other VCPU is running by checking the vcpu->cpu | |
2305 | * field. If no other VPCUs are running we can safely access the VGIC | |
2306 | * state, because even if another VPU is run after this point, that | |
2307 | * VCPU will not touch the vgic state, because it will block on | |
2308 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). | |
2309 | */ | |
2310 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { | |
2311 | if (unlikely(tmp_vcpu->cpu != -1)) { | |
2312 | ret = -EBUSY; | |
2313 | goto out_vgic_unlock; | |
2314 | } | |
2315 | } | |
2316 | ||
cbd333a4 CD |
2317 | /* |
2318 | * Move all pending IRQs from the LRs on all VCPUs so the pending | |
2319 | * state can be properly represented in the register state accessible | |
2320 | * through this API. | |
2321 | */ | |
2322 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) | |
2323 | vgic_unqueue_irqs(tmp_vcpu); | |
2324 | ||
c07a0191 CD |
2325 | offset -= r->base; |
2326 | r->handle_mmio(vcpu, &mmio, offset); | |
2327 | ||
2328 | if (!is_write) | |
2329 | *reg = mmio_data_read(&mmio, ~0); | |
2330 | ||
2331 | ret = 0; | |
2332 | out_vgic_unlock: | |
2333 | spin_unlock(&vgic->lock); | |
2334 | out: | |
2335 | mutex_unlock(&dev->kvm->lock); | |
2336 | return ret; | |
2337 | } | |
2338 | ||
7330672b CD |
2339 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2340 | { | |
ce01e4e8 CD |
2341 | int r; |
2342 | ||
2343 | switch (attr->group) { | |
2344 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2345 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2346 | u64 addr; | |
2347 | unsigned long type = (unsigned long)attr->attr; | |
2348 | ||
2349 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
2350 | return -EFAULT; | |
2351 | ||
2352 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
2353 | return (r == -ENODEV) ? -ENXIO : r; | |
2354 | } | |
c07a0191 CD |
2355 | |
2356 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2357 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2358 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2359 | u32 reg; | |
2360 | ||
2361 | if (get_user(reg, uaddr)) | |
2362 | return -EFAULT; | |
2363 | ||
2364 | return vgic_attr_regs_access(dev, attr, ®, true); | |
2365 | } | |
a98f26f1 MZ |
2366 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
2367 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2368 | u32 val; | |
2369 | int ret = 0; | |
2370 | ||
2371 | if (get_user(val, uaddr)) | |
2372 | return -EFAULT; | |
2373 | ||
2374 | /* | |
2375 | * We require: | |
2376 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs | |
2377 | * - at most 1024 interrupts | |
2378 | * - a multiple of 32 interrupts | |
2379 | */ | |
2380 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || | |
2381 | val > VGIC_MAX_IRQS || | |
2382 | (val & 31)) | |
2383 | return -EINVAL; | |
2384 | ||
2385 | mutex_lock(&dev->kvm->lock); | |
2386 | ||
c52edf5f | 2387 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
a98f26f1 MZ |
2388 | ret = -EBUSY; |
2389 | else | |
2390 | dev->kvm->arch.vgic.nr_irqs = val; | |
2391 | ||
2392 | mutex_unlock(&dev->kvm->lock); | |
2393 | ||
2394 | return ret; | |
2395 | } | |
065c0034 EA |
2396 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
2397 | switch (attr->attr) { | |
2398 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
2399 | r = vgic_init(dev->kvm); | |
2400 | return r; | |
2401 | } | |
2402 | break; | |
2403 | } | |
ce01e4e8 CD |
2404 | } |
2405 | ||
7330672b CD |
2406 | return -ENXIO; |
2407 | } | |
2408 | ||
2409 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
2410 | { | |
ce01e4e8 CD |
2411 | int r = -ENXIO; |
2412 | ||
2413 | switch (attr->group) { | |
2414 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2415 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2416 | u64 addr; | |
2417 | unsigned long type = (unsigned long)attr->attr; | |
2418 | ||
2419 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
2420 | if (r) | |
2421 | return (r == -ENODEV) ? -ENXIO : r; | |
2422 | ||
2423 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
2424 | return -EFAULT; | |
c07a0191 CD |
2425 | break; |
2426 | } | |
2427 | ||
2428 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2429 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2430 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2431 | u32 reg = 0; | |
2432 | ||
2433 | r = vgic_attr_regs_access(dev, attr, ®, false); | |
2434 | if (r) | |
2435 | return r; | |
2436 | r = put_user(reg, uaddr); | |
2437 | break; | |
ce01e4e8 | 2438 | } |
a98f26f1 MZ |
2439 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
2440 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2441 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); | |
2442 | break; | |
2443 | } | |
c07a0191 | 2444 | |
ce01e4e8 CD |
2445 | } |
2446 | ||
2447 | return r; | |
7330672b CD |
2448 | } |
2449 | ||
c07a0191 CD |
2450 | static int vgic_has_attr_regs(const struct mmio_range *ranges, |
2451 | phys_addr_t offset) | |
2452 | { | |
2453 | struct kvm_exit_mmio dev_attr_mmio; | |
2454 | ||
2455 | dev_attr_mmio.len = 4; | |
2456 | if (find_matching_range(ranges, &dev_attr_mmio, offset)) | |
2457 | return 0; | |
2458 | else | |
2459 | return -ENXIO; | |
2460 | } | |
2461 | ||
7330672b CD |
2462 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2463 | { | |
c07a0191 CD |
2464 | phys_addr_t offset; |
2465 | ||
ce01e4e8 CD |
2466 | switch (attr->group) { |
2467 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
2468 | switch (attr->attr) { | |
2469 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
2470 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
2471 | return 0; | |
2472 | } | |
2473 | break; | |
c07a0191 CD |
2474 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
2475 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2476 | return vgic_has_attr_regs(vgic_dist_ranges, offset); | |
2477 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2478 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2479 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); | |
a98f26f1 MZ |
2480 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: |
2481 | return 0; | |
065c0034 EA |
2482 | case KVM_DEV_ARM_VGIC_GRP_CTRL: |
2483 | switch (attr->attr) { | |
2484 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
2485 | return 0; | |
2486 | } | |
ce01e4e8 | 2487 | } |
7330672b CD |
2488 | return -ENXIO; |
2489 | } | |
2490 | ||
2491 | static void vgic_destroy(struct kvm_device *dev) | |
2492 | { | |
2493 | kfree(dev); | |
2494 | } | |
2495 | ||
2496 | static int vgic_create(struct kvm_device *dev, u32 type) | |
2497 | { | |
59892136 | 2498 | return kvm_vgic_create(dev->kvm, type); |
7330672b CD |
2499 | } |
2500 | ||
c06a841b | 2501 | static struct kvm_device_ops kvm_arm_vgic_v2_ops = { |
7330672b CD |
2502 | .name = "kvm-arm-vgic", |
2503 | .create = vgic_create, | |
2504 | .destroy = vgic_destroy, | |
2505 | .set_attr = vgic_set_attr, | |
2506 | .get_attr = vgic_get_attr, | |
2507 | .has_attr = vgic_has_attr, | |
2508 | }; | |
c06a841b WD |
2509 | |
2510 | static void vgic_init_maintenance_interrupt(void *info) | |
2511 | { | |
2512 | enable_percpu_irq(vgic->maint_irq, 0); | |
2513 | } | |
2514 | ||
2515 | static int vgic_cpu_notify(struct notifier_block *self, | |
2516 | unsigned long action, void *cpu) | |
2517 | { | |
2518 | switch (action) { | |
2519 | case CPU_STARTING: | |
2520 | case CPU_STARTING_FROZEN: | |
2521 | vgic_init_maintenance_interrupt(NULL); | |
2522 | break; | |
2523 | case CPU_DYING: | |
2524 | case CPU_DYING_FROZEN: | |
2525 | disable_percpu_irq(vgic->maint_irq); | |
2526 | break; | |
2527 | } | |
2528 | ||
2529 | return NOTIFY_OK; | |
2530 | } | |
2531 | ||
2532 | static struct notifier_block vgic_cpu_nb = { | |
2533 | .notifier_call = vgic_cpu_notify, | |
2534 | }; | |
2535 | ||
2536 | static const struct of_device_id vgic_ids[] = { | |
2537 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
2538 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
2539 | {}, | |
2540 | }; | |
2541 | ||
2542 | int kvm_vgic_hyp_init(void) | |
2543 | { | |
2544 | const struct of_device_id *matched_id; | |
a875dafc CD |
2545 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2546 | const struct vgic_params **); | |
c06a841b WD |
2547 | struct device_node *vgic_node; |
2548 | int ret; | |
2549 | ||
2550 | vgic_node = of_find_matching_node_and_match(NULL, | |
2551 | vgic_ids, &matched_id); | |
2552 | if (!vgic_node) { | |
2553 | kvm_err("error: no compatible GIC node found\n"); | |
2554 | return -ENODEV; | |
2555 | } | |
2556 | ||
2557 | vgic_probe = matched_id->data; | |
2558 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2559 | if (ret) | |
2560 | return ret; | |
2561 | ||
2562 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2563 | "vgic", kvm_get_running_vcpus()); | |
2564 | if (ret) { | |
2565 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2566 | return ret; | |
2567 | } | |
2568 | ||
2569 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2570 | if (ret) { | |
2571 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2572 | goto out_free_irq; | |
2573 | } | |
2574 | ||
2575 | /* Callback into for arch code for setup */ | |
2576 | vgic_arch_setup(vgic); | |
2577 | ||
2578 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
2579 | ||
2580 | return kvm_register_device_ops(&kvm_arm_vgic_v2_ops, | |
2581 | KVM_DEV_TYPE_ARM_VGIC_V2); | |
2582 | ||
2583 | out_free_irq: | |
2584 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2585 | return ret; | |
2586 | } |