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KVM: ARM: vgic: abstract MISR decoding
[deliverable/linux.git] / virt / kvm / arm / vgic.c
CommitLineData
1a89dd91
MZ		 1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
01ac5e34 19#include <linux/cpu.h>
1a89dd91
MZ		 20#include <linux/kvm.h>
21#include <linux/kvm_host.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
01ac5e34
MZ		 24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
2a2f3e26 27#include <linux/uaccess.h>
01ac5e34
MZ		 28
29#include <linux/irqchip/arm-gic.h>
30
1a89dd91 31#include <asm/kvm_emulate.h>
01ac5e34
MZ		 32#include <asm/kvm_arm.h>
33#include <asm/kvm_mmu.h>
1a89dd91 34
b47ef92a
MZ		 35/*
36 * How the whole thing works (courtesy of Christoffer Dall):
37 *
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
45 * recalculated
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_state & dist->irq_enable
49 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
57 *
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
61 *
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_active is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_active. This allow the
69 * interrupt line to be sampled again.
70 */
71
330690cd
CD		 72#define VGIC_ADDR_UNDEF (-1)
73#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
74
fa20f5ae
CD		 75#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76#define IMPLEMENTER_ARM 0x43b
77#define GICC_ARCH_VERSION_V2 0x2
78
01ac5e34
MZ		 79/* Physical address of vgic virtual cpu interface */
80static phys_addr_t vgic_vcpu_base;
81
82/* Virtual control interface base address */
83static void __iomem *vgic_vctrl_base;
84
85static struct device_node *vgic_node;
86
1a89dd91
MZ		 87#define ACCESS_READ_VALUE (1 << 0)
88#define ACCESS_READ_RAZ (0 << 0)
89#define ACCESS_READ_MASK(x) ((x) & (1 << 0))
90#define ACCESS_WRITE_IGNORED (0 << 1)
91#define ACCESS_WRITE_SETBIT (1 << 1)
92#define ACCESS_WRITE_CLEARBIT (2 << 1)
93#define ACCESS_WRITE_VALUE (3 << 1)
94#define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
95
a1fcb44e 96static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
8d5c6b06 97static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
b47ef92a 98static void vgic_update_state(struct kvm *kvm);
5863c2ce 99static void vgic_kick_vcpus(struct kvm *kvm);
b47ef92a 100static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
8d5c6b06
MZ		 101static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
102static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
01ac5e34
MZ		 103static u32 vgic_nr_lr;
104
105static unsigned int vgic_maint_irq;
b47ef92a
MZ		 106
107static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
108 int cpuid, u32 offset)
109{
110 offset >>= 2;
111 if (!offset)
112 return x->percpu[cpuid].reg;
113 else
114 return x->shared.reg + offset - 1;
115}
116
117static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
118 int cpuid, int irq)
119{
120 if (irq < VGIC_NR_PRIVATE_IRQS)
121 return test_bit(irq, x->percpu[cpuid].reg_ul);
122
123 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
124}
125
126static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
127 int irq, int val)
128{
129 unsigned long *reg;
130
131 if (irq < VGIC_NR_PRIVATE_IRQS) {
132 reg = x->percpu[cpuid].reg_ul;
133 } else {
134 reg = x->shared.reg_ul;
135 irq -= VGIC_NR_PRIVATE_IRQS;
136 }
137
138 if (val)
139 set_bit(irq, reg);
140 else
141 clear_bit(irq, reg);
142}
143
144static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
145{
146 if (unlikely(cpuid >= VGIC_MAX_CPUS))
147 return NULL;
148 return x->percpu[cpuid].reg_ul;
149}
150
151static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
152{
153 return x->shared.reg_ul;
154}
155
156static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
157{
158 offset >>= 2;
159 BUG_ON(offset > (VGIC_NR_IRQS / 4));
8d98915b 160 if (offset < 8)
b47ef92a
MZ		 161 return x->percpu[cpuid] + offset;
162 else
163 return x->shared + offset - 8;
164}
165
166#define VGIC_CFG_LEVEL 0
167#define VGIC_CFG_EDGE 1
168
169static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
170{
171 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
172 int irq_val;
173
174 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
175 return irq_val == VGIC_CFG_EDGE;
176}
177
178static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
179{
180 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
181
182 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
183}
184
9d949dce
MZ		 185static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
186{
187 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
188
189 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
190}
191
192static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
193{
194 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
195
196 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
197}
198
199static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
200{
201 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
202
203 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
204}
205
206static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
207{
208 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
209
210 return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
211}
212
b47ef92a
MZ		 213static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
214{
215 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
216
217 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
218}
219
220static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
221{
222 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
223
224 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
225}
226
227static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
228{
229 if (irq < VGIC_NR_PRIVATE_IRQS)
230 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
231 else
232 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
233 vcpu->arch.vgic_cpu.pending_shared);
234}
235
236static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
237{
238 if (irq < VGIC_NR_PRIVATE_IRQS)
239 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
240 else
241 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
242 vcpu->arch.vgic_cpu.pending_shared);
243}
244
1a89dd91
MZ		 245static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
246{
247 return *((u32 *)mmio->data) & mask;
248}
249
250static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
251{
252 *((u32 *)mmio->data) = value & mask;
253}
254
255/**
256 * vgic_reg_access - access vgic register
257 * @mmio: pointer to the data describing the mmio access
258 * @reg: pointer to the virtual backing of vgic distributor data
259 * @offset: least significant 2 bits used for word offset
260 * @mode: ACCESS_ mode (see defines above)
261 *
262 * Helper to make vgic register access easier using one of the access
263 * modes defined for vgic register access
264 * (read,raz,write-ignored,setbit,clearbit,write)
265 */
266static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
267 phys_addr_t offset, int mode)
268{
269 int word_offset = (offset & 3) * 8;
270 u32 mask = (1UL << (mmio->len * 8)) - 1;
271 u32 regval;
272
273 /*
274 * Any alignment fault should have been delivered to the guest
275 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
276 */
277
278 if (reg) {
279 regval = *reg;
280 } else {
281 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
282 regval = 0;
283 }
284
285 if (mmio->is_write) {
286 u32 data = mmio_data_read(mmio, mask) << word_offset;
287 switch (ACCESS_WRITE_MASK(mode)) {
288 case ACCESS_WRITE_IGNORED:
289 return;
290
291 case ACCESS_WRITE_SETBIT:
292 regval |= data;
293 break;
294
295 case ACCESS_WRITE_CLEARBIT:
296 regval &= ~data;
297 break;
298
299 case ACCESS_WRITE_VALUE:
300 regval = (regval & ~(mask << word_offset)) | data;
301 break;
302 }
303 *reg = regval;
304 } else {
305 switch (ACCESS_READ_MASK(mode)) {
306 case ACCESS_READ_RAZ:
307 regval = 0;
308 /* fall through */
309
310 case ACCESS_READ_VALUE:
311 mmio_data_write(mmio, mask, regval >> word_offset);
312 }
313 }
314}
315
b47ef92a
MZ		 316static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
317 struct kvm_exit_mmio *mmio, phys_addr_t offset)
318{
319 u32 reg;
320 u32 word_offset = offset & 3;
321
322 switch (offset & ~3) {
fa20f5ae 323 case 0: /* GICD_CTLR */
b47ef92a
MZ		 324 reg = vcpu->kvm->arch.vgic.enabled;
325 vgic_reg_access(mmio, &reg, word_offset,
326 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
327 if (mmio->is_write) {
328 vcpu->kvm->arch.vgic.enabled = reg & 1;
329 vgic_update_state(vcpu->kvm);
330 return true;
331 }
332 break;
333
fa20f5ae 334 case 4: /* GICD_TYPER */
b47ef92a
MZ		 335 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
336 reg |= (VGIC_NR_IRQS >> 5) - 1;
337 vgic_reg_access(mmio, &reg, word_offset,
338 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
339 break;
340
fa20f5ae
CD		 341 case 8: /* GICD_IIDR */
342 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
b47ef92a
MZ		 343 vgic_reg_access(mmio, &reg, word_offset,
344 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
345 break;
346 }
347
348 return false;
349}
350
351static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
352 struct kvm_exit_mmio *mmio, phys_addr_t offset)
353{
354 vgic_reg_access(mmio, NULL, offset,
355 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
356 return false;
357}
358
359static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
360 struct kvm_exit_mmio *mmio,
361 phys_addr_t offset)
362{
363 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
364 vcpu->vcpu_id, offset);
365 vgic_reg_access(mmio, reg, offset,
366 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
367 if (mmio->is_write) {
368 vgic_update_state(vcpu->kvm);
369 return true;
370 }
371
372 return false;
373}
374
375static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
376 struct kvm_exit_mmio *mmio,
377 phys_addr_t offset)
378{
379 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
380 vcpu->vcpu_id, offset);
381 vgic_reg_access(mmio, reg, offset,
382 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
383 if (mmio->is_write) {
384 if (offset < 4) /* Force SGI enabled */
385 *reg |= 0xffff;
a1fcb44e 386 vgic_retire_disabled_irqs(vcpu);
b47ef92a
MZ		 387 vgic_update_state(vcpu->kvm);
388 return true;
389 }
390
391 return false;
392}
393
394static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
395 struct kvm_exit_mmio *mmio,
396 phys_addr_t offset)
397{
398 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
399 vcpu->vcpu_id, offset);
400 vgic_reg_access(mmio, reg, offset,
401 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
402 if (mmio->is_write) {
403 vgic_update_state(vcpu->kvm);
404 return true;
405 }
406
407 return false;
408}
409
410static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
411 struct kvm_exit_mmio *mmio,
412 phys_addr_t offset)
413{
414 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
415 vcpu->vcpu_id, offset);
416 vgic_reg_access(mmio, reg, offset,
417 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
418 if (mmio->is_write) {
419 vgic_update_state(vcpu->kvm);
420 return true;
421 }
422
423 return false;
424}
425
426static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
427 struct kvm_exit_mmio *mmio,
428 phys_addr_t offset)
429{
430 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
431 vcpu->vcpu_id, offset);
432 vgic_reg_access(mmio, reg, offset,
433 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
434 return false;
435}
436
437#define GICD_ITARGETSR_SIZE 32
438#define GICD_CPUTARGETS_BITS 8
439#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
440static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
441{
442 struct vgic_dist *dist = &kvm->arch.vgic;
986af8e0 443 int i;
b47ef92a
MZ		 444 u32 val = 0;
445
446 irq -= VGIC_NR_PRIVATE_IRQS;
447
986af8e0
MZ		 448 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
449 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
b47ef92a
MZ		 450
451 return val;
452}
453
454static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
455{
456 struct vgic_dist *dist = &kvm->arch.vgic;
457 struct kvm_vcpu *vcpu;
458 int i, c;
459 unsigned long *bmap;
460 u32 target;
461
462 irq -= VGIC_NR_PRIVATE_IRQS;
463
464 /*
465 * Pick the LSB in each byte. This ensures we target exactly
466 * one vcpu per IRQ. If the byte is null, assume we target
467 * CPU0.
468 */
469 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
470 int shift = i * GICD_CPUTARGETS_BITS;
471 target = ffs((val >> shift) & 0xffU);
472 target = target ? (target - 1) : 0;
473 dist->irq_spi_cpu[irq + i] = target;
474 kvm_for_each_vcpu(c, vcpu, kvm) {
475 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
476 if (c == target)
477 set_bit(irq + i, bmap);
478 else
479 clear_bit(irq + i, bmap);
480 }
481 }
482}
483
484static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
485 struct kvm_exit_mmio *mmio,
486 phys_addr_t offset)
487{
488 u32 reg;
489
490 /* We treat the banked interrupts targets as read-only */
491 if (offset < 32) {
492 u32 roreg = 1 << vcpu->vcpu_id;
493 roreg |= roreg << 8;
494 roreg |= roreg << 16;
495
496 vgic_reg_access(mmio, &roreg, offset,
497 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
498 return false;
499 }
500
501 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
502 vgic_reg_access(mmio, &reg, offset,
503 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
504 if (mmio->is_write) {
505 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
506 vgic_update_state(vcpu->kvm);
507 return true;
508 }
509
510 return false;
511}
512
513static u32 vgic_cfg_expand(u16 val)
514{
515 u32 res = 0;
516 int i;
517
518 /*
519 * Turn a 16bit value like abcd...mnop into a 32bit word
520 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
521 */
522 for (i = 0; i < 16; i++)
523 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
524
525 return res;
526}
527
528static u16 vgic_cfg_compress(u32 val)
529{
530 u16 res = 0;
531 int i;
532
533 /*
534 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
535 * abcd...mnop which is what we really care about.
536 */
537 for (i = 0; i < 16; i++)
538 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
539
540 return res;
541}
542
543/*
544 * The distributor uses 2 bits per IRQ for the CFG register, but the
545 * LSB is always 0. As such, we only keep the upper bit, and use the
546 * two above functions to compress/expand the bits
547 */
548static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
549 struct kvm_exit_mmio *mmio, phys_addr_t offset)
550{
551 u32 val;
6545eae3
MZ		 552 u32 *reg;
553
6545eae3 554 reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
f2ae85b2 555 vcpu->vcpu_id, offset >> 1);
6545eae3 556
f2ae85b2 557 if (offset & 4)
b47ef92a
MZ		 558 val = *reg >> 16;
559 else
560 val = *reg & 0xffff;
561
562 val = vgic_cfg_expand(val);
563 vgic_reg_access(mmio, &val, offset,
564 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
565 if (mmio->is_write) {
f2ae85b2 566 if (offset < 8) {
b47ef92a
MZ		 567 *reg = ~0U; /* Force PPIs/SGIs to 1 */
568 return false;
569 }
570
571 val = vgic_cfg_compress(val);
f2ae85b2 572 if (offset & 4) {
b47ef92a
MZ		 573 *reg &= 0xffff;
574 *reg |= val << 16;
575 } else {
576 *reg &= 0xffff << 16;
577 *reg |= val;
578 }
579 }
580
581 return false;
582}
583
584static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
585 struct kvm_exit_mmio *mmio, phys_addr_t offset)
586{
587 u32 reg;
588 vgic_reg_access(mmio, &reg, offset,
589 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
590 if (mmio->is_write) {
591 vgic_dispatch_sgi(vcpu, reg);
592 vgic_update_state(vcpu->kvm);
593 return true;
594 }
595
596 return false;
597}
598
cbd333a4
CD		 599/**
600 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
601 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
602 *
603 * Move any pending IRQs that have already been assigned to LRs back to the
604 * emulated distributor state so that the complete emulated state can be read
605 * from the main emulation structures without investigating the LRs.
606 *
607 * Note that IRQs in the active state in the LRs get their pending state moved
608 * to the distributor but the active state stays in the LRs, because we don't
609 * track the active state on the distributor side.
610 */
611static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
612{
613 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
614 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
615 int vcpu_id = vcpu->vcpu_id;
8d5c6b06 616 int i;
cbd333a4
CD		 617
618 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
8d5c6b06 619 struct vgic_lr lr = vgic_get_lr(vcpu, i);
cbd333a4
CD		 620
621 /*
622 * There are three options for the state bits:
623 *
624 * 01: pending
625 * 10: active
626 * 11: pending and active
627 *
628 * If the LR holds only an active interrupt (not pending) then
629 * just leave it alone.
630 */
8d5c6b06 631 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
cbd333a4
CD		 632 continue;
633
634 /*
635 * Reestablish the pending state on the distributor and the
636 * CPU interface. It may have already been pending, but that
637 * is fine, then we are only setting a few bits that were
638 * already set.
639 */
8d5c6b06
MZ		 640 vgic_dist_irq_set(vcpu, lr.irq);
641 if (lr.irq < VGIC_NR_SGIS)
642 dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source;
643 lr.state &= ~LR_STATE_PENDING;
644 vgic_set_lr(vcpu, i, lr);
cbd333a4
CD		 645
646 /*
647 * If there's no state left on the LR (it could still be
648 * active), then the LR does not hold any useful info and can
649 * be marked as free for other use.
650 */
8d5c6b06
MZ		 651 if (!(lr.state & LR_STATE_MASK))
652 vgic_retire_lr(i, lr.irq, vcpu);
cbd333a4
CD		 653
654 /* Finally update the VGIC state. */
655 vgic_update_state(vcpu->kvm);
656 }
657}
658
90a5355e
CD		 659/* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
660static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
661 struct kvm_exit_mmio *mmio,
662 phys_addr_t offset)
c07a0191 663{
90a5355e
CD		 664 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
665 int sgi;
666 int min_sgi = (offset & ~0x3) * 4;
667 int max_sgi = min_sgi + 3;
668 int vcpu_id = vcpu->vcpu_id;
669 u32 reg = 0;
670
671 /* Copy source SGIs from distributor side */
672 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
673 int shift = 8 * (sgi - min_sgi);
674 reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift;
675 }
676
677 mmio_data_write(mmio, ~0, reg);
c07a0191
CD		 678 return false;
679}
680
90a5355e
CD		 681static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
682 struct kvm_exit_mmio *mmio,
683 phys_addr_t offset, bool set)
684{
685 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
686 int sgi;
687 int min_sgi = (offset & ~0x3) * 4;
688 int max_sgi = min_sgi + 3;
689 int vcpu_id = vcpu->vcpu_id;
690 u32 reg;
691 bool updated = false;
692
693 reg = mmio_data_read(mmio, ~0);
694
695 /* Clear pending SGIs on the distributor */
696 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
697 u8 mask = reg >> (8 * (sgi - min_sgi));
698 if (set) {
699 if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask)
700 updated = true;
701 dist->irq_sgi_sources[vcpu_id][sgi] |= mask;
702 } else {
703 if (dist->irq_sgi_sources[vcpu_id][sgi] & mask)
704 updated = true;
705 dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask;
706 }
707 }
708
709 if (updated)
710 vgic_update_state(vcpu->kvm);
711
712 return updated;
713}
714
c07a0191
CD		 715static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
716 struct kvm_exit_mmio *mmio,
717 phys_addr_t offset)
718{
90a5355e
CD		 719 if (!mmio->is_write)
720 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
721 else
722 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
723}
724
725static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
726 struct kvm_exit_mmio *mmio,
727 phys_addr_t offset)
728{
729 if (!mmio->is_write)
730 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
731 else
732 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
c07a0191
CD		 733}
734
1a89dd91
MZ		 735/*
736 * I would have liked to use the kvm_bus_io_*() API instead, but it
737 * cannot cope with banked registers (only the VM pointer is passed
738 * around, and we need the vcpu). One of these days, someone please
739 * fix it!
740 */
741struct mmio_range {
742 phys_addr_t base;
743 unsigned long len;
744 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
745 phys_addr_t offset);
746};
747
1006e8cb 748static const struct mmio_range vgic_dist_ranges[] = {
b47ef92a
MZ		 749 {
750 .base = GIC_DIST_CTRL,
751 .len = 12,
752 .handle_mmio = handle_mmio_misc,
753 },
754 {
755 .base = GIC_DIST_IGROUP,
756 .len = VGIC_NR_IRQS / 8,
757 .handle_mmio = handle_mmio_raz_wi,
758 },
759 {
760 .base = GIC_DIST_ENABLE_SET,
761 .len = VGIC_NR_IRQS / 8,
762 .handle_mmio = handle_mmio_set_enable_reg,
763 },
764 {
765 .base = GIC_DIST_ENABLE_CLEAR,
766 .len = VGIC_NR_IRQS / 8,
767 .handle_mmio = handle_mmio_clear_enable_reg,
768 },
769 {
770 .base = GIC_DIST_PENDING_SET,
771 .len = VGIC_NR_IRQS / 8,
772 .handle_mmio = handle_mmio_set_pending_reg,
773 },
774 {
775 .base = GIC_DIST_PENDING_CLEAR,
776 .len = VGIC_NR_IRQS / 8,
777 .handle_mmio = handle_mmio_clear_pending_reg,
778 },
779 {
780 .base = GIC_DIST_ACTIVE_SET,
781 .len = VGIC_NR_IRQS / 8,
782 .handle_mmio = handle_mmio_raz_wi,
783 },
784 {
785 .base = GIC_DIST_ACTIVE_CLEAR,
786 .len = VGIC_NR_IRQS / 8,
787 .handle_mmio = handle_mmio_raz_wi,
788 },
789 {
790 .base = GIC_DIST_PRI,
791 .len = VGIC_NR_IRQS,
792 .handle_mmio = handle_mmio_priority_reg,
793 },
794 {
795 .base = GIC_DIST_TARGET,
796 .len = VGIC_NR_IRQS,
797 .handle_mmio = handle_mmio_target_reg,
798 },
799 {
800 .base = GIC_DIST_CONFIG,
801 .len = VGIC_NR_IRQS / 4,
802 .handle_mmio = handle_mmio_cfg_reg,
803 },
804 {
805 .base = GIC_DIST_SOFTINT,
806 .len = 4,
807 .handle_mmio = handle_mmio_sgi_reg,
808 },
c07a0191
CD		 809 {
810 .base = GIC_DIST_SGI_PENDING_CLEAR,
811 .len = VGIC_NR_SGIS,
812 .handle_mmio = handle_mmio_sgi_clear,
813 },
814 {
815 .base = GIC_DIST_SGI_PENDING_SET,
816 .len = VGIC_NR_SGIS,
817 .handle_mmio = handle_mmio_sgi_set,
818 },
1a89dd91
MZ		 819 {}
820};
821
822static const
823struct mmio_range *find_matching_range(const struct mmio_range *ranges,
824 struct kvm_exit_mmio *mmio,
1006e8cb 825 phys_addr_t offset)
1a89dd91
MZ		 826{
827 const struct mmio_range *r = ranges;
1a89dd91
MZ		 828
829 while (r->len) {
1006e8cb
CD		 830 if (offset >= r->base &&
831 (offset + mmio->len) <= (r->base + r->len))
1a89dd91
MZ		 832 return r;
833 r++;
834 }
835
836 return NULL;
837}
838
839/**
840 * vgic_handle_mmio - handle an in-kernel MMIO access
841 * @vcpu: pointer to the vcpu performing the access
842 * @run: pointer to the kvm_run structure
843 * @mmio: pointer to the data describing the access
844 *
845 * returns true if the MMIO access has been performed in kernel space,
846 * and false if it needs to be emulated in user space.
847 */
848bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
849 struct kvm_exit_mmio *mmio)
850{
b47ef92a
MZ		 851 const struct mmio_range *range;
852 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
853 unsigned long base = dist->vgic_dist_base;
854 bool updated_state;
855 unsigned long offset;
856
857 if (!irqchip_in_kernel(vcpu->kvm) ||
858 mmio->phys_addr < base ||
859 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
860 return false;
861
862 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
863 if (mmio->len > 4) {
864 kvm_inject_dabt(vcpu, mmio->phys_addr);
865 return true;
866 }
867
1006e8cb
CD		 868 offset = mmio->phys_addr - base;
869 range = find_matching_range(vgic_dist_ranges, mmio, offset);
b47ef92a
MZ		 870 if (unlikely(!range || !range->handle_mmio)) {
871 pr_warn("Unhandled access %d %08llx %d\n",
872 mmio->is_write, mmio->phys_addr, mmio->len);
873 return false;
874 }
875
876 spin_lock(&vcpu->kvm->arch.vgic.lock);
877 offset = mmio->phys_addr - range->base - base;
878 updated_state = range->handle_mmio(vcpu, mmio, offset);
879 spin_unlock(&vcpu->kvm->arch.vgic.lock);
880 kvm_prepare_mmio(run, mmio);
881 kvm_handle_mmio_return(vcpu, run);
882
5863c2ce
MZ		 883 if (updated_state)
884 vgic_kick_vcpus(vcpu->kvm);
885
b47ef92a
MZ		 886 return true;
887}
888
889static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
890{
891 struct kvm *kvm = vcpu->kvm;
892 struct vgic_dist *dist = &kvm->arch.vgic;
893 int nrcpus = atomic_read(&kvm->online_vcpus);
894 u8 target_cpus;
895 int sgi, mode, c, vcpu_id;
896
897 vcpu_id = vcpu->vcpu_id;
898
899 sgi = reg & 0xf;
900 target_cpus = (reg >> 16) & 0xff;
901 mode = (reg >> 24) & 3;
902
903 switch (mode) {
904 case 0:
905 if (!target_cpus)
906 return;
91021a6c 907 break;
b47ef92a
MZ		 908
909 case 1:
910 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
911 break;
912
913 case 2:
914 target_cpus = 1 << vcpu_id;
915 break;
916 }
917
918 kvm_for_each_vcpu(c, vcpu, kvm) {
919 if (target_cpus & 1) {
920 /* Flag the SGI as pending */
921 vgic_dist_irq_set(vcpu, sgi);
922 dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
923 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
924 }
925
926 target_cpus >>= 1;
927 }
928}
929
930static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
931{
9d949dce
MZ		 932 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
933 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
934 unsigned long pending_private, pending_shared;
935 int vcpu_id;
936
937 vcpu_id = vcpu->vcpu_id;
938 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
939 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
940
941 pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
942 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
943 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
944
945 pending = vgic_bitmap_get_shared_map(&dist->irq_state);
946 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
947 bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
948 bitmap_and(pend_shared, pend_shared,
949 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
950 VGIC_NR_SHARED_IRQS);
951
952 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
953 pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
954 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
955 pending_shared < VGIC_NR_SHARED_IRQS);
b47ef92a
MZ		 956}
957
958/*
959 * Update the interrupt state and determine which CPUs have pending
960 * interrupts. Must be called with distributor lock held.
961 */
962static void vgic_update_state(struct kvm *kvm)
963{
964 struct vgic_dist *dist = &kvm->arch.vgic;
965 struct kvm_vcpu *vcpu;
966 int c;
967
968 if (!dist->enabled) {
969 set_bit(0, &dist->irq_pending_on_cpu);
970 return;
971 }
972
973 kvm_for_each_vcpu(c, vcpu, kvm) {
974 if (compute_pending_for_cpu(vcpu)) {
975 pr_debug("CPU%d has pending interrupts\n", c);
976 set_bit(c, &dist->irq_pending_on_cpu);
977 }
978 }
1a89dd91 979}
330690cd 980
8d5c6b06
MZ		 981static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
982{
983 struct vgic_lr lr_desc;
984 u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
985
986 lr_desc.irq = val & GICH_LR_VIRTUALID;
987 if (lr_desc.irq <= 15)
988 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
989 else
990 lr_desc.source = 0;
991 lr_desc.state = 0;
992
993 if (val & GICH_LR_PENDING_BIT)
994 lr_desc.state |= LR_STATE_PENDING;
995 if (val & GICH_LR_ACTIVE_BIT)
996 lr_desc.state |= LR_STATE_ACTIVE;
997 if (val & GICH_LR_EOI)
998 lr_desc.state |= LR_EOI_INT;
999
1000 return lr_desc;
1001}
1002
1003static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
1004 struct vgic_lr lr_desc)
1005{
1006 u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;
1007
1008 if (lr_desc.state & LR_STATE_PENDING)
1009 lr_val |= GICH_LR_PENDING_BIT;
1010 if (lr_desc.state & LR_STATE_ACTIVE)
1011 lr_val |= GICH_LR_ACTIVE_BIT;
1012 if (lr_desc.state & LR_EOI_INT)
1013 lr_val |= GICH_LR_EOI;
1014
1015 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
1016}
1017
69bb2c9f
MZ		 1018static void vgic_v2_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1019 struct vgic_lr lr_desc)
1020{
1021 if (!(lr_desc.state & LR_STATE_MASK))
1022 set_bit(lr, (unsigned long *)vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr);
1023}
1024
1025static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
1026{
1027 u64 val;
1028
1029#if BITS_PER_LONG == 64
1030 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[1];
1031 val <<= 32;
1032 val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[0];
1033#else
1034 val = *(u64 *)vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
1035#endif
1036 return val;
1037}
1038
8d6a0313
MZ		 1039static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
1040{
1041 u64 val;
1042
1043#if BITS_PER_LONG == 64
1044 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[1];
1045 val <<= 32;
1046 val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[0];
1047#else
1048 val = *(u64 *)vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
1049#endif
1050 return val;
1051}
1052
495dd859
MZ		 1053static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
1054{
1055 u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
1056 u32 ret = 0;
1057
1058 if (misr & GICH_MISR_EOI)
1059 ret |= INT_STATUS_EOI;
1060 if (misr & GICH_MISR_U)
1061 ret |= INT_STATUS_UNDERFLOW;
1062
1063 return ret;
1064}
1065
8d5c6b06
MZ		 1066static const struct vgic_ops vgic_ops = {
1067 .get_lr = vgic_v2_get_lr,
1068 .set_lr = vgic_v2_set_lr,
69bb2c9f
MZ		 1069 .sync_lr_elrsr = vgic_v2_sync_lr_elrsr,
1070 .get_elrsr = vgic_v2_get_elrsr,
8d6a0313 1071 .get_eisr = vgic_v2_get_eisr,
495dd859 1072 .get_interrupt_status = vgic_v2_get_interrupt_status,
8d5c6b06
MZ		 1073};
1074
1075static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1076{
1077 return vgic_ops.get_lr(vcpu, lr);
1078}
1079
1080static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1081 struct vgic_lr vlr)
1082{
1083 vgic_ops.set_lr(vcpu, lr, vlr);
1084}
1085
69bb2c9f
MZ		 1086static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1087 struct vgic_lr vlr)
1088{
1089 vgic_ops.sync_lr_elrsr(vcpu, lr, vlr);
1090}
1091
1092static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1093{
1094 return vgic_ops.get_elrsr(vcpu);
1095}
1096
8d6a0313
MZ		 1097static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1098{
1099 return vgic_ops.get_eisr(vcpu);
1100}
1101
495dd859
MZ		 1102static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1103{
1104 return vgic_ops.get_interrupt_status(vcpu);
1105}
1106
8d5c6b06
MZ		 1107static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1108{
1109 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1110 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1111
1112 vlr.state = 0;
1113 vgic_set_lr(vcpu, lr_nr, vlr);
1114 clear_bit(lr_nr, vgic_cpu->lr_used);
1115 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1116}
a1fcb44e
MZ		 1117
1118/*
1119 * An interrupt may have been disabled after being made pending on the
1120 * CPU interface (the classic case is a timer running while we're
1121 * rebooting the guest - the interrupt would kick as soon as the CPU
1122 * interface gets enabled, with deadly consequences).
1123 *
1124 * The solution is to examine already active LRs, and check the
1125 * interrupt is still enabled. If not, just retire it.
1126 */
1127static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1128{
1129 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1130 int lr;
1131
1132 for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
8d5c6b06 1133 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
a1fcb44e 1134
8d5c6b06
MZ		 1135 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1136 vgic_retire_lr(lr, vlr.irq, vcpu);
1137 if (vgic_irq_is_active(vcpu, vlr.irq))
1138 vgic_irq_clear_active(vcpu, vlr.irq);
a1fcb44e
MZ		 1139 }
1140 }
1141}
1142
9d949dce
MZ		 1143/*
1144 * Queue an interrupt to a CPU virtual interface. Return true on success,
1145 * or false if it wasn't possible to queue it.
1146 */
1147static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1148{
1149 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
8d5c6b06 1150 struct vgic_lr vlr;
9d949dce
MZ		 1151 int lr;
1152
1153 /* Sanitize the input... */
1154 BUG_ON(sgi_source_id & ~7);
1155 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1156 BUG_ON(irq >= VGIC_NR_IRQS);
1157
1158 kvm_debug("Queue IRQ%d\n", irq);
1159
1160 lr = vgic_cpu->vgic_irq_lr_map[irq];
1161
1162 /* Do we have an active interrupt for the same CPUID? */
8d5c6b06
MZ		 1163 if (lr != LR_EMPTY) {
1164 vlr = vgic_get_lr(vcpu, lr);
1165 if (vlr.source == sgi_source_id) {
1166 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1167 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1168 vlr.state |= LR_STATE_PENDING;
1169 vgic_set_lr(vcpu, lr, vlr);
1170 return true;
1171 }
9d949dce
MZ		 1172 }
1173
1174 /* Try to use another LR for this interrupt */
1175 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1176 vgic_cpu->nr_lr);
1177 if (lr >= vgic_cpu->nr_lr)
1178 return false;
1179
1180 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
9d949dce
MZ		 1181 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1182 set_bit(lr, vgic_cpu->lr_used);
1183
8d5c6b06
MZ		 1184 vlr.irq = irq;
1185 vlr.source = sgi_source_id;
1186 vlr.state = LR_STATE_PENDING;
9d949dce 1187 if (!vgic_irq_is_edge(vcpu, irq))
8d5c6b06
MZ		 1188 vlr.state |= LR_EOI_INT;
1189
1190 vgic_set_lr(vcpu, lr, vlr);
9d949dce
MZ		 1191
1192 return true;
1193}
1194
1195static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1196{
1197 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1198 unsigned long sources;
1199 int vcpu_id = vcpu->vcpu_id;
1200 int c;
1201
1202 sources = dist->irq_sgi_sources[vcpu_id][irq];
1203
1204 for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
1205 if (vgic_queue_irq(vcpu, c, irq))
1206 clear_bit(c, &sources);
1207 }
1208
1209 dist->irq_sgi_sources[vcpu_id][irq] = sources;
1210
1211 /*
1212 * If the sources bitmap has been cleared it means that we
1213 * could queue all the SGIs onto link registers (see the
1214 * clear_bit above), and therefore we are done with them in
1215 * our emulated gic and can get rid of them.
1216 */
1217 if (!sources) {
1218 vgic_dist_irq_clear(vcpu, irq);
1219 vgic_cpu_irq_clear(vcpu, irq);
1220 return true;
1221 }
1222
1223 return false;
1224}
1225
1226static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1227{
1228 if (vgic_irq_is_active(vcpu, irq))
1229 return true; /* level interrupt, already queued */
1230
1231 if (vgic_queue_irq(vcpu, 0, irq)) {
1232 if (vgic_irq_is_edge(vcpu, irq)) {
1233 vgic_dist_irq_clear(vcpu, irq);
1234 vgic_cpu_irq_clear(vcpu, irq);
1235 } else {
1236 vgic_irq_set_active(vcpu, irq);
1237 }
1238
1239 return true;
1240 }
1241
1242 return false;
1243}
1244
1245/*
1246 * Fill the list registers with pending interrupts before running the
1247 * guest.
1248 */
1249static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1250{
1251 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1252 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1253 int i, vcpu_id;
1254 int overflow = 0;
1255
1256 vcpu_id = vcpu->vcpu_id;
1257
1258 /*
1259 * We may not have any pending interrupt, or the interrupts
1260 * may have been serviced from another vcpu. In all cases,
1261 * move along.
1262 */
1263 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1264 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1265 goto epilog;
1266 }
1267
1268 /* SGIs */
1269 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1270 if (!vgic_queue_sgi(vcpu, i))
1271 overflow = 1;
1272 }
1273
1274 /* PPIs */
1275 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1276 if (!vgic_queue_hwirq(vcpu, i))
1277 overflow = 1;
1278 }
1279
1280 /* SPIs */
1281 for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
1282 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1283 overflow = 1;
1284 }
1285
1286epilog:
1287 if (overflow) {
eede821d 1288 vgic_cpu->vgic_v2.vgic_hcr |= GICH_HCR_UIE;
9d949dce 1289 } else {
eede821d 1290 vgic_cpu->vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
9d949dce
MZ		 1291 /*
1292 * We're about to run this VCPU, and we've consumed
1293 * everything the distributor had in store for
1294 * us. Claim we don't have anything pending. We'll
1295 * adjust that if needed while exiting.
1296 */
1297 clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
1298 }
1299}
1300
1301static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1302{
1303 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
495dd859 1304 u32 status = vgic_get_interrupt_status(vcpu);
9d949dce
MZ		 1305 bool level_pending = false;
1306
495dd859 1307 kvm_debug("STATUS = %08x\n", status);
9d949dce 1308
495dd859 1309 if (status & INT_STATUS_EOI) {
9d949dce
MZ		 1310 /*
1311 * Some level interrupts have been EOIed. Clear their
1312 * active bit.
1313 */
8d6a0313
MZ		 1314 u64 eisr = vgic_get_eisr(vcpu);
1315 unsigned long *eisr_ptr = (unsigned long *)&eisr;
8d5c6b06 1316 int lr;
9d949dce 1317
8d6a0313 1318 for_each_set_bit(lr, eisr_ptr, vgic_cpu->nr_lr) {
8d5c6b06 1319 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
9d949dce 1320
8d5c6b06
MZ		 1321 vgic_irq_clear_active(vcpu, vlr.irq);
1322 WARN_ON(vlr.state & LR_STATE_MASK);
1323 vlr.state = 0;
1324 vgic_set_lr(vcpu, lr, vlr);
9d949dce
MZ		 1325
1326 /* Any additional pending interrupt? */
8d5c6b06
MZ		 1327 if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) {
1328 vgic_cpu_irq_set(vcpu, vlr.irq);
9d949dce
MZ		 1329 level_pending = true;
1330 } else {
8d5c6b06 1331 vgic_cpu_irq_clear(vcpu, vlr.irq);
9d949dce 1332 }
75da01e1
MZ		 1333
1334 /*
1335 * Despite being EOIed, the LR may not have
1336 * been marked as empty.
1337 */
69bb2c9f 1338 vgic_sync_lr_elrsr(vcpu, lr, vlr);
9d949dce
MZ		 1339 }
1340 }
1341
495dd859 1342 if (status & INT_STATUS_UNDERFLOW)
eede821d 1343 vgic_cpu->vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
9d949dce
MZ		 1344
1345 return level_pending;
1346}
1347
1348/*
33c83cb3
MZ		 1349 * Sync back the VGIC state after a guest run. The distributor lock is
1350 * needed so we don't get preempted in the middle of the state processing.
9d949dce
MZ		 1351 */
1352static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1353{
1354 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1355 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
69bb2c9f
MZ		 1356 u64 elrsr;
1357 unsigned long *elrsr_ptr;
9d949dce
MZ		 1358 int lr, pending;
1359 bool level_pending;
1360
1361 level_pending = vgic_process_maintenance(vcpu);
69bb2c9f
MZ		 1362 elrsr = vgic_get_elrsr(vcpu);
1363 elrsr_ptr = (unsigned long *)&elrsr;
9d949dce
MZ		 1364
1365 /* Clear mappings for empty LRs */
69bb2c9f 1366 for_each_set_bit(lr, elrsr_ptr, vgic_cpu->nr_lr) {
8d5c6b06 1367 struct vgic_lr vlr;
9d949dce
MZ		 1368
1369 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1370 continue;
1371
8d5c6b06 1372 vlr = vgic_get_lr(vcpu, lr);
9d949dce 1373
8d5c6b06
MZ		 1374 BUG_ON(vlr.irq >= VGIC_NR_IRQS);
1375 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
9d949dce
MZ		 1376 }
1377
1378 /* Check if we still have something up our sleeve... */
69bb2c9f 1379 pending = find_first_zero_bit(elrsr_ptr, vgic_cpu->nr_lr);
9d949dce
MZ		 1380 if (level_pending || pending < vgic_cpu->nr_lr)
1381 set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1382}
1383
1384void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1385{
1386 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1387
1388 if (!irqchip_in_kernel(vcpu->kvm))
1389 return;
1390
1391 spin_lock(&dist->lock);
1392 __kvm_vgic_flush_hwstate(vcpu);
1393 spin_unlock(&dist->lock);
1394}
1395
1396void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1397{
33c83cb3
MZ		 1398 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1399
9d949dce
MZ		 1400 if (!irqchip_in_kernel(vcpu->kvm))
1401 return;
1402
33c83cb3 1403 spin_lock(&dist->lock);
9d949dce 1404 __kvm_vgic_sync_hwstate(vcpu);
33c83cb3 1405 spin_unlock(&dist->lock);
9d949dce
MZ		 1406}
1407
1408int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1409{
1410 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1411
1412 if (!irqchip_in_kernel(vcpu->kvm))
1413 return 0;
1414
1415 return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1416}
1417
5863c2ce
MZ		 1418static void vgic_kick_vcpus(struct kvm *kvm)
1419{
1420 struct kvm_vcpu *vcpu;
1421 int c;
1422
1423 /*
1424 * We've injected an interrupt, time to find out who deserves
1425 * a good kick...
1426 */
1427 kvm_for_each_vcpu(c, vcpu, kvm) {
1428 if (kvm_vgic_vcpu_pending_irq(vcpu))
1429 kvm_vcpu_kick(vcpu);
1430 }
1431}
1432
1433static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1434{
1435 int is_edge = vgic_irq_is_edge(vcpu, irq);
1436 int state = vgic_dist_irq_is_pending(vcpu, irq);
1437
1438 /*
1439 * Only inject an interrupt if:
1440 * - edge triggered and we have a rising edge
1441 * - level triggered and we change level
1442 */
1443 if (is_edge)
1444 return level > state;
1445 else
1446 return level != state;
1447}
1448
1449static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
1450 unsigned int irq_num, bool level)
1451{
1452 struct vgic_dist *dist = &kvm->arch.vgic;
1453 struct kvm_vcpu *vcpu;
1454 int is_edge, is_level;
1455 int enabled;
1456 bool ret = true;
1457
1458 spin_lock(&dist->lock);
1459
1460 vcpu = kvm_get_vcpu(kvm, cpuid);
1461 is_edge = vgic_irq_is_edge(vcpu, irq_num);
1462 is_level = !is_edge;
1463
1464 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1465 ret = false;
1466 goto out;
1467 }
1468
1469 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1470 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1471 vcpu = kvm_get_vcpu(kvm, cpuid);
1472 }
1473
1474 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1475
1476 if (level)
1477 vgic_dist_irq_set(vcpu, irq_num);
1478 else
1479 vgic_dist_irq_clear(vcpu, irq_num);
1480
1481 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1482
1483 if (!enabled) {
1484 ret = false;
1485 goto out;
1486 }
1487
1488 if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
1489 /*
1490 * Level interrupt in progress, will be picked up
1491 * when EOId.
1492 */
1493 ret = false;
1494 goto out;
1495 }
1496
1497 if (level) {
1498 vgic_cpu_irq_set(vcpu, irq_num);
1499 set_bit(cpuid, &dist->irq_pending_on_cpu);
1500 }
1501
1502out:
1503 spin_unlock(&dist->lock);
1504
1505 return ret;
1506}
1507
1508/**
1509 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1510 * @kvm: The VM structure pointer
1511 * @cpuid: The CPU for PPIs
1512 * @irq_num: The IRQ number that is assigned to the device
1513 * @level: Edge-triggered: true: to trigger the interrupt
1514 * false: to ignore the call
1515 * Level-sensitive true: activates an interrupt
1516 * false: deactivates an interrupt
1517 *
1518 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1519 * level-sensitive interrupts. You can think of the level parameter as 1
1520 * being HIGH and 0 being LOW and all devices being active-HIGH.
1521 */
1522int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1523 bool level)
1524{
1525 if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
1526 vgic_kick_vcpus(kvm);
1527
1528 return 0;
1529}
1530
01ac5e34
MZ		 1531static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1532{
1533 /*
1534 * We cannot rely on the vgic maintenance interrupt to be
1535 * delivered synchronously. This means we can only use it to
1536 * exit the VM, and we perform the handling of EOIed
1537 * interrupts on the exit path (see vgic_process_maintenance).
1538 */
1539 return IRQ_HANDLED;
1540}
1541
e1ba0207
CD		 1542/**
1543 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1544 * @vcpu: pointer to the vcpu struct
1545 *
1546 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1547 * this vcpu and enable the VGIC for this VCPU
1548 */
01ac5e34
MZ		 1549int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1550{
1551 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1552 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1553 int i;
1554
01ac5e34
MZ		 1555 if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
1556 return -EBUSY;
1557
1558 for (i = 0; i < VGIC_NR_IRQS; i++) {
1559 if (i < VGIC_NR_PPIS)
1560 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1561 vcpu->vcpu_id, i, 1);
1562 if (i < VGIC_NR_PRIVATE_IRQS)
1563 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1564 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1565
1566 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1567 }
1568
1569 /*
1570 * By forcing VMCR to zero, the GIC will restore the binary
1571 * points to their reset values. Anything else resets to zero
1572 * anyway.
1573 */
eede821d 1574 vgic_cpu->vgic_v2.vgic_vmcr = 0;
01ac5e34
MZ		 1575
1576 vgic_cpu->nr_lr = vgic_nr_lr;
eede821d 1577 vgic_cpu->vgic_v2.vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
01ac5e34
MZ		 1578
1579 return 0;
1580}
1581
1582static void vgic_init_maintenance_interrupt(void *info)
1583{
1584 enable_percpu_irq(vgic_maint_irq, 0);
1585}
1586
1587static int vgic_cpu_notify(struct notifier_block *self,
1588 unsigned long action, void *cpu)
1589{
1590 switch (action) {
1591 case CPU_STARTING:
1592 case CPU_STARTING_FROZEN:
1593 vgic_init_maintenance_interrupt(NULL);
1594 break;
1595 case CPU_DYING:
1596 case CPU_DYING_FROZEN:
1597 disable_percpu_irq(vgic_maint_irq);
1598 break;
1599 }
1600
1601 return NOTIFY_OK;
1602}
1603
1604static struct notifier_block vgic_cpu_nb = {
1605 .notifier_call = vgic_cpu_notify,
1606};
1607
1608int kvm_vgic_hyp_init(void)
1609{
1610 int ret;
1611 struct resource vctrl_res;
1612 struct resource vcpu_res;
1613
1614 vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
1615 if (!vgic_node) {
1616 kvm_err("error: no compatible vgic node in DT\n");
1617 return -ENODEV;
1618 }
1619
1620 vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
1621 if (!vgic_maint_irq) {
1622 kvm_err("error getting vgic maintenance irq from DT\n");
1623 ret = -ENXIO;
1624 goto out;
1625 }
1626
1627 ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
1628 "vgic", kvm_get_running_vcpus());
1629 if (ret) {
1630 kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
1631 goto out;
1632 }
1633
553f809e 1634 ret = __register_cpu_notifier(&vgic_cpu_nb);
01ac5e34
MZ		 1635 if (ret) {
1636 kvm_err("Cannot register vgic CPU notifier\n");
1637 goto out_free_irq;
1638 }
1639
1640 ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
1641 if (ret) {
1642 kvm_err("Cannot obtain VCTRL resource\n");
1643 goto out_free_irq;
1644 }
1645
1646 vgic_vctrl_base = of_iomap(vgic_node, 2);
1647 if (!vgic_vctrl_base) {
1648 kvm_err("Cannot ioremap VCTRL\n");
1649 ret = -ENOMEM;
1650 goto out_free_irq;
1651 }
1652
1653 vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
1654 vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
1655
1656 ret = create_hyp_io_mappings(vgic_vctrl_base,
1657 vgic_vctrl_base + resource_size(&vctrl_res),
1658 vctrl_res.start);
1659 if (ret) {
1660 kvm_err("Cannot map VCTRL into hyp\n");
1661 goto out_unmap;
1662 }
1663
1664 kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
1665 vctrl_res.start, vgic_maint_irq);
1666 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
1667
1668 if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
1669 kvm_err("Cannot obtain VCPU resource\n");
1670 ret = -ENXIO;
1671 goto out_unmap;
1672 }
1673 vgic_vcpu_base = vcpu_res.start;
1674
1675 goto out;
1676
1677out_unmap:
1678 iounmap(vgic_vctrl_base);
1679out_free_irq:
1680 free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
1681out:
1682 of_node_put(vgic_node);
1683 return ret;
1684}
1685
e1ba0207
CD		 1686/**
1687 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1688 * @kvm: pointer to the kvm struct
1689 *
1690 * Map the virtual CPU interface into the VM before running any VCPUs. We
1691 * can't do this at creation time, because user space must first set the
1692 * virtual CPU interface address in the guest physical address space. Also
1693 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1694 */
01ac5e34
MZ		 1695int kvm_vgic_init(struct kvm *kvm)
1696{
1697 int ret = 0, i;
1698
e1ba0207
CD		 1699 if (!irqchip_in_kernel(kvm))
1700 return 0;
1701
01ac5e34
MZ		 1702 mutex_lock(&kvm->lock);
1703
1704 if (vgic_initialized(kvm))
1705 goto out;
1706
1707 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1708 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1709 kvm_err("Need to set vgic cpu and dist addresses first\n");
1710 ret = -ENXIO;
1711 goto out;
1712 }
1713
1714 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1715 vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
1716 if (ret) {
1717 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1718 goto out;
1719 }
1720
1721 for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1722 vgic_set_target_reg(kvm, 0, i);
1723
1724 kvm->arch.vgic.ready = true;
1725out:
1726 mutex_unlock(&kvm->lock);
1727 return ret;
1728}
1729
1730int kvm_vgic_create(struct kvm *kvm)
1731{
7330672b
CD		 1732 int i, vcpu_lock_idx = -1, ret = 0;
1733 struct kvm_vcpu *vcpu;
01ac5e34
MZ		 1734
1735 mutex_lock(&kvm->lock);
1736
7330672b 1737 if (kvm->arch.vgic.vctrl_base) {
01ac5e34
MZ		 1738 ret = -EEXIST;
1739 goto out;
1740 }
1741
7330672b
CD		 1742 /*
1743 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1744 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1745 * that no other VCPUs are run while we create the vgic.
1746 */
1747 kvm_for_each_vcpu(i, vcpu, kvm) {
1748 if (!mutex_trylock(&vcpu->mutex))
1749 goto out_unlock;
1750 vcpu_lock_idx = i;
1751 }
1752
1753 kvm_for_each_vcpu(i, vcpu, kvm) {
1754 if (vcpu->arch.has_run_once) {
1755 ret = -EBUSY;
1756 goto out_unlock;
1757 }
1758 }
1759
01ac5e34
MZ		 1760 spin_lock_init(&kvm->arch.vgic.lock);
1761 kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
1762 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1763 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1764
7330672b
CD		 1765out_unlock:
1766 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1767 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1768 mutex_unlock(&vcpu->mutex);
1769 }
1770
01ac5e34
MZ		 1771out:
1772 mutex_unlock(&kvm->lock);
1773 return ret;
1774}
1775
330690cd
CD		 1776static bool vgic_ioaddr_overlap(struct kvm *kvm)
1777{
1778 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1779 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1780
1781 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1782 return 0;
1783 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1784 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1785 return -EBUSY;
1786 return 0;
1787}
1788
1789static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1790 phys_addr_t addr, phys_addr_t size)
1791{
1792 int ret;
1793
ce01e4e8
CD		 1794 if (addr & ~KVM_PHYS_MASK)
1795 return -E2BIG;
1796
1797 if (addr & (SZ_4K - 1))
1798 return -EINVAL;
1799
330690cd
CD		 1800 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1801 return -EEXIST;
1802 if (addr + size < addr)
1803 return -EINVAL;
1804
30c21170 1805 *ioaddr = addr;
330690cd
CD		 1806 ret = vgic_ioaddr_overlap(kvm);
1807 if (ret)
30c21170
HW		 1808 *ioaddr = VGIC_ADDR_UNDEF;
1809
330690cd
CD		 1810 return ret;
1811}
1812
ce01e4e8
CD		 1813/**
1814 * kvm_vgic_addr - set or get vgic VM base addresses
1815 * @kvm: pointer to the vm struct
1816 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1817 * @addr: pointer to address value
1818 * @write: if true set the address in the VM address space, if false read the
1819 * address
1820 *
1821 * Set or get the vgic base addresses for the distributor and the virtual CPU
1822 * interface in the VM physical address space. These addresses are properties
1823 * of the emulated core/SoC and therefore user space initially knows this
1824 * information.
1825 */
1826int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
330690cd
CD		 1827{
1828 int r = 0;
1829 struct vgic_dist *vgic = &kvm->arch.vgic;
1830
330690cd
CD		 1831 mutex_lock(&kvm->lock);
1832 switch (type) {
1833 case KVM_VGIC_V2_ADDR_TYPE_DIST:
ce01e4e8
CD		 1834 if (write) {
1835 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1836 *addr, KVM_VGIC_V2_DIST_SIZE);
1837 } else {
1838 *addr = vgic->vgic_dist_base;
1839 }
330690cd
CD		 1840 break;
1841 case KVM_VGIC_V2_ADDR_TYPE_CPU:
ce01e4e8
CD		 1842 if (write) {
1843 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1844 *addr, KVM_VGIC_V2_CPU_SIZE);
1845 } else {
1846 *addr = vgic->vgic_cpu_base;
1847 }
330690cd
CD		 1848 break;
1849 default:
1850 r = -ENODEV;
1851 }
1852
1853 mutex_unlock(&kvm->lock);
1854 return r;
1855}
7330672b 1856
c07a0191
CD		 1857static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
1858 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1859{
fa20f5ae
CD		 1860 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1861 u32 reg, mask = 0, shift = 0;
1862 bool updated = false;
1863
1864 switch (offset & ~0x3) {
1865 case GIC_CPU_CTRL:
1866 mask = GICH_VMCR_CTRL_MASK;
1867 shift = GICH_VMCR_CTRL_SHIFT;
1868 break;
1869 case GIC_CPU_PRIMASK:
1870 mask = GICH_VMCR_PRIMASK_MASK;
1871 shift = GICH_VMCR_PRIMASK_SHIFT;
1872 break;
1873 case GIC_CPU_BINPOINT:
1874 mask = GICH_VMCR_BINPOINT_MASK;
1875 shift = GICH_VMCR_BINPOINT_SHIFT;
1876 break;
1877 case GIC_CPU_ALIAS_BINPOINT:
1878 mask = GICH_VMCR_ALIAS_BINPOINT_MASK;
1879 shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT;
1880 break;
1881 }
1882
1883 if (!mmio->is_write) {
eede821d 1884 reg = (vgic_cpu->vgic_v2.vgic_vmcr & mask) >> shift;
fa20f5ae
CD		 1885 mmio_data_write(mmio, ~0, reg);
1886 } else {
1887 reg = mmio_data_read(mmio, ~0);
1888 reg = (reg << shift) & mask;
eede821d 1889 if (reg != (vgic_cpu->vgic_v2.vgic_vmcr & mask))
fa20f5ae 1890 updated = true;
eede821d
MZ		 1891 vgic_cpu->vgic_v2.vgic_vmcr &= ~mask;
1892 vgic_cpu->vgic_v2.vgic_vmcr |= reg;
fa20f5ae
CD		 1893 }
1894 return updated;
1895}
1896
1897static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
1898 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1899{
1900 return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
c07a0191
CD		 1901}
1902
fa20f5ae
CD		 1903static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
1904 struct kvm_exit_mmio *mmio,
1905 phys_addr_t offset)
1906{
1907 u32 reg;
1908
1909 if (mmio->is_write)
1910 return false;
1911
1912 /* GICC_IIDR */
1913 reg = (PRODUCT_ID_KVM << 20) |
1914 (GICC_ARCH_VERSION_V2 << 16) |
1915 (IMPLEMENTER_ARM << 0);
1916 mmio_data_write(mmio, ~0, reg);
1917 return false;
1918}
1919
1920/*
1921 * CPU Interface Register accesses - these are not accessed by the VM, but by
1922 * user space for saving and restoring VGIC state.
1923 */
c07a0191
CD		 1924static const struct mmio_range vgic_cpu_ranges[] = {
1925 {
1926 .base = GIC_CPU_CTRL,
1927 .len = 12,
1928 .handle_mmio = handle_cpu_mmio_misc,
1929 },
1930 {
1931 .base = GIC_CPU_ALIAS_BINPOINT,
1932 .len = 4,
fa20f5ae 1933 .handle_mmio = handle_mmio_abpr,
c07a0191
CD		 1934 },
1935 {
1936 .base = GIC_CPU_ACTIVEPRIO,
1937 .len = 16,
fa20f5ae 1938 .handle_mmio = handle_mmio_raz_wi,
c07a0191
CD		 1939 },
1940 {
1941 .base = GIC_CPU_IDENT,
1942 .len = 4,
fa20f5ae 1943 .handle_mmio = handle_cpu_mmio_ident,
c07a0191
CD		 1944 },
1945};
1946
1947static int vgic_attr_regs_access(struct kvm_device *dev,
1948 struct kvm_device_attr *attr,
1949 u32 *reg, bool is_write)
1950{
1951 const struct mmio_range *r = NULL, *ranges;
1952 phys_addr_t offset;
1953 int ret, cpuid, c;
1954 struct kvm_vcpu *vcpu, *tmp_vcpu;
1955 struct vgic_dist *vgic;
1956 struct kvm_exit_mmio mmio;
1957
1958 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1959 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
1960 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
1961
1962 mutex_lock(&dev->kvm->lock);
1963
1964 if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
1965 ret = -EINVAL;
1966 goto out;
1967 }
1968
1969 vcpu = kvm_get_vcpu(dev->kvm, cpuid);
1970 vgic = &dev->kvm->arch.vgic;
1971
1972 mmio.len = 4;
1973 mmio.is_write = is_write;
1974 if (is_write)
1975 mmio_data_write(&mmio, ~0, *reg);
1976 switch (attr->group) {
1977 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1978 mmio.phys_addr = vgic->vgic_dist_base + offset;
1979 ranges = vgic_dist_ranges;
1980 break;
1981 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
1982 mmio.phys_addr = vgic->vgic_cpu_base + offset;
1983 ranges = vgic_cpu_ranges;
1984 break;
1985 default:
1986 BUG();
1987 }
1988 r = find_matching_range(ranges, &mmio, offset);
1989
1990 if (unlikely(!r || !r->handle_mmio)) {
1991 ret = -ENXIO;
1992 goto out;
1993 }
1994
1995
1996 spin_lock(&vgic->lock);
1997
1998 /*
1999 * Ensure that no other VCPU is running by checking the vcpu->cpu
2000 * field. If no other VPCUs are running we can safely access the VGIC
2001 * state, because even if another VPU is run after this point, that
2002 * VCPU will not touch the vgic state, because it will block on
2003 * getting the vgic->lock in kvm_vgic_sync_hwstate().
2004 */
2005 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
2006 if (unlikely(tmp_vcpu->cpu != -1)) {
2007 ret = -EBUSY;
2008 goto out_vgic_unlock;
2009 }
2010 }
2011
cbd333a4
CD		 2012 /*
2013 * Move all pending IRQs from the LRs on all VCPUs so the pending
2014 * state can be properly represented in the register state accessible
2015 * through this API.
2016 */
2017 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
2018 vgic_unqueue_irqs(tmp_vcpu);
2019
c07a0191
CD		 2020 offset -= r->base;
2021 r->handle_mmio(vcpu, &mmio, offset);
2022
2023 if (!is_write)
2024 *reg = mmio_data_read(&mmio, ~0);
2025
2026 ret = 0;
2027out_vgic_unlock:
2028 spin_unlock(&vgic->lock);
2029out:
2030 mutex_unlock(&dev->kvm->lock);
2031 return ret;
2032}
2033
7330672b
CD		 2034static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2035{
ce01e4e8
CD		 2036 int r;
2037
2038 switch (attr->group) {
2039 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2040 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2041 u64 addr;
2042 unsigned long type = (unsigned long)attr->attr;
2043
2044 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2045 return -EFAULT;
2046
2047 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2048 return (r == -ENODEV) ? -ENXIO : r;
2049 }
c07a0191
CD		 2050
2051 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2052 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2053 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2054 u32 reg;
2055
2056 if (get_user(reg, uaddr))
2057 return -EFAULT;
2058
2059 return vgic_attr_regs_access(dev, attr, &reg, true);
2060 }
2061
ce01e4e8
CD		 2062 }
2063
7330672b
CD		 2064 return -ENXIO;
2065}
2066
2067static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2068{
ce01e4e8
CD		 2069 int r = -ENXIO;
2070
2071 switch (attr->group) {
2072 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2073 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2074 u64 addr;
2075 unsigned long type = (unsigned long)attr->attr;
2076
2077 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2078 if (r)
2079 return (r == -ENODEV) ? -ENXIO : r;
2080
2081 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2082 return -EFAULT;
c07a0191
CD		 2083 break;
2084 }
2085
2086 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2087 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2088 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2089 u32 reg = 0;
2090
2091 r = vgic_attr_regs_access(dev, attr, &reg, false);
2092 if (r)
2093 return r;
2094 r = put_user(reg, uaddr);
2095 break;
ce01e4e8 2096 }
c07a0191 2097
ce01e4e8
CD		 2098 }
2099
2100 return r;
7330672b
CD		 2101}
2102
c07a0191
CD		 2103static int vgic_has_attr_regs(const struct mmio_range *ranges,
2104 phys_addr_t offset)
2105{
2106 struct kvm_exit_mmio dev_attr_mmio;
2107
2108 dev_attr_mmio.len = 4;
2109 if (find_matching_range(ranges, &dev_attr_mmio, offset))
2110 return 0;
2111 else
2112 return -ENXIO;
2113}
2114
7330672b
CD		 2115static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2116{
c07a0191
CD		 2117 phys_addr_t offset;
2118
ce01e4e8
CD		 2119 switch (attr->group) {
2120 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2121 switch (attr->attr) {
2122 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2123 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2124 return 0;
2125 }
2126 break;
c07a0191
CD		 2127 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2128 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2129 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2130 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2131 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2132 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
ce01e4e8 2133 }
7330672b
CD		 2134 return -ENXIO;
2135}
2136
2137static void vgic_destroy(struct kvm_device *dev)
2138{
2139 kfree(dev);
2140}
2141
2142static int vgic_create(struct kvm_device *dev, u32 type)
2143{
2144 return kvm_vgic_create(dev->kvm);
2145}
2146
2147struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2148 .name = "kvm-arm-vgic",
2149 .create = vgic_create,
2150 .destroy = vgic_destroy,
2151 .set_attr = vgic_set_attr,
2152 .get_attr = vgic_get_attr,
2153 .has_attr = vgic_has_attr,
2154};
Linux kernel - Deliverables
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