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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
39 | * something is pending | |
40 | * - VGIC pending interrupts are stored on the vgic.irq_state vgic | |
41 | * bitmap (this bitmap is updated by both user land ioctls and guest | |
42 | * mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers) and indicate the 'wire' state. | |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is | |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
48 | * - PPI: dist->irq_state & dist->irq_enable | |
49 | * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target | |
50 | * - irq_spi_target is a 'formatted' version of the GICD_ICFGR | |
51 | * registers, stored on each vcpu. We only keep one bit of | |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
54 | * - The same is true when injecting an interrupt, except that we only | |
55 | * consider a single interrupt at a time. The irq_spi_cpu array | |
56 | * contains the target CPU for each SPI. | |
57 | * | |
58 | * The handling of level interrupts adds some extra complexity. We | |
59 | * need to track when the interrupt has been EOIed, so we can sample | |
60 | * the 'line' again. This is achieved as such: | |
61 | * | |
62 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
63 | * bit in irq_active is set. As long as this bit is set, the line | |
64 | * will be ignored for further interrupts. The interrupt is injected | |
65 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
66 | * maintenance interrupt on EOI). | |
67 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
68 | * and clears the corresponding bit in irq_active. This allow the | |
69 | * interrupt line to be sampled again. | |
70 | */ | |
71 | ||
330690cd CD |
72 | #define VGIC_ADDR_UNDEF (-1) |
73 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) | |
74 | ||
fa20f5ae CD |
75 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
76 | #define IMPLEMENTER_ARM 0x43b | |
77 | #define GICC_ARCH_VERSION_V2 0x2 | |
78 | ||
1a89dd91 MZ |
79 | #define ACCESS_READ_VALUE (1 << 0) |
80 | #define ACCESS_READ_RAZ (0 << 0) | |
81 | #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) | |
82 | #define ACCESS_WRITE_IGNORED (0 << 1) | |
83 | #define ACCESS_WRITE_SETBIT (1 << 1) | |
84 | #define ACCESS_WRITE_CLEARBIT (2 << 1) | |
85 | #define ACCESS_WRITE_VALUE (3 << 1) | |
86 | #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) | |
87 | ||
a1fcb44e | 88 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 89 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
b47ef92a | 90 | static void vgic_update_state(struct kvm *kvm); |
5863c2ce | 91 | static void vgic_kick_vcpus(struct kvm *kvm); |
b47ef92a | 92 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
8d5c6b06 MZ |
93 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
94 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
beee38b9 MZ |
95 | static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
96 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
01ac5e34 | 97 | |
8f186d52 MZ |
98 | static const struct vgic_ops *vgic_ops; |
99 | static const struct vgic_params *vgic; | |
b47ef92a MZ |
100 | |
101 | static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, | |
102 | int cpuid, u32 offset) | |
103 | { | |
104 | offset >>= 2; | |
105 | if (!offset) | |
106 | return x->percpu[cpuid].reg; | |
107 | else | |
108 | return x->shared.reg + offset - 1; | |
109 | } | |
110 | ||
111 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
112 | int cpuid, int irq) | |
113 | { | |
114 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
115 | return test_bit(irq, x->percpu[cpuid].reg_ul); | |
116 | ||
117 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul); | |
118 | } | |
119 | ||
120 | static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, | |
121 | int irq, int val) | |
122 | { | |
123 | unsigned long *reg; | |
124 | ||
125 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
126 | reg = x->percpu[cpuid].reg_ul; | |
127 | } else { | |
128 | reg = x->shared.reg_ul; | |
129 | irq -= VGIC_NR_PRIVATE_IRQS; | |
130 | } | |
131 | ||
132 | if (val) | |
133 | set_bit(irq, reg); | |
134 | else | |
135 | clear_bit(irq, reg); | |
136 | } | |
137 | ||
138 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
139 | { | |
140 | if (unlikely(cpuid >= VGIC_MAX_CPUS)) | |
141 | return NULL; | |
142 | return x->percpu[cpuid].reg_ul; | |
143 | } | |
144 | ||
145 | static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) | |
146 | { | |
147 | return x->shared.reg_ul; | |
148 | } | |
149 | ||
150 | static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) | |
151 | { | |
152 | offset >>= 2; | |
153 | BUG_ON(offset > (VGIC_NR_IRQS / 4)); | |
8d98915b | 154 | if (offset < 8) |
b47ef92a MZ |
155 | return x->percpu[cpuid] + offset; |
156 | else | |
157 | return x->shared + offset - 8; | |
158 | } | |
159 | ||
160 | #define VGIC_CFG_LEVEL 0 | |
161 | #define VGIC_CFG_EDGE 1 | |
162 | ||
163 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
164 | { | |
165 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
166 | int irq_val; | |
167 | ||
168 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
169 | return irq_val == VGIC_CFG_EDGE; | |
170 | } | |
171 | ||
172 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
173 | { | |
174 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
175 | ||
176 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
177 | } | |
178 | ||
9d949dce MZ |
179 | static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq) |
180 | { | |
181 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
182 | ||
183 | return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq); | |
184 | } | |
185 | ||
186 | static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq) | |
187 | { | |
188 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
189 | ||
190 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1); | |
191 | } | |
192 | ||
193 | static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq) | |
194 | { | |
195 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
196 | ||
197 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0); | |
198 | } | |
199 | ||
200 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) | |
201 | { | |
202 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
203 | ||
204 | return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq); | |
205 | } | |
206 | ||
b47ef92a MZ |
207 | static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq) |
208 | { | |
209 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
210 | ||
211 | vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1); | |
212 | } | |
213 | ||
214 | static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
215 | { | |
216 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
217 | ||
218 | vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0); | |
219 | } | |
220 | ||
221 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
222 | { | |
223 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
224 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
225 | else | |
226 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
227 | vcpu->arch.vgic_cpu.pending_shared); | |
228 | } | |
229 | ||
230 | static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
231 | { | |
232 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
233 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
234 | else | |
235 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
236 | vcpu->arch.vgic_cpu.pending_shared); | |
237 | } | |
238 | ||
1a89dd91 MZ |
239 | static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) |
240 | { | |
241 | return *((u32 *)mmio->data) & mask; | |
242 | } | |
243 | ||
244 | static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) | |
245 | { | |
246 | *((u32 *)mmio->data) = value & mask; | |
247 | } | |
248 | ||
249 | /** | |
250 | * vgic_reg_access - access vgic register | |
251 | * @mmio: pointer to the data describing the mmio access | |
252 | * @reg: pointer to the virtual backing of vgic distributor data | |
253 | * @offset: least significant 2 bits used for word offset | |
254 | * @mode: ACCESS_ mode (see defines above) | |
255 | * | |
256 | * Helper to make vgic register access easier using one of the access | |
257 | * modes defined for vgic register access | |
258 | * (read,raz,write-ignored,setbit,clearbit,write) | |
259 | */ | |
260 | static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, | |
261 | phys_addr_t offset, int mode) | |
262 | { | |
263 | int word_offset = (offset & 3) * 8; | |
264 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
265 | u32 regval; | |
266 | ||
267 | /* | |
268 | * Any alignment fault should have been delivered to the guest | |
269 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
270 | */ | |
271 | ||
272 | if (reg) { | |
273 | regval = *reg; | |
274 | } else { | |
275 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
276 | regval = 0; | |
277 | } | |
278 | ||
279 | if (mmio->is_write) { | |
280 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
281 | switch (ACCESS_WRITE_MASK(mode)) { | |
282 | case ACCESS_WRITE_IGNORED: | |
283 | return; | |
284 | ||
285 | case ACCESS_WRITE_SETBIT: | |
286 | regval |= data; | |
287 | break; | |
288 | ||
289 | case ACCESS_WRITE_CLEARBIT: | |
290 | regval &= ~data; | |
291 | break; | |
292 | ||
293 | case ACCESS_WRITE_VALUE: | |
294 | regval = (regval & ~(mask << word_offset)) | data; | |
295 | break; | |
296 | } | |
297 | *reg = regval; | |
298 | } else { | |
299 | switch (ACCESS_READ_MASK(mode)) { | |
300 | case ACCESS_READ_RAZ: | |
301 | regval = 0; | |
302 | /* fall through */ | |
303 | ||
304 | case ACCESS_READ_VALUE: | |
305 | mmio_data_write(mmio, mask, regval >> word_offset); | |
306 | } | |
307 | } | |
308 | } | |
309 | ||
b47ef92a MZ |
310 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
311 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
312 | { | |
313 | u32 reg; | |
314 | u32 word_offset = offset & 3; | |
315 | ||
316 | switch (offset & ~3) { | |
fa20f5ae | 317 | case 0: /* GICD_CTLR */ |
b47ef92a MZ |
318 | reg = vcpu->kvm->arch.vgic.enabled; |
319 | vgic_reg_access(mmio, ®, word_offset, | |
320 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
321 | if (mmio->is_write) { | |
322 | vcpu->kvm->arch.vgic.enabled = reg & 1; | |
323 | vgic_update_state(vcpu->kvm); | |
324 | return true; | |
325 | } | |
326 | break; | |
327 | ||
fa20f5ae | 328 | case 4: /* GICD_TYPER */ |
b47ef92a MZ |
329 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
330 | reg |= (VGIC_NR_IRQS >> 5) - 1; | |
331 | vgic_reg_access(mmio, ®, word_offset, | |
332 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
333 | break; | |
334 | ||
fa20f5ae CD |
335 | case 8: /* GICD_IIDR */ |
336 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
b47ef92a MZ |
337 | vgic_reg_access(mmio, ®, word_offset, |
338 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
339 | break; | |
340 | } | |
341 | ||
342 | return false; | |
343 | } | |
344 | ||
345 | static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, | |
346 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
347 | { | |
348 | vgic_reg_access(mmio, NULL, offset, | |
349 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
350 | return false; | |
351 | } | |
352 | ||
353 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, | |
354 | struct kvm_exit_mmio *mmio, | |
355 | phys_addr_t offset) | |
356 | { | |
357 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
358 | vcpu->vcpu_id, offset); | |
359 | vgic_reg_access(mmio, reg, offset, | |
360 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
361 | if (mmio->is_write) { | |
362 | vgic_update_state(vcpu->kvm); | |
363 | return true; | |
364 | } | |
365 | ||
366 | return false; | |
367 | } | |
368 | ||
369 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, | |
370 | struct kvm_exit_mmio *mmio, | |
371 | phys_addr_t offset) | |
372 | { | |
373 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
374 | vcpu->vcpu_id, offset); | |
375 | vgic_reg_access(mmio, reg, offset, | |
376 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
377 | if (mmio->is_write) { | |
378 | if (offset < 4) /* Force SGI enabled */ | |
379 | *reg |= 0xffff; | |
a1fcb44e | 380 | vgic_retire_disabled_irqs(vcpu); |
b47ef92a MZ |
381 | vgic_update_state(vcpu->kvm); |
382 | return true; | |
383 | } | |
384 | ||
385 | return false; | |
386 | } | |
387 | ||
388 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, | |
389 | struct kvm_exit_mmio *mmio, | |
390 | phys_addr_t offset) | |
391 | { | |
392 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state, | |
393 | vcpu->vcpu_id, offset); | |
394 | vgic_reg_access(mmio, reg, offset, | |
395 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
396 | if (mmio->is_write) { | |
397 | vgic_update_state(vcpu->kvm); | |
398 | return true; | |
399 | } | |
400 | ||
401 | return false; | |
402 | } | |
403 | ||
404 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, | |
405 | struct kvm_exit_mmio *mmio, | |
406 | phys_addr_t offset) | |
407 | { | |
408 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state, | |
409 | vcpu->vcpu_id, offset); | |
410 | vgic_reg_access(mmio, reg, offset, | |
411 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
412 | if (mmio->is_write) { | |
413 | vgic_update_state(vcpu->kvm); | |
414 | return true; | |
415 | } | |
416 | ||
417 | return false; | |
418 | } | |
419 | ||
420 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, | |
421 | struct kvm_exit_mmio *mmio, | |
422 | phys_addr_t offset) | |
423 | { | |
424 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, | |
425 | vcpu->vcpu_id, offset); | |
426 | vgic_reg_access(mmio, reg, offset, | |
427 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
428 | return false; | |
429 | } | |
430 | ||
431 | #define GICD_ITARGETSR_SIZE 32 | |
432 | #define GICD_CPUTARGETS_BITS 8 | |
433 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) | |
434 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) | |
435 | { | |
436 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986af8e0 | 437 | int i; |
b47ef92a MZ |
438 | u32 val = 0; |
439 | ||
440 | irq -= VGIC_NR_PRIVATE_IRQS; | |
441 | ||
986af8e0 MZ |
442 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
443 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); | |
b47ef92a MZ |
444 | |
445 | return val; | |
446 | } | |
447 | ||
448 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) | |
449 | { | |
450 | struct vgic_dist *dist = &kvm->arch.vgic; | |
451 | struct kvm_vcpu *vcpu; | |
452 | int i, c; | |
453 | unsigned long *bmap; | |
454 | u32 target; | |
455 | ||
456 | irq -= VGIC_NR_PRIVATE_IRQS; | |
457 | ||
458 | /* | |
459 | * Pick the LSB in each byte. This ensures we target exactly | |
460 | * one vcpu per IRQ. If the byte is null, assume we target | |
461 | * CPU0. | |
462 | */ | |
463 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { | |
464 | int shift = i * GICD_CPUTARGETS_BITS; | |
465 | target = ffs((val >> shift) & 0xffU); | |
466 | target = target ? (target - 1) : 0; | |
467 | dist->irq_spi_cpu[irq + i] = target; | |
468 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
469 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); | |
470 | if (c == target) | |
471 | set_bit(irq + i, bmap); | |
472 | else | |
473 | clear_bit(irq + i, bmap); | |
474 | } | |
475 | } | |
476 | } | |
477 | ||
478 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, | |
479 | struct kvm_exit_mmio *mmio, | |
480 | phys_addr_t offset) | |
481 | { | |
482 | u32 reg; | |
483 | ||
484 | /* We treat the banked interrupts targets as read-only */ | |
485 | if (offset < 32) { | |
486 | u32 roreg = 1 << vcpu->vcpu_id; | |
487 | roreg |= roreg << 8; | |
488 | roreg |= roreg << 16; | |
489 | ||
490 | vgic_reg_access(mmio, &roreg, offset, | |
491 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
492 | return false; | |
493 | } | |
494 | ||
495 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); | |
496 | vgic_reg_access(mmio, ®, offset, | |
497 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
498 | if (mmio->is_write) { | |
499 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); | |
500 | vgic_update_state(vcpu->kvm); | |
501 | return true; | |
502 | } | |
503 | ||
504 | return false; | |
505 | } | |
506 | ||
507 | static u32 vgic_cfg_expand(u16 val) | |
508 | { | |
509 | u32 res = 0; | |
510 | int i; | |
511 | ||
512 | /* | |
513 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
514 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
515 | */ | |
516 | for (i = 0; i < 16; i++) | |
517 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
518 | ||
519 | return res; | |
520 | } | |
521 | ||
522 | static u16 vgic_cfg_compress(u32 val) | |
523 | { | |
524 | u16 res = 0; | |
525 | int i; | |
526 | ||
527 | /* | |
528 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
529 | * abcd...mnop which is what we really care about. | |
530 | */ | |
531 | for (i = 0; i < 16; i++) | |
532 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
533 | ||
534 | return res; | |
535 | } | |
536 | ||
537 | /* | |
538 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
539 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
540 | * two above functions to compress/expand the bits | |
541 | */ | |
542 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, | |
543 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
544 | { | |
545 | u32 val; | |
6545eae3 MZ |
546 | u32 *reg; |
547 | ||
6545eae3 | 548 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
f2ae85b2 | 549 | vcpu->vcpu_id, offset >> 1); |
6545eae3 | 550 | |
f2ae85b2 | 551 | if (offset & 4) |
b47ef92a MZ |
552 | val = *reg >> 16; |
553 | else | |
554 | val = *reg & 0xffff; | |
555 | ||
556 | val = vgic_cfg_expand(val); | |
557 | vgic_reg_access(mmio, &val, offset, | |
558 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
559 | if (mmio->is_write) { | |
f2ae85b2 | 560 | if (offset < 8) { |
b47ef92a MZ |
561 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
562 | return false; | |
563 | } | |
564 | ||
565 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 566 | if (offset & 4) { |
b47ef92a MZ |
567 | *reg &= 0xffff; |
568 | *reg |= val << 16; | |
569 | } else { | |
570 | *reg &= 0xffff << 16; | |
571 | *reg |= val; | |
572 | } | |
573 | } | |
574 | ||
575 | return false; | |
576 | } | |
577 | ||
578 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, | |
579 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
580 | { | |
581 | u32 reg; | |
582 | vgic_reg_access(mmio, ®, offset, | |
583 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); | |
584 | if (mmio->is_write) { | |
585 | vgic_dispatch_sgi(vcpu, reg); | |
586 | vgic_update_state(vcpu->kvm); | |
587 | return true; | |
588 | } | |
589 | ||
590 | return false; | |
591 | } | |
592 | ||
cbd333a4 CD |
593 | /** |
594 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
595 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
596 | * | |
597 | * Move any pending IRQs that have already been assigned to LRs back to the | |
598 | * emulated distributor state so that the complete emulated state can be read | |
599 | * from the main emulation structures without investigating the LRs. | |
600 | * | |
601 | * Note that IRQs in the active state in the LRs get their pending state moved | |
602 | * to the distributor but the active state stays in the LRs, because we don't | |
603 | * track the active state on the distributor side. | |
604 | */ | |
605 | static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) | |
606 | { | |
607 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
608 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
609 | int vcpu_id = vcpu->vcpu_id; | |
8d5c6b06 | 610 | int i; |
cbd333a4 CD |
611 | |
612 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 613 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
614 | |
615 | /* | |
616 | * There are three options for the state bits: | |
617 | * | |
618 | * 01: pending | |
619 | * 10: active | |
620 | * 11: pending and active | |
621 | * | |
622 | * If the LR holds only an active interrupt (not pending) then | |
623 | * just leave it alone. | |
624 | */ | |
8d5c6b06 | 625 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
626 | continue; |
627 | ||
628 | /* | |
629 | * Reestablish the pending state on the distributor and the | |
630 | * CPU interface. It may have already been pending, but that | |
631 | * is fine, then we are only setting a few bits that were | |
632 | * already set. | |
633 | */ | |
8d5c6b06 MZ |
634 | vgic_dist_irq_set(vcpu, lr.irq); |
635 | if (lr.irq < VGIC_NR_SGIS) | |
636 | dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source; | |
637 | lr.state &= ~LR_STATE_PENDING; | |
638 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
639 | |
640 | /* | |
641 | * If there's no state left on the LR (it could still be | |
642 | * active), then the LR does not hold any useful info and can | |
643 | * be marked as free for other use. | |
644 | */ | |
8d5c6b06 MZ |
645 | if (!(lr.state & LR_STATE_MASK)) |
646 | vgic_retire_lr(i, lr.irq, vcpu); | |
cbd333a4 CD |
647 | |
648 | /* Finally update the VGIC state. */ | |
649 | vgic_update_state(vcpu->kvm); | |
650 | } | |
651 | } | |
652 | ||
90a5355e CD |
653 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
654 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, | |
655 | struct kvm_exit_mmio *mmio, | |
656 | phys_addr_t offset) | |
c07a0191 | 657 | { |
90a5355e CD |
658 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
659 | int sgi; | |
660 | int min_sgi = (offset & ~0x3) * 4; | |
661 | int max_sgi = min_sgi + 3; | |
662 | int vcpu_id = vcpu->vcpu_id; | |
663 | u32 reg = 0; | |
664 | ||
665 | /* Copy source SGIs from distributor side */ | |
666 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
667 | int shift = 8 * (sgi - min_sgi); | |
668 | reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift; | |
669 | } | |
670 | ||
671 | mmio_data_write(mmio, ~0, reg); | |
c07a0191 CD |
672 | return false; |
673 | } | |
674 | ||
90a5355e CD |
675 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
676 | struct kvm_exit_mmio *mmio, | |
677 | phys_addr_t offset, bool set) | |
678 | { | |
679 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
680 | int sgi; | |
681 | int min_sgi = (offset & ~0x3) * 4; | |
682 | int max_sgi = min_sgi + 3; | |
683 | int vcpu_id = vcpu->vcpu_id; | |
684 | u32 reg; | |
685 | bool updated = false; | |
686 | ||
687 | reg = mmio_data_read(mmio, ~0); | |
688 | ||
689 | /* Clear pending SGIs on the distributor */ | |
690 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
691 | u8 mask = reg >> (8 * (sgi - min_sgi)); | |
692 | if (set) { | |
693 | if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask) | |
694 | updated = true; | |
695 | dist->irq_sgi_sources[vcpu_id][sgi] |= mask; | |
696 | } else { | |
697 | if (dist->irq_sgi_sources[vcpu_id][sgi] & mask) | |
698 | updated = true; | |
699 | dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask; | |
700 | } | |
701 | } | |
702 | ||
703 | if (updated) | |
704 | vgic_update_state(vcpu->kvm); | |
705 | ||
706 | return updated; | |
707 | } | |
708 | ||
c07a0191 CD |
709 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
710 | struct kvm_exit_mmio *mmio, | |
711 | phys_addr_t offset) | |
712 | { | |
90a5355e CD |
713 | if (!mmio->is_write) |
714 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
715 | else | |
716 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); | |
717 | } | |
718 | ||
719 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, | |
720 | struct kvm_exit_mmio *mmio, | |
721 | phys_addr_t offset) | |
722 | { | |
723 | if (!mmio->is_write) | |
724 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
725 | else | |
726 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); | |
c07a0191 CD |
727 | } |
728 | ||
1a89dd91 MZ |
729 | /* |
730 | * I would have liked to use the kvm_bus_io_*() API instead, but it | |
731 | * cannot cope with banked registers (only the VM pointer is passed | |
732 | * around, and we need the vcpu). One of these days, someone please | |
733 | * fix it! | |
734 | */ | |
735 | struct mmio_range { | |
736 | phys_addr_t base; | |
737 | unsigned long len; | |
738 | bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, | |
739 | phys_addr_t offset); | |
740 | }; | |
741 | ||
1006e8cb | 742 | static const struct mmio_range vgic_dist_ranges[] = { |
b47ef92a MZ |
743 | { |
744 | .base = GIC_DIST_CTRL, | |
745 | .len = 12, | |
746 | .handle_mmio = handle_mmio_misc, | |
747 | }, | |
748 | { | |
749 | .base = GIC_DIST_IGROUP, | |
750 | .len = VGIC_NR_IRQS / 8, | |
751 | .handle_mmio = handle_mmio_raz_wi, | |
752 | }, | |
753 | { | |
754 | .base = GIC_DIST_ENABLE_SET, | |
755 | .len = VGIC_NR_IRQS / 8, | |
756 | .handle_mmio = handle_mmio_set_enable_reg, | |
757 | }, | |
758 | { | |
759 | .base = GIC_DIST_ENABLE_CLEAR, | |
760 | .len = VGIC_NR_IRQS / 8, | |
761 | .handle_mmio = handle_mmio_clear_enable_reg, | |
762 | }, | |
763 | { | |
764 | .base = GIC_DIST_PENDING_SET, | |
765 | .len = VGIC_NR_IRQS / 8, | |
766 | .handle_mmio = handle_mmio_set_pending_reg, | |
767 | }, | |
768 | { | |
769 | .base = GIC_DIST_PENDING_CLEAR, | |
770 | .len = VGIC_NR_IRQS / 8, | |
771 | .handle_mmio = handle_mmio_clear_pending_reg, | |
772 | }, | |
773 | { | |
774 | .base = GIC_DIST_ACTIVE_SET, | |
775 | .len = VGIC_NR_IRQS / 8, | |
776 | .handle_mmio = handle_mmio_raz_wi, | |
777 | }, | |
778 | { | |
779 | .base = GIC_DIST_ACTIVE_CLEAR, | |
780 | .len = VGIC_NR_IRQS / 8, | |
781 | .handle_mmio = handle_mmio_raz_wi, | |
782 | }, | |
783 | { | |
784 | .base = GIC_DIST_PRI, | |
785 | .len = VGIC_NR_IRQS, | |
786 | .handle_mmio = handle_mmio_priority_reg, | |
787 | }, | |
788 | { | |
789 | .base = GIC_DIST_TARGET, | |
790 | .len = VGIC_NR_IRQS, | |
791 | .handle_mmio = handle_mmio_target_reg, | |
792 | }, | |
793 | { | |
794 | .base = GIC_DIST_CONFIG, | |
795 | .len = VGIC_NR_IRQS / 4, | |
796 | .handle_mmio = handle_mmio_cfg_reg, | |
797 | }, | |
798 | { | |
799 | .base = GIC_DIST_SOFTINT, | |
800 | .len = 4, | |
801 | .handle_mmio = handle_mmio_sgi_reg, | |
802 | }, | |
c07a0191 CD |
803 | { |
804 | .base = GIC_DIST_SGI_PENDING_CLEAR, | |
805 | .len = VGIC_NR_SGIS, | |
806 | .handle_mmio = handle_mmio_sgi_clear, | |
807 | }, | |
808 | { | |
809 | .base = GIC_DIST_SGI_PENDING_SET, | |
810 | .len = VGIC_NR_SGIS, | |
811 | .handle_mmio = handle_mmio_sgi_set, | |
812 | }, | |
1a89dd91 MZ |
813 | {} |
814 | }; | |
815 | ||
816 | static const | |
817 | struct mmio_range *find_matching_range(const struct mmio_range *ranges, | |
818 | struct kvm_exit_mmio *mmio, | |
1006e8cb | 819 | phys_addr_t offset) |
1a89dd91 MZ |
820 | { |
821 | const struct mmio_range *r = ranges; | |
1a89dd91 MZ |
822 | |
823 | while (r->len) { | |
1006e8cb CD |
824 | if (offset >= r->base && |
825 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
826 | return r; |
827 | r++; | |
828 | } | |
829 | ||
830 | return NULL; | |
831 | } | |
832 | ||
833 | /** | |
834 | * vgic_handle_mmio - handle an in-kernel MMIO access | |
835 | * @vcpu: pointer to the vcpu performing the access | |
836 | * @run: pointer to the kvm_run structure | |
837 | * @mmio: pointer to the data describing the access | |
838 | * | |
839 | * returns true if the MMIO access has been performed in kernel space, | |
840 | * and false if it needs to be emulated in user space. | |
841 | */ | |
842 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
843 | struct kvm_exit_mmio *mmio) | |
844 | { | |
b47ef92a MZ |
845 | const struct mmio_range *range; |
846 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
847 | unsigned long base = dist->vgic_dist_base; | |
848 | bool updated_state; | |
849 | unsigned long offset; | |
850 | ||
851 | if (!irqchip_in_kernel(vcpu->kvm) || | |
852 | mmio->phys_addr < base || | |
853 | (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE)) | |
854 | return false; | |
855 | ||
856 | /* We don't support ldrd / strd or ldm / stm to the emulated vgic */ | |
857 | if (mmio->len > 4) { | |
858 | kvm_inject_dabt(vcpu, mmio->phys_addr); | |
859 | return true; | |
860 | } | |
861 | ||
1006e8cb CD |
862 | offset = mmio->phys_addr - base; |
863 | range = find_matching_range(vgic_dist_ranges, mmio, offset); | |
b47ef92a MZ |
864 | if (unlikely(!range || !range->handle_mmio)) { |
865 | pr_warn("Unhandled access %d %08llx %d\n", | |
866 | mmio->is_write, mmio->phys_addr, mmio->len); | |
867 | return false; | |
868 | } | |
869 | ||
870 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
871 | offset = mmio->phys_addr - range->base - base; | |
872 | updated_state = range->handle_mmio(vcpu, mmio, offset); | |
873 | spin_unlock(&vcpu->kvm->arch.vgic.lock); | |
874 | kvm_prepare_mmio(run, mmio); | |
875 | kvm_handle_mmio_return(vcpu, run); | |
876 | ||
5863c2ce MZ |
877 | if (updated_state) |
878 | vgic_kick_vcpus(vcpu->kvm); | |
879 | ||
b47ef92a MZ |
880 | return true; |
881 | } | |
882 | ||
883 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) | |
884 | { | |
885 | struct kvm *kvm = vcpu->kvm; | |
886 | struct vgic_dist *dist = &kvm->arch.vgic; | |
887 | int nrcpus = atomic_read(&kvm->online_vcpus); | |
888 | u8 target_cpus; | |
889 | int sgi, mode, c, vcpu_id; | |
890 | ||
891 | vcpu_id = vcpu->vcpu_id; | |
892 | ||
893 | sgi = reg & 0xf; | |
894 | target_cpus = (reg >> 16) & 0xff; | |
895 | mode = (reg >> 24) & 3; | |
896 | ||
897 | switch (mode) { | |
898 | case 0: | |
899 | if (!target_cpus) | |
900 | return; | |
91021a6c | 901 | break; |
b47ef92a MZ |
902 | |
903 | case 1: | |
904 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; | |
905 | break; | |
906 | ||
907 | case 2: | |
908 | target_cpus = 1 << vcpu_id; | |
909 | break; | |
910 | } | |
911 | ||
912 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
913 | if (target_cpus & 1) { | |
914 | /* Flag the SGI as pending */ | |
915 | vgic_dist_irq_set(vcpu, sgi); | |
916 | dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id; | |
917 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); | |
918 | } | |
919 | ||
920 | target_cpus >>= 1; | |
921 | } | |
922 | } | |
923 | ||
924 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) | |
925 | { | |
9d949dce MZ |
926 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
927 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
928 | unsigned long pending_private, pending_shared; | |
929 | int vcpu_id; | |
930 | ||
931 | vcpu_id = vcpu->vcpu_id; | |
932 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
933 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
934 | ||
935 | pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id); | |
936 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); | |
937 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
938 | ||
939 | pending = vgic_bitmap_get_shared_map(&dist->irq_state); | |
940 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); | |
941 | bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS); | |
942 | bitmap_and(pend_shared, pend_shared, | |
943 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
944 | VGIC_NR_SHARED_IRQS); | |
945 | ||
946 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
947 | pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS); | |
948 | return (pending_private < VGIC_NR_PRIVATE_IRQS || | |
949 | pending_shared < VGIC_NR_SHARED_IRQS); | |
b47ef92a MZ |
950 | } |
951 | ||
952 | /* | |
953 | * Update the interrupt state and determine which CPUs have pending | |
954 | * interrupts. Must be called with distributor lock held. | |
955 | */ | |
956 | static void vgic_update_state(struct kvm *kvm) | |
957 | { | |
958 | struct vgic_dist *dist = &kvm->arch.vgic; | |
959 | struct kvm_vcpu *vcpu; | |
960 | int c; | |
961 | ||
962 | if (!dist->enabled) { | |
963 | set_bit(0, &dist->irq_pending_on_cpu); | |
964 | return; | |
965 | } | |
966 | ||
967 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
968 | if (compute_pending_for_cpu(vcpu)) { | |
969 | pr_debug("CPU%d has pending interrupts\n", c); | |
970 | set_bit(c, &dist->irq_pending_on_cpu); | |
971 | } | |
972 | } | |
1a89dd91 | 973 | } |
330690cd | 974 | |
8d5c6b06 MZ |
975 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
976 | { | |
8f186d52 | 977 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
978 | } |
979 | ||
980 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
981 | struct vgic_lr vlr) | |
982 | { | |
8f186d52 | 983 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
984 | } |
985 | ||
69bb2c9f MZ |
986 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
987 | struct vgic_lr vlr) | |
988 | { | |
8f186d52 | 989 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
990 | } |
991 | ||
992 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
993 | { | |
8f186d52 | 994 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
995 | } |
996 | ||
8d6a0313 MZ |
997 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
998 | { | |
8f186d52 | 999 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1000 | } |
1001 | ||
495dd859 MZ |
1002 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1003 | { | |
8f186d52 | 1004 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1005 | } |
1006 | ||
909d9b50 MZ |
1007 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1008 | { | |
8f186d52 | 1009 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1010 | } |
1011 | ||
1012 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1013 | { | |
8f186d52 | 1014 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1015 | } |
1016 | ||
beee38b9 MZ |
1017 | static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
1018 | { | |
8f186d52 | 1019 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1020 | } |
1021 | ||
1022 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) | |
1023 | { | |
8f186d52 | 1024 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1025 | } |
1026 | ||
da8dafd1 MZ |
1027 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1028 | { | |
8f186d52 | 1029 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1030 | } |
1031 | ||
8d5c6b06 MZ |
1032 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1033 | { | |
1034 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1035 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1036 | ||
1037 | vlr.state = 0; | |
1038 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1039 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1040 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1041 | } | |
a1fcb44e MZ |
1042 | |
1043 | /* | |
1044 | * An interrupt may have been disabled after being made pending on the | |
1045 | * CPU interface (the classic case is a timer running while we're | |
1046 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1047 | * interface gets enabled, with deadly consequences). | |
1048 | * | |
1049 | * The solution is to examine already active LRs, and check the | |
1050 | * interrupt is still enabled. If not, just retire it. | |
1051 | */ | |
1052 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1053 | { | |
1054 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1055 | int lr; | |
1056 | ||
8f186d52 | 1057 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1058 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1059 | |
8d5c6b06 MZ |
1060 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1061 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
1062 | if (vgic_irq_is_active(vcpu, vlr.irq)) | |
1063 | vgic_irq_clear_active(vcpu, vlr.irq); | |
a1fcb44e MZ |
1064 | } |
1065 | } | |
1066 | } | |
1067 | ||
9d949dce MZ |
1068 | /* |
1069 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1070 | * or false if it wasn't possible to queue it. | |
1071 | */ | |
1072 | static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |
1073 | { | |
1074 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
8d5c6b06 | 1075 | struct vgic_lr vlr; |
9d949dce MZ |
1076 | int lr; |
1077 | ||
1078 | /* Sanitize the input... */ | |
1079 | BUG_ON(sgi_source_id & ~7); | |
1080 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
1081 | BUG_ON(irq >= VGIC_NR_IRQS); | |
1082 | ||
1083 | kvm_debug("Queue IRQ%d\n", irq); | |
1084 | ||
1085 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1086 | ||
1087 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1088 | if (lr != LR_EMPTY) { |
1089 | vlr = vgic_get_lr(vcpu, lr); | |
1090 | if (vlr.source == sgi_source_id) { | |
1091 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1092 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
1093 | vlr.state |= LR_STATE_PENDING; | |
1094 | vgic_set_lr(vcpu, lr, vlr); | |
1095 | return true; | |
1096 | } | |
9d949dce MZ |
1097 | } |
1098 | ||
1099 | /* Try to use another LR for this interrupt */ | |
1100 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1101 | vgic->nr_lr); |
1102 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1103 | return false; |
1104 | ||
1105 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1106 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1107 | set_bit(lr, vgic_cpu->lr_used); | |
1108 | ||
8d5c6b06 MZ |
1109 | vlr.irq = irq; |
1110 | vlr.source = sgi_source_id; | |
1111 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 1112 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
1113 | vlr.state |= LR_EOI_INT; |
1114 | ||
1115 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1116 | |
1117 | return true; | |
1118 | } | |
1119 | ||
1120 | static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
1121 | { | |
1122 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1123 | unsigned long sources; | |
1124 | int vcpu_id = vcpu->vcpu_id; | |
1125 | int c; | |
1126 | ||
1127 | sources = dist->irq_sgi_sources[vcpu_id][irq]; | |
1128 | ||
1129 | for_each_set_bit(c, &sources, VGIC_MAX_CPUS) { | |
1130 | if (vgic_queue_irq(vcpu, c, irq)) | |
1131 | clear_bit(c, &sources); | |
1132 | } | |
1133 | ||
1134 | dist->irq_sgi_sources[vcpu_id][irq] = sources; | |
1135 | ||
1136 | /* | |
1137 | * If the sources bitmap has been cleared it means that we | |
1138 | * could queue all the SGIs onto link registers (see the | |
1139 | * clear_bit above), and therefore we are done with them in | |
1140 | * our emulated gic and can get rid of them. | |
1141 | */ | |
1142 | if (!sources) { | |
1143 | vgic_dist_irq_clear(vcpu, irq); | |
1144 | vgic_cpu_irq_clear(vcpu, irq); | |
1145 | return true; | |
1146 | } | |
1147 | ||
1148 | return false; | |
1149 | } | |
1150 | ||
1151 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) | |
1152 | { | |
1153 | if (vgic_irq_is_active(vcpu, irq)) | |
1154 | return true; /* level interrupt, already queued */ | |
1155 | ||
1156 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1157 | if (vgic_irq_is_edge(vcpu, irq)) { | |
1158 | vgic_dist_irq_clear(vcpu, irq); | |
1159 | vgic_cpu_irq_clear(vcpu, irq); | |
1160 | } else { | |
1161 | vgic_irq_set_active(vcpu, irq); | |
1162 | } | |
1163 | ||
1164 | return true; | |
1165 | } | |
1166 | ||
1167 | return false; | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * Fill the list registers with pending interrupts before running the | |
1172 | * guest. | |
1173 | */ | |
1174 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1175 | { | |
1176 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1177 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1178 | int i, vcpu_id; | |
1179 | int overflow = 0; | |
1180 | ||
1181 | vcpu_id = vcpu->vcpu_id; | |
1182 | ||
1183 | /* | |
1184 | * We may not have any pending interrupt, or the interrupts | |
1185 | * may have been serviced from another vcpu. In all cases, | |
1186 | * move along. | |
1187 | */ | |
1188 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1189 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1190 | goto epilog; | |
1191 | } | |
1192 | ||
1193 | /* SGIs */ | |
1194 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
1195 | if (!vgic_queue_sgi(vcpu, i)) | |
1196 | overflow = 1; | |
1197 | } | |
1198 | ||
1199 | /* PPIs */ | |
1200 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1201 | if (!vgic_queue_hwirq(vcpu, i)) | |
1202 | overflow = 1; | |
1203 | } | |
1204 | ||
1205 | /* SPIs */ | |
1206 | for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) { | |
1207 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) | |
1208 | overflow = 1; | |
1209 | } | |
1210 | ||
1211 | epilog: | |
1212 | if (overflow) { | |
909d9b50 | 1213 | vgic_enable_underflow(vcpu); |
9d949dce | 1214 | } else { |
909d9b50 | 1215 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1216 | /* |
1217 | * We're about to run this VCPU, and we've consumed | |
1218 | * everything the distributor had in store for | |
1219 | * us. Claim we don't have anything pending. We'll | |
1220 | * adjust that if needed while exiting. | |
1221 | */ | |
1222 | clear_bit(vcpu_id, &dist->irq_pending_on_cpu); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1227 | { | |
495dd859 | 1228 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1229 | bool level_pending = false; |
1230 | ||
495dd859 | 1231 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1232 | |
495dd859 | 1233 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1234 | /* |
1235 | * Some level interrupts have been EOIed. Clear their | |
1236 | * active bit. | |
1237 | */ | |
8d6a0313 MZ |
1238 | u64 eisr = vgic_get_eisr(vcpu); |
1239 | unsigned long *eisr_ptr = (unsigned long *)&eisr; | |
8d5c6b06 | 1240 | int lr; |
9d949dce | 1241 | |
8f186d52 | 1242 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1243 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1244 | |
8d5c6b06 MZ |
1245 | vgic_irq_clear_active(vcpu, vlr.irq); |
1246 | WARN_ON(vlr.state & LR_STATE_MASK); | |
1247 | vlr.state = 0; | |
1248 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1249 | |
1250 | /* Any additional pending interrupt? */ | |
8d5c6b06 MZ |
1251 | if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) { |
1252 | vgic_cpu_irq_set(vcpu, vlr.irq); | |
9d949dce MZ |
1253 | level_pending = true; |
1254 | } else { | |
8d5c6b06 | 1255 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1256 | } |
75da01e1 MZ |
1257 | |
1258 | /* | |
1259 | * Despite being EOIed, the LR may not have | |
1260 | * been marked as empty. | |
1261 | */ | |
69bb2c9f | 1262 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1263 | } |
1264 | } | |
1265 | ||
495dd859 | 1266 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1267 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1268 | |
1269 | return level_pending; | |
1270 | } | |
1271 | ||
1272 | /* | |
33c83cb3 MZ |
1273 | * Sync back the VGIC state after a guest run. The distributor lock is |
1274 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1275 | */ |
1276 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1277 | { | |
1278 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1279 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1280 | u64 elrsr; |
1281 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1282 | int lr, pending; |
1283 | bool level_pending; | |
1284 | ||
1285 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f MZ |
1286 | elrsr = vgic_get_elrsr(vcpu); |
1287 | elrsr_ptr = (unsigned long *)&elrsr; | |
9d949dce MZ |
1288 | |
1289 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1290 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1291 | struct vgic_lr vlr; |
9d949dce MZ |
1292 | |
1293 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1294 | continue; | |
1295 | ||
8d5c6b06 | 1296 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1297 | |
8d5c6b06 MZ |
1298 | BUG_ON(vlr.irq >= VGIC_NR_IRQS); |
1299 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; | |
9d949dce MZ |
1300 | } |
1301 | ||
1302 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1303 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1304 | if (level_pending || pending < vgic->nr_lr) | |
9d949dce MZ |
1305 | set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); |
1306 | } | |
1307 | ||
1308 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1309 | { | |
1310 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1311 | ||
1312 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1313 | return; | |
1314 | ||
1315 | spin_lock(&dist->lock); | |
1316 | __kvm_vgic_flush_hwstate(vcpu); | |
1317 | spin_unlock(&dist->lock); | |
1318 | } | |
1319 | ||
1320 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1321 | { | |
33c83cb3 MZ |
1322 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1323 | ||
9d949dce MZ |
1324 | if (!irqchip_in_kernel(vcpu->kvm)) |
1325 | return; | |
1326 | ||
33c83cb3 | 1327 | spin_lock(&dist->lock); |
9d949dce | 1328 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1329 | spin_unlock(&dist->lock); |
9d949dce MZ |
1330 | } |
1331 | ||
1332 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1333 | { | |
1334 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1335 | ||
1336 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1337 | return 0; | |
1338 | ||
1339 | return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); | |
1340 | } | |
1341 | ||
5863c2ce MZ |
1342 | static void vgic_kick_vcpus(struct kvm *kvm) |
1343 | { | |
1344 | struct kvm_vcpu *vcpu; | |
1345 | int c; | |
1346 | ||
1347 | /* | |
1348 | * We've injected an interrupt, time to find out who deserves | |
1349 | * a good kick... | |
1350 | */ | |
1351 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1352 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1353 | kvm_vcpu_kick(vcpu); | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1358 | { | |
1359 | int is_edge = vgic_irq_is_edge(vcpu, irq); | |
1360 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
1361 | ||
1362 | /* | |
1363 | * Only inject an interrupt if: | |
1364 | * - edge triggered and we have a rising edge | |
1365 | * - level triggered and we change level | |
1366 | */ | |
1367 | if (is_edge) | |
1368 | return level > state; | |
1369 | else | |
1370 | return level != state; | |
1371 | } | |
1372 | ||
1373 | static bool vgic_update_irq_state(struct kvm *kvm, int cpuid, | |
1374 | unsigned int irq_num, bool level) | |
1375 | { | |
1376 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1377 | struct kvm_vcpu *vcpu; | |
1378 | int is_edge, is_level; | |
1379 | int enabled; | |
1380 | bool ret = true; | |
1381 | ||
1382 | spin_lock(&dist->lock); | |
1383 | ||
1384 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1385 | is_edge = vgic_irq_is_edge(vcpu, irq_num); | |
1386 | is_level = !is_edge; | |
1387 | ||
1388 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1389 | ret = false; | |
1390 | goto out; | |
1391 | } | |
1392 | ||
1393 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1394 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
1395 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1396 | } | |
1397 | ||
1398 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1399 | ||
1400 | if (level) | |
1401 | vgic_dist_irq_set(vcpu, irq_num); | |
1402 | else | |
1403 | vgic_dist_irq_clear(vcpu, irq_num); | |
1404 | ||
1405 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1406 | ||
1407 | if (!enabled) { | |
1408 | ret = false; | |
1409 | goto out; | |
1410 | } | |
1411 | ||
1412 | if (is_level && vgic_irq_is_active(vcpu, irq_num)) { | |
1413 | /* | |
1414 | * Level interrupt in progress, will be picked up | |
1415 | * when EOId. | |
1416 | */ | |
1417 | ret = false; | |
1418 | goto out; | |
1419 | } | |
1420 | ||
1421 | if (level) { | |
1422 | vgic_cpu_irq_set(vcpu, irq_num); | |
1423 | set_bit(cpuid, &dist->irq_pending_on_cpu); | |
1424 | } | |
1425 | ||
1426 | out: | |
1427 | spin_unlock(&dist->lock); | |
1428 | ||
1429 | return ret; | |
1430 | } | |
1431 | ||
1432 | /** | |
1433 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1434 | * @kvm: The VM structure pointer | |
1435 | * @cpuid: The CPU for PPIs | |
1436 | * @irq_num: The IRQ number that is assigned to the device | |
1437 | * @level: Edge-triggered: true: to trigger the interrupt | |
1438 | * false: to ignore the call | |
1439 | * Level-sensitive true: activates an interrupt | |
1440 | * false: deactivates an interrupt | |
1441 | * | |
1442 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1443 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1444 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1445 | */ | |
1446 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1447 | bool level) | |
1448 | { | |
1449 | if (vgic_update_irq_state(kvm, cpuid, irq_num, level)) | |
1450 | vgic_kick_vcpus(kvm); | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
01ac5e34 MZ |
1455 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1456 | { | |
1457 | /* | |
1458 | * We cannot rely on the vgic maintenance interrupt to be | |
1459 | * delivered synchronously. This means we can only use it to | |
1460 | * exit the VM, and we perform the handling of EOIed | |
1461 | * interrupts on the exit path (see vgic_process_maintenance). | |
1462 | */ | |
1463 | return IRQ_HANDLED; | |
1464 | } | |
1465 | ||
e1ba0207 CD |
1466 | /** |
1467 | * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state | |
1468 | * @vcpu: pointer to the vcpu struct | |
1469 | * | |
1470 | * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to | |
1471 | * this vcpu and enable the VGIC for this VCPU | |
1472 | */ | |
01ac5e34 MZ |
1473 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) |
1474 | { | |
1475 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1476 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1477 | int i; | |
1478 | ||
01ac5e34 MZ |
1479 | if (vcpu->vcpu_id >= VGIC_MAX_CPUS) |
1480 | return -EBUSY; | |
1481 | ||
1482 | for (i = 0; i < VGIC_NR_IRQS; i++) { | |
1483 | if (i < VGIC_NR_PPIS) | |
1484 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1485 | vcpu->vcpu_id, i, 1); | |
1486 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1487 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1488 | vcpu->vcpu_id, i, VGIC_CFG_EDGE); | |
1489 | ||
1490 | vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY; | |
1491 | } | |
1492 | ||
ca85f623 MZ |
1493 | /* |
1494 | * Store the number of LRs per vcpu, so we don't have to go | |
1495 | * all the way to the distributor structure to find out. Only | |
1496 | * assembly code should use this one. | |
1497 | */ | |
8f186d52 | 1498 | vgic_cpu->nr_lr = vgic->nr_lr; |
da8dafd1 MZ |
1499 | |
1500 | vgic_enable(vcpu); | |
01ac5e34 MZ |
1501 | |
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | static void vgic_init_maintenance_interrupt(void *info) | |
1506 | { | |
8f186d52 | 1507 | enable_percpu_irq(vgic->maint_irq, 0); |
01ac5e34 MZ |
1508 | } |
1509 | ||
1510 | static int vgic_cpu_notify(struct notifier_block *self, | |
1511 | unsigned long action, void *cpu) | |
1512 | { | |
1513 | switch (action) { | |
1514 | case CPU_STARTING: | |
1515 | case CPU_STARTING_FROZEN: | |
1516 | vgic_init_maintenance_interrupt(NULL); | |
1517 | break; | |
1518 | case CPU_DYING: | |
1519 | case CPU_DYING_FROZEN: | |
8f186d52 | 1520 | disable_percpu_irq(vgic->maint_irq); |
01ac5e34 MZ |
1521 | break; |
1522 | } | |
1523 | ||
1524 | return NOTIFY_OK; | |
1525 | } | |
1526 | ||
1527 | static struct notifier_block vgic_cpu_nb = { | |
1528 | .notifier_call = vgic_cpu_notify, | |
1529 | }; | |
1530 | ||
8f186d52 MZ |
1531 | static const struct of_device_id vgic_ids[] = { |
1532 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
67b2abfe | 1533 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, |
8f186d52 MZ |
1534 | {}, |
1535 | }; | |
1536 | ||
01ac5e34 MZ |
1537 | int kvm_vgic_hyp_init(void) |
1538 | { | |
8f186d52 MZ |
1539 | const struct of_device_id *matched_id; |
1540 | int (*vgic_probe)(struct device_node *,const struct vgic_ops **, | |
1541 | const struct vgic_params **); | |
ca85f623 | 1542 | struct device_node *vgic_node; |
8f186d52 | 1543 | int ret; |
01ac5e34 | 1544 | |
8f186d52 MZ |
1545 | vgic_node = of_find_matching_node_and_match(NULL, |
1546 | vgic_ids, &matched_id); | |
01ac5e34 | 1547 | if (!vgic_node) { |
8f186d52 | 1548 | kvm_err("error: no compatible GIC node found\n"); |
01ac5e34 MZ |
1549 | return -ENODEV; |
1550 | } | |
1551 | ||
8f186d52 MZ |
1552 | vgic_probe = matched_id->data; |
1553 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
1554 | if (ret) | |
1555 | return ret; | |
01ac5e34 | 1556 | |
8f186d52 | 1557 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, |
01ac5e34 MZ |
1558 | "vgic", kvm_get_running_vcpus()); |
1559 | if (ret) { | |
8f186d52 MZ |
1560 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); |
1561 | return ret; | |
01ac5e34 MZ |
1562 | } |
1563 | ||
553f809e | 1564 | ret = __register_cpu_notifier(&vgic_cpu_nb); |
01ac5e34 MZ |
1565 | if (ret) { |
1566 | kvm_err("Cannot register vgic CPU notifier\n"); | |
1567 | goto out_free_irq; | |
1568 | } | |
1569 | ||
01ac5e34 MZ |
1570 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); |
1571 | ||
1a9b1305 MZ |
1572 | /* Callback into for arch code for setup */ |
1573 | vgic_arch_setup(vgic); | |
1574 | ||
8f186d52 | 1575 | return 0; |
01ac5e34 | 1576 | |
01ac5e34 | 1577 | out_free_irq: |
8f186d52 | 1578 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); |
01ac5e34 MZ |
1579 | return ret; |
1580 | } | |
1581 | ||
e1ba0207 CD |
1582 | /** |
1583 | * kvm_vgic_init - Initialize global VGIC state before running any VCPUs | |
1584 | * @kvm: pointer to the kvm struct | |
1585 | * | |
1586 | * Map the virtual CPU interface into the VM before running any VCPUs. We | |
1587 | * can't do this at creation time, because user space must first set the | |
1588 | * virtual CPU interface address in the guest physical address space. Also | |
1589 | * initialize the ITARGETSRn regs to 0 on the emulated distributor. | |
1590 | */ | |
01ac5e34 MZ |
1591 | int kvm_vgic_init(struct kvm *kvm) |
1592 | { | |
1593 | int ret = 0, i; | |
1594 | ||
e1ba0207 CD |
1595 | if (!irqchip_in_kernel(kvm)) |
1596 | return 0; | |
1597 | ||
01ac5e34 MZ |
1598 | mutex_lock(&kvm->lock); |
1599 | ||
1600 | if (vgic_initialized(kvm)) | |
1601 | goto out; | |
1602 | ||
1603 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || | |
1604 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { | |
1605 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
1606 | ret = -ENXIO; | |
1607 | goto out; | |
1608 | } | |
1609 | ||
1610 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, | |
8f186d52 | 1611 | vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE); |
01ac5e34 MZ |
1612 | if (ret) { |
1613 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
1614 | goto out; | |
1615 | } | |
1616 | ||
1617 | for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4) | |
1618 | vgic_set_target_reg(kvm, 0, i); | |
1619 | ||
1620 | kvm->arch.vgic.ready = true; | |
1621 | out: | |
1622 | mutex_unlock(&kvm->lock); | |
1623 | return ret; | |
1624 | } | |
1625 | ||
1626 | int kvm_vgic_create(struct kvm *kvm) | |
1627 | { | |
7330672b CD |
1628 | int i, vcpu_lock_idx = -1, ret = 0; |
1629 | struct kvm_vcpu *vcpu; | |
01ac5e34 MZ |
1630 | |
1631 | mutex_lock(&kvm->lock); | |
1632 | ||
7330672b | 1633 | if (kvm->arch.vgic.vctrl_base) { |
01ac5e34 MZ |
1634 | ret = -EEXIST; |
1635 | goto out; | |
1636 | } | |
1637 | ||
7330672b CD |
1638 | /* |
1639 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1640 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1641 | * that no other VCPUs are run while we create the vgic. | |
1642 | */ | |
1643 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1644 | if (!mutex_trylock(&vcpu->mutex)) | |
1645 | goto out_unlock; | |
1646 | vcpu_lock_idx = i; | |
1647 | } | |
1648 | ||
1649 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1650 | if (vcpu->arch.has_run_once) { | |
1651 | ret = -EBUSY; | |
1652 | goto out_unlock; | |
1653 | } | |
1654 | } | |
1655 | ||
01ac5e34 | 1656 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1657 | kvm->arch.vgic.in_kernel = true; |
8f186d52 | 1658 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1659 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1660 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
1661 | ||
7330672b CD |
1662 | out_unlock: |
1663 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1664 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1665 | mutex_unlock(&vcpu->mutex); | |
1666 | } | |
1667 | ||
01ac5e34 MZ |
1668 | out: |
1669 | mutex_unlock(&kvm->lock); | |
1670 | return ret; | |
1671 | } | |
1672 | ||
330690cd CD |
1673 | static bool vgic_ioaddr_overlap(struct kvm *kvm) |
1674 | { | |
1675 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1676 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1677 | ||
1678 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1679 | return 0; | |
1680 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1681 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1682 | return -EBUSY; | |
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1687 | phys_addr_t addr, phys_addr_t size) | |
1688 | { | |
1689 | int ret; | |
1690 | ||
ce01e4e8 CD |
1691 | if (addr & ~KVM_PHYS_MASK) |
1692 | return -E2BIG; | |
1693 | ||
1694 | if (addr & (SZ_4K - 1)) | |
1695 | return -EINVAL; | |
1696 | ||
330690cd CD |
1697 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1698 | return -EEXIST; | |
1699 | if (addr + size < addr) | |
1700 | return -EINVAL; | |
1701 | ||
30c21170 | 1702 | *ioaddr = addr; |
330690cd CD |
1703 | ret = vgic_ioaddr_overlap(kvm); |
1704 | if (ret) | |
30c21170 HW |
1705 | *ioaddr = VGIC_ADDR_UNDEF; |
1706 | ||
330690cd CD |
1707 | return ret; |
1708 | } | |
1709 | ||
ce01e4e8 CD |
1710 | /** |
1711 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1712 | * @kvm: pointer to the vm struct | |
1713 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX | |
1714 | * @addr: pointer to address value | |
1715 | * @write: if true set the address in the VM address space, if false read the | |
1716 | * address | |
1717 | * | |
1718 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1719 | * interface in the VM physical address space. These addresses are properties | |
1720 | * of the emulated core/SoC and therefore user space initially knows this | |
1721 | * information. | |
1722 | */ | |
1723 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1724 | { |
1725 | int r = 0; | |
1726 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
1727 | ||
330690cd CD |
1728 | mutex_lock(&kvm->lock); |
1729 | switch (type) { | |
1730 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ce01e4e8 CD |
1731 | if (write) { |
1732 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, | |
1733 | *addr, KVM_VGIC_V2_DIST_SIZE); | |
1734 | } else { | |
1735 | *addr = vgic->vgic_dist_base; | |
1736 | } | |
330690cd CD |
1737 | break; |
1738 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ce01e4e8 CD |
1739 | if (write) { |
1740 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, | |
1741 | *addr, KVM_VGIC_V2_CPU_SIZE); | |
1742 | } else { | |
1743 | *addr = vgic->vgic_cpu_base; | |
1744 | } | |
330690cd CD |
1745 | break; |
1746 | default: | |
1747 | r = -ENODEV; | |
1748 | } | |
1749 | ||
1750 | mutex_unlock(&kvm->lock); | |
1751 | return r; | |
1752 | } | |
7330672b | 1753 | |
c07a0191 CD |
1754 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
1755 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1756 | { | |
fa20f5ae | 1757 | bool updated = false; |
beee38b9 MZ |
1758 | struct vgic_vmcr vmcr; |
1759 | u32 *vmcr_field; | |
1760 | u32 reg; | |
1761 | ||
1762 | vgic_get_vmcr(vcpu, &vmcr); | |
fa20f5ae CD |
1763 | |
1764 | switch (offset & ~0x3) { | |
1765 | case GIC_CPU_CTRL: | |
beee38b9 | 1766 | vmcr_field = &vmcr.ctlr; |
fa20f5ae CD |
1767 | break; |
1768 | case GIC_CPU_PRIMASK: | |
beee38b9 | 1769 | vmcr_field = &vmcr.pmr; |
fa20f5ae CD |
1770 | break; |
1771 | case GIC_CPU_BINPOINT: | |
beee38b9 | 1772 | vmcr_field = &vmcr.bpr; |
fa20f5ae CD |
1773 | break; |
1774 | case GIC_CPU_ALIAS_BINPOINT: | |
beee38b9 | 1775 | vmcr_field = &vmcr.abpr; |
fa20f5ae | 1776 | break; |
beee38b9 MZ |
1777 | default: |
1778 | BUG(); | |
fa20f5ae CD |
1779 | } |
1780 | ||
1781 | if (!mmio->is_write) { | |
beee38b9 | 1782 | reg = *vmcr_field; |
fa20f5ae CD |
1783 | mmio_data_write(mmio, ~0, reg); |
1784 | } else { | |
1785 | reg = mmio_data_read(mmio, ~0); | |
beee38b9 MZ |
1786 | if (reg != *vmcr_field) { |
1787 | *vmcr_field = reg; | |
1788 | vgic_set_vmcr(vcpu, &vmcr); | |
fa20f5ae | 1789 | updated = true; |
beee38b9 | 1790 | } |
fa20f5ae CD |
1791 | } |
1792 | return updated; | |
1793 | } | |
1794 | ||
1795 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, | |
1796 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1797 | { | |
1798 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); | |
c07a0191 CD |
1799 | } |
1800 | ||
fa20f5ae CD |
1801 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
1802 | struct kvm_exit_mmio *mmio, | |
1803 | phys_addr_t offset) | |
1804 | { | |
1805 | u32 reg; | |
1806 | ||
1807 | if (mmio->is_write) | |
1808 | return false; | |
1809 | ||
1810 | /* GICC_IIDR */ | |
1811 | reg = (PRODUCT_ID_KVM << 20) | | |
1812 | (GICC_ARCH_VERSION_V2 << 16) | | |
1813 | (IMPLEMENTER_ARM << 0); | |
1814 | mmio_data_write(mmio, ~0, reg); | |
1815 | return false; | |
1816 | } | |
1817 | ||
1818 | /* | |
1819 | * CPU Interface Register accesses - these are not accessed by the VM, but by | |
1820 | * user space for saving and restoring VGIC state. | |
1821 | */ | |
c07a0191 CD |
1822 | static const struct mmio_range vgic_cpu_ranges[] = { |
1823 | { | |
1824 | .base = GIC_CPU_CTRL, | |
1825 | .len = 12, | |
1826 | .handle_mmio = handle_cpu_mmio_misc, | |
1827 | }, | |
1828 | { | |
1829 | .base = GIC_CPU_ALIAS_BINPOINT, | |
1830 | .len = 4, | |
fa20f5ae | 1831 | .handle_mmio = handle_mmio_abpr, |
c07a0191 CD |
1832 | }, |
1833 | { | |
1834 | .base = GIC_CPU_ACTIVEPRIO, | |
1835 | .len = 16, | |
fa20f5ae | 1836 | .handle_mmio = handle_mmio_raz_wi, |
c07a0191 CD |
1837 | }, |
1838 | { | |
1839 | .base = GIC_CPU_IDENT, | |
1840 | .len = 4, | |
fa20f5ae | 1841 | .handle_mmio = handle_cpu_mmio_ident, |
c07a0191 CD |
1842 | }, |
1843 | }; | |
1844 | ||
1845 | static int vgic_attr_regs_access(struct kvm_device *dev, | |
1846 | struct kvm_device_attr *attr, | |
1847 | u32 *reg, bool is_write) | |
1848 | { | |
1849 | const struct mmio_range *r = NULL, *ranges; | |
1850 | phys_addr_t offset; | |
1851 | int ret, cpuid, c; | |
1852 | struct kvm_vcpu *vcpu, *tmp_vcpu; | |
1853 | struct vgic_dist *vgic; | |
1854 | struct kvm_exit_mmio mmio; | |
1855 | ||
1856 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
1857 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> | |
1858 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; | |
1859 | ||
1860 | mutex_lock(&dev->kvm->lock); | |
1861 | ||
1862 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { | |
1863 | ret = -EINVAL; | |
1864 | goto out; | |
1865 | } | |
1866 | ||
1867 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); | |
1868 | vgic = &dev->kvm->arch.vgic; | |
1869 | ||
1870 | mmio.len = 4; | |
1871 | mmio.is_write = is_write; | |
1872 | if (is_write) | |
1873 | mmio_data_write(&mmio, ~0, *reg); | |
1874 | switch (attr->group) { | |
1875 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1876 | mmio.phys_addr = vgic->vgic_dist_base + offset; | |
1877 | ranges = vgic_dist_ranges; | |
1878 | break; | |
1879 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
1880 | mmio.phys_addr = vgic->vgic_cpu_base + offset; | |
1881 | ranges = vgic_cpu_ranges; | |
1882 | break; | |
1883 | default: | |
1884 | BUG(); | |
1885 | } | |
1886 | r = find_matching_range(ranges, &mmio, offset); | |
1887 | ||
1888 | if (unlikely(!r || !r->handle_mmio)) { | |
1889 | ret = -ENXIO; | |
1890 | goto out; | |
1891 | } | |
1892 | ||
1893 | ||
1894 | spin_lock(&vgic->lock); | |
1895 | ||
1896 | /* | |
1897 | * Ensure that no other VCPU is running by checking the vcpu->cpu | |
1898 | * field. If no other VPCUs are running we can safely access the VGIC | |
1899 | * state, because even if another VPU is run after this point, that | |
1900 | * VCPU will not touch the vgic state, because it will block on | |
1901 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). | |
1902 | */ | |
1903 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { | |
1904 | if (unlikely(tmp_vcpu->cpu != -1)) { | |
1905 | ret = -EBUSY; | |
1906 | goto out_vgic_unlock; | |
1907 | } | |
1908 | } | |
1909 | ||
cbd333a4 CD |
1910 | /* |
1911 | * Move all pending IRQs from the LRs on all VCPUs so the pending | |
1912 | * state can be properly represented in the register state accessible | |
1913 | * through this API. | |
1914 | */ | |
1915 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) | |
1916 | vgic_unqueue_irqs(tmp_vcpu); | |
1917 | ||
c07a0191 CD |
1918 | offset -= r->base; |
1919 | r->handle_mmio(vcpu, &mmio, offset); | |
1920 | ||
1921 | if (!is_write) | |
1922 | *reg = mmio_data_read(&mmio, ~0); | |
1923 | ||
1924 | ret = 0; | |
1925 | out_vgic_unlock: | |
1926 | spin_unlock(&vgic->lock); | |
1927 | out: | |
1928 | mutex_unlock(&dev->kvm->lock); | |
1929 | return ret; | |
1930 | } | |
1931 | ||
7330672b CD |
1932 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
1933 | { | |
ce01e4e8 CD |
1934 | int r; |
1935 | ||
1936 | switch (attr->group) { | |
1937 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1938 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1939 | u64 addr; | |
1940 | unsigned long type = (unsigned long)attr->attr; | |
1941 | ||
1942 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
1943 | return -EFAULT; | |
1944 | ||
1945 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
1946 | return (r == -ENODEV) ? -ENXIO : r; | |
1947 | } | |
c07a0191 CD |
1948 | |
1949 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1950 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
1951 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1952 | u32 reg; | |
1953 | ||
1954 | if (get_user(reg, uaddr)) | |
1955 | return -EFAULT; | |
1956 | ||
1957 | return vgic_attr_regs_access(dev, attr, ®, true); | |
1958 | } | |
1959 | ||
ce01e4e8 CD |
1960 | } |
1961 | ||
7330672b CD |
1962 | return -ENXIO; |
1963 | } | |
1964 | ||
1965 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1966 | { | |
ce01e4e8 CD |
1967 | int r = -ENXIO; |
1968 | ||
1969 | switch (attr->group) { | |
1970 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1971 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1972 | u64 addr; | |
1973 | unsigned long type = (unsigned long)attr->attr; | |
1974 | ||
1975 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
1976 | if (r) | |
1977 | return (r == -ENODEV) ? -ENXIO : r; | |
1978 | ||
1979 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
1980 | return -EFAULT; | |
c07a0191 CD |
1981 | break; |
1982 | } | |
1983 | ||
1984 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1985 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
1986 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1987 | u32 reg = 0; | |
1988 | ||
1989 | r = vgic_attr_regs_access(dev, attr, ®, false); | |
1990 | if (r) | |
1991 | return r; | |
1992 | r = put_user(reg, uaddr); | |
1993 | break; | |
ce01e4e8 | 1994 | } |
c07a0191 | 1995 | |
ce01e4e8 CD |
1996 | } |
1997 | ||
1998 | return r; | |
7330672b CD |
1999 | } |
2000 | ||
c07a0191 CD |
2001 | static int vgic_has_attr_regs(const struct mmio_range *ranges, |
2002 | phys_addr_t offset) | |
2003 | { | |
2004 | struct kvm_exit_mmio dev_attr_mmio; | |
2005 | ||
2006 | dev_attr_mmio.len = 4; | |
2007 | if (find_matching_range(ranges, &dev_attr_mmio, offset)) | |
2008 | return 0; | |
2009 | else | |
2010 | return -ENXIO; | |
2011 | } | |
2012 | ||
7330672b CD |
2013 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2014 | { | |
c07a0191 CD |
2015 | phys_addr_t offset; |
2016 | ||
ce01e4e8 CD |
2017 | switch (attr->group) { |
2018 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
2019 | switch (attr->attr) { | |
2020 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
2021 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
2022 | return 0; | |
2023 | } | |
2024 | break; | |
c07a0191 CD |
2025 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
2026 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2027 | return vgic_has_attr_regs(vgic_dist_ranges, offset); | |
2028 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2029 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2030 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); | |
ce01e4e8 | 2031 | } |
7330672b CD |
2032 | return -ENXIO; |
2033 | } | |
2034 | ||
2035 | static void vgic_destroy(struct kvm_device *dev) | |
2036 | { | |
2037 | kfree(dev); | |
2038 | } | |
2039 | ||
2040 | static int vgic_create(struct kvm_device *dev, u32 type) | |
2041 | { | |
2042 | return kvm_vgic_create(dev->kvm); | |
2043 | } | |
2044 | ||
2045 | struct kvm_device_ops kvm_arm_vgic_v2_ops = { | |
2046 | .name = "kvm-arm-vgic", | |
2047 | .create = vgic_create, | |
2048 | .destroy = vgic_destroy, | |
2049 | .set_attr = vgic_set_attr, | |
2050 | .get_attr = vgic_get_attr, | |
2051 | .has_attr = vgic_has_attr, | |
2052 | }; |