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KVM: ARM: vgic: abstract EISR bitmap access
[deliverable/linux.git] / virt / kvm / arm / vgic.c
CommitLineData
1a89dd91
MZ		 1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
01ac5e34 19#include <linux/cpu.h>
1a89dd91
MZ		 20#include <linux/kvm.h>
21#include <linux/kvm_host.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
01ac5e34
MZ		 24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
2a2f3e26 27#include <linux/uaccess.h>
01ac5e34
MZ		 28
29#include <linux/irqchip/arm-gic.h>
30
1a89dd91 31#include <asm/kvm_emulate.h>
01ac5e34
MZ		 32#include <asm/kvm_arm.h>
33#include <asm/kvm_mmu.h>
1a89dd91 34
b47ef92a
MZ		 35/*
36 * How the whole thing works (courtesy of Christoffer Dall):
37 *
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
45 * recalculated
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_state & dist->irq_enable
49 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
57 *
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
61 *
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_active is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_active. This allow the
69 * interrupt line to be sampled again.
70 */
71
330690cd
CD		 72#define VGIC_ADDR_UNDEF (-1)
73#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
74
fa20f5ae
CD		 75#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76#define IMPLEMENTER_ARM 0x43b
77#define GICC_ARCH_VERSION_V2 0x2
78
01ac5e34
MZ		 79/* Physical address of vgic virtual cpu interface */
80static phys_addr_t vgic_vcpu_base;
81
82/* Virtual control interface base address */
83static void __iomem *vgic_vctrl_base;
84
85static struct device_node *vgic_node;
86
1a89dd91
MZ		 87#define ACCESS_READ_VALUE (1 << 0)
88#define ACCESS_READ_RAZ (0 << 0)
89#define ACCESS_READ_MASK(x) ((x) & (1 << 0))
90#define ACCESS_WRITE_IGNORED (0 << 1)
91#define ACCESS_WRITE_SETBIT (1 << 1)
92#define ACCESS_WRITE_CLEARBIT (2 << 1)
93#define ACCESS_WRITE_VALUE (3 << 1)
94#define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
95
a1fcb44e 96static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
8d5c6b06 97static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
b47ef92a 98static void vgic_update_state(struct kvm *kvm);
5863c2ce 99static void vgic_kick_vcpus(struct kvm *kvm);
b47ef92a 100static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
8d5c6b06
MZ		 101static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
102static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
01ac5e34
MZ		 103static u32 vgic_nr_lr;
104
105static unsigned int vgic_maint_irq;
b47ef92a
MZ		 106
107static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
108 int cpuid, u32 offset)
109{
110 offset >>= 2;
111 if (!offset)
112 return x->percpu[cpuid].reg;
113 else
114 return x->shared.reg + offset - 1;
115}
116
117static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
118 int cpuid, int irq)
119{
120 if (irq < VGIC_NR_PRIVATE_IRQS)
121 return test_bit(irq, x->percpu[cpuid].reg_ul);
122
123 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
124}
125
126static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
127 int irq, int val)
128{
129 unsigned long *reg;
130
131 if (irq < VGIC_NR_PRIVATE_IRQS) {
132 reg = x->percpu[cpuid].reg_ul;
133 } else {
134 reg = x->shared.reg_ul;
135 irq -= VGIC_NR_PRIVATE_IRQS;
136 }
137
138 if (val)
139 set_bit(irq, reg);
140 else
141 clear_bit(irq, reg);
142}
143
144static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
145{
146 if (unlikely(cpuid >= VGIC_MAX_CPUS))
147 return NULL;
148 return x->percpu[cpuid].reg_ul;
149}
150
151static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
152{
153 return x->shared.reg_ul;
154}
155
156static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
157{
158 offset >>= 2;
159 BUG_ON(offset > (VGIC_NR_IRQS / 4));
8d98915b 160 if (offset < 8)
b47ef92a
MZ		 161 return x->percpu[cpuid] + offset;
162 else
163 return x->shared + offset - 8;
164}
165
166#define VGIC_CFG_LEVEL 0
167#define VGIC_CFG_EDGE 1
168
169static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
170{
171 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
172 int irq_val;
173
174 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
175 return irq_val == VGIC_CFG_EDGE;
176}
177
178static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
179{
180 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
181
182 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
183}
184
9d949dce
MZ		 185static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
186{
187 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
188
189 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
190}
191
192static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
193{
194 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
195
196 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
197}
198
199static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
200{
201 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
202
203 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
204}
205
206static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
207{
208 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
209
210 return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
211}
212
b47ef92a
MZ		 213static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
214{
215 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
216
217 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
218}
219
220static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
221{
222 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
223
224 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
225}
226
227static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
228{
229 if (irq < VGIC_NR_PRIVATE_IRQS)
230 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
231 else
232 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
233 vcpu->arch.vgic_cpu.pending_shared);
234}
235
236static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
237{
238 if (irq < VGIC_NR_PRIVATE_IRQS)
239 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
240 else
241 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
242 vcpu->arch.vgic_cpu.pending_shared);
243}
244
1a89dd91
MZ		 245static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
246{
247 return *((u32 *)mmio->data) & mask;
248}
249
250static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
251{
252 *((u32 *)mmio->data) = value & mask;
253}
254
255/**
256 * vgic_reg_access - access vgic register
257 * @mmio: pointer to the data describing the mmio access
258 * @reg: pointer to the virtual backing of vgic distributor data
259 * @offset: least significant 2 bits used for word offset
260 * @mode: ACCESS_ mode (see defines above)
261 *
262 * Helper to make vgic register access easier using one of the access
263 * modes defined for vgic register access
264 * (read,raz,write-ignored,setbit,clearbit,write)
265 */
266static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
267 phys_addr_t offset, int mode)
268{
269 int word_offset = (offset & 3) * 8;
270 u32 mask = (1UL << (mmio->len * 8)) - 1;
271 u32 regval;
272
273 /*
274 * Any alignment fault should have been delivered to the guest
275 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
276 */
277
278 if (reg) {
279 regval = *reg;
280 } else {
281 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
282 regval = 0;
283 }
284
285 if (mmio->is_write) {
286 u32 data = mmio_data_read(mmio, mask) << word_offset;
287 switch (ACCESS_WRITE_MASK(mode)) {
288 case ACCESS_WRITE_IGNORED:
289 return;
290
291 case ACCESS_WRITE_SETBIT:
292 regval |= data;
293 break;
294
295 case ACCESS_WRITE_CLEARBIT:
296 regval &= ~data;
297 break;
298
299 case ACCESS_WRITE_VALUE:
300 regval = (regval & ~(mask << word_offset)) | data;
301 break;
302 }
303 *reg = regval;
304 } else {
305 switch (ACCESS_READ_MASK(mode)) {
306 case ACCESS_READ_RAZ:
307 regval = 0;
308 /* fall through */
309
310 case ACCESS_READ_VALUE:
311 mmio_data_write(mmio, mask, regval >> word_offset);
312 }
313 }
314}
315
b47ef92a
MZ		 316static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
317 struct kvm_exit_mmio *mmio, phys_addr_t offset)
318{
319 u32 reg;
320 u32 word_offset = offset & 3;
321
322 switch (offset & ~3) {
fa20f5ae 323 case 0: /* GICD_CTLR */
b47ef92a
MZ		 324 reg = vcpu->kvm->arch.vgic.enabled;
325 vgic_reg_access(mmio, &reg, word_offset,
326 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
327 if (mmio->is_write) {
328 vcpu->kvm->arch.vgic.enabled = reg & 1;
329 vgic_update_state(vcpu->kvm);
330 return true;
331 }
332 break;
333
fa20f5ae 334 case 4: /* GICD_TYPER */
b47ef92a
MZ		 335 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
336 reg |= (VGIC_NR_IRQS >> 5) - 1;
337 vgic_reg_access(mmio, &reg, word_offset,
338 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
339 break;
340
fa20f5ae
CD		 341 case 8: /* GICD_IIDR */
342 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
b47ef92a
MZ		 343 vgic_reg_access(mmio, &reg, word_offset,
344 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
345 break;
346 }
347
348 return false;
349}
350
351static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
352 struct kvm_exit_mmio *mmio, phys_addr_t offset)
353{
354 vgic_reg_access(mmio, NULL, offset,
355 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
356 return false;
357}
358
359static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
360 struct kvm_exit_mmio *mmio,
361 phys_addr_t offset)
362{
363 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
364 vcpu->vcpu_id, offset);
365 vgic_reg_access(mmio, reg, offset,
366 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
367 if (mmio->is_write) {
368 vgic_update_state(vcpu->kvm);
369 return true;
370 }
371
372 return false;
373}
374
375static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
376 struct kvm_exit_mmio *mmio,
377 phys_addr_t offset)
378{
379 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
380 vcpu->vcpu_id, offset);
381 vgic_reg_access(mmio, reg, offset,
382 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
383 if (mmio->is_write) {
384 if (offset < 4) /* Force SGI enabled */
385 *reg |= 0xffff;
a1fcb44e 386 vgic_retire_disabled_irqs(vcpu);
b47ef92a
MZ		 387 vgic_update_state(vcpu->kvm);
388 return true;
389 }
390
391 return false;
392}
393
394static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
395 struct kvm_exit_mmio *mmio,
396 phys_addr_t offset)
397{
398 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
399 vcpu->vcpu_id, offset);
400 vgic_reg_access(mmio, reg, offset,
401 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
402 if (mmio->is_write) {
403 vgic_update_state(vcpu->kvm);
404 return true;
405 }
406
407 return false;
408}
409
410static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
411 struct kvm_exit_mmio *mmio,
412 phys_addr_t offset)
413{
414 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
415 vcpu->vcpu_id, offset);
416 vgic_reg_access(mmio, reg, offset,
417 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
418 if (mmio->is_write) {
419 vgic_update_state(vcpu->kvm);
420 return true;
421 }
422
423 return false;
424}
425
426static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
427 struct kvm_exit_mmio *mmio,
428 phys_addr_t offset)
429{
430 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
431 vcpu->vcpu_id, offset);
432 vgic_reg_access(mmio, reg, offset,
433 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
434 return false;
435}
436
437#define GICD_ITARGETSR_SIZE 32
438#define GICD_CPUTARGETS_BITS 8
439#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
440static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
441{
442 struct vgic_dist *dist = &kvm->arch.vgic;
986af8e0 443 int i;
b47ef92a
MZ		 444 u32 val = 0;
445
446 irq -= VGIC_NR_PRIVATE_IRQS;
447
986af8e0
MZ		 448 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
449 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
b47ef92a
MZ		 450
451 return val;
452}
453
454static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
455{
456 struct vgic_dist *dist = &kvm->arch.vgic;
457 struct kvm_vcpu *vcpu;
458 int i, c;
459 unsigned long *bmap;
460 u32 target;
461
462 irq -= VGIC_NR_PRIVATE_IRQS;
463
464 /*
465 * Pick the LSB in each byte. This ensures we target exactly
466 * one vcpu per IRQ. If the byte is null, assume we target
467 * CPU0.
468 */
469 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
470 int shift = i * GICD_CPUTARGETS_BITS;
471 target = ffs((val >> shift) & 0xffU);
472 target = target ? (target - 1) : 0;
473 dist->irq_spi_cpu[irq + i] = target;
474 kvm_for_each_vcpu(c, vcpu, kvm) {
475 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
476 if (c == target)
477 set_bit(irq + i, bmap);
478 else
479 clear_bit(irq + i, bmap);
480 }
481 }
482}
483
484static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
485 struct kvm_exit_mmio *mmio,
486 phys_addr_t offset)
487{
488 u32 reg;
489
490 /* We treat the banked interrupts targets as read-only */
491 if (offset < 32) {
492 u32 roreg = 1 << vcpu->vcpu_id;
493 roreg |= roreg << 8;
494 roreg |= roreg << 16;
495
496 vgic_reg_access(mmio, &roreg, offset,
497 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
498 return false;
499 }
500
501 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
502 vgic_reg_access(mmio, &reg, offset,
503 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
504 if (mmio->is_write) {
505 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
506 vgic_update_state(vcpu->kvm);
507 return true;
508 }
509
510 return false;
511}
512
513static u32 vgic_cfg_expand(u16 val)
514{
515 u32 res = 0;
516 int i;
517
518 /*
519 * Turn a 16bit value like abcd...mnop into a 32bit word
520 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
521 */
522 for (i = 0; i < 16; i++)
523 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
524
525 return res;
526}
527
528static u16 vgic_cfg_compress(u32 val)
529{
530 u16 res = 0;
531 int i;
532
533 /*
534 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
535 * abcd...mnop which is what we really care about.
536 */
537 for (i = 0; i < 16; i++)
538 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
539
540 return res;
541}
542
543/*
544 * The distributor uses 2 bits per IRQ for the CFG register, but the
545 * LSB is always 0. As such, we only keep the upper bit, and use the
546 * two above functions to compress/expand the bits
547 */
548static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
549 struct kvm_exit_mmio *mmio, phys_addr_t offset)
550{
551 u32 val;
6545eae3
MZ		 552 u32 *reg;
553
6545eae3 554 reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
f2ae85b2 555 vcpu->vcpu_id, offset >> 1);
6545eae3 556
f2ae85b2 557 if (offset & 4)
b47ef92a
MZ		 558 val = *reg >> 16;
559 else
560 val = *reg & 0xffff;
561
562 val = vgic_cfg_expand(val);
563 vgic_reg_access(mmio, &val, offset,
564 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
565 if (mmio->is_write) {
f2ae85b2 566 if (offset < 8) {
b47ef92a
MZ		 567 *reg = ~0U; /* Force PPIs/SGIs to 1 */
568 return false;
569 }
570
571 val = vgic_cfg_compress(val);
f2ae85b2 572 if (offset & 4) {
b47ef92a
MZ		 573 *reg &= 0xffff;
574 *reg |= val << 16;
575 } else {
576 *reg &= 0xffff << 16;
577 *reg |= val;
578 }
579 }
580
581 return false;
582}
583
584static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
585 struct kvm_exit_mmio *mmio, phys_addr_t offset)
586{
587 u32 reg;
588 vgic_reg_access(mmio, &reg, offset,
589 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
590 if (mmio->is_write) {
591 vgic_dispatch_sgi(vcpu, reg);
592 vgic_update_state(vcpu->kvm);
593 return true;
594 }
595
596 return false;
597}
598
cbd333a4
CD		 599/**
600 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
601 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
602 *
603 * Move any pending IRQs that have already been assigned to LRs back to the
604 * emulated distributor state so that the complete emulated state can be read
605 * from the main emulation structures without investigating the LRs.
606 *
607 * Note that IRQs in the active state in the LRs get their pending state moved
608 * to the distributor but the active state stays in the LRs, because we don't
609 * track the active state on the distributor side.
610 */
611static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
612{
613 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
614 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
615 int vcpu_id = vcpu->vcpu_id;
8d5c6b06 616 int i;
cbd333a4
CD		 617
618 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
8d5c6b06 619 struct vgic_lr lr = vgic_get_lr(vcpu, i);
cbd333a4
CD		 620
621 /*
622 * There are three options for the state bits:
623 *
624 * 01: pending
625 * 10: active
626 * 11: pending and active
627 *
628 * If the LR holds only an active interrupt (not pending) then
629 * just leave it alone.
630 */
8d5c6b06 631 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
cbd333a4
CD		 632 continue;
633
634 /*
635 * Reestablish the pending state on the distributor and the
636 * CPU interface. It may have already been pending, but that
637 * is fine, then we are only setting a few bits that were
638 * already set.
639 */
8d5c6b06
MZ		 640 vgic_dist_irq_set(vcpu, lr.irq);
641 if (lr.irq < VGIC_NR_SGIS)
642 dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source;
643 lr.state &= ~LR_STATE_PENDING;
644 vgic_set_lr(vcpu, i, lr);
cbd333a4
CD		 645
646 /*
647 * If there's no state left on the LR (it could still be
648 * active), then the LR does not hold any useful info and can
649 * be marked as free for other use.
650 */
8d5c6b06
MZ		 651 if (!(lr.state & LR_STATE_MASK))
652 vgic_retire_lr(i, lr.irq, vcpu);
cbd333a4
CD		 653
654 /* Finally update the VGIC state. */
655 vgic_update_state(vcpu->kvm);
656 }
657}
658
90a5355e
CD		 659/* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
660static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
661 struct kvm_exit_mmio *mmio,
662 phys_addr_t offset)
c07a0191 663{
90a5355e
CD		 664 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
665 int sgi;
666 int min_sgi = (offset & ~0x3) * 4;
667 int max_sgi = min_sgi + 3;
668 int vcpu_id = vcpu->vcpu_id;
669 u32 reg = 0;
670
671 /* Copy source SGIs from distributor side */
672 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
673 int shift = 8 * (sgi - min_sgi);
674 reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift;
675 }
676
677 mmio_data_write(mmio, ~0, reg);
c07a0191
CD		 678 return false;
679}
680
90a5355e
CD		 681static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
682 struct kvm_exit_mmio *mmio,
683 phys_addr_t offset, bool set)
684{
685 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
686 int sgi;
687 int min_sgi = (offset & ~0x3) * 4;
688 int max_sgi = min_sgi + 3;
689 int vcpu_id = vcpu->vcpu_id;
690 u32 reg;
691 bool updated = false;
692
693 reg = mmio_data_read(mmio, ~0);
694
695 /* Clear pending SGIs on the distributor */
696 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
697 u8 mask = reg >> (8 * (sgi - min_sgi));
698 if (set) {
699 if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask)
700 updated = true;
701 dist->irq_sgi_sources[vcpu_id][sgi] |= mask;
702 } else {
703 if (dist->irq_sgi_sources[vcpu_id][sgi] & mask)
704 updated = true;
705 dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask;
706 }
707 }
708
709 if (updated)
710 vgic_update_state(vcpu->kvm);
711
712 return updated;
713}
714
c07a0191
CD		 715static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
716 struct kvm_exit_mmio *mmio,
717 phys_addr_t offset)
718{
90a5355e
CD		 719 if (!mmio->is_write)
720 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
721 else
722 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
723}
724
725static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
726 struct kvm_exit_mmio *mmio,
727 phys_addr_t offset)
728{
729 if (!mmio->is_write)
730 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
731 else
732 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
c07a0191
CD		 733}
734
1a89dd91
MZ		 735/*
736 * I would have liked to use the kvm_bus_io_*() API instead, but it
737 * cannot cope with banked registers (only the VM pointer is passed
738 * around, and we need the vcpu). One of these days, someone please
739 * fix it!
740 */
741struct mmio_range {
742 phys_addr_t base;
743 unsigned long len;
744 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
745 phys_addr_t offset);
746};
747
1006e8cb 748static const struct mmio_range vgic_dist_ranges[] = {
b47ef92a
MZ		 749 {
750 .base = GIC_DIST_CTRL,
751 .len = 12,
752 .handle_mmio = handle_mmio_misc,
753 },
754 {
755 .base = GIC_DIST_IGROUP,
756 .len = VGIC_NR_IRQS / 8,
757 .handle_mmio = handle_mmio_raz_wi,
758 },
759 {
760 .base = GIC_DIST_ENABLE_SET,
761 .len = VGIC_NR_IRQS / 8,
762 .handle_mmio = handle_mmio_set_enable_reg,
763 },
764 {
765 .base = GIC_DIST_ENABLE_CLEAR,
766 .len = VGIC_NR_IRQS / 8,
767 .handle_mmio = handle_mmio_clear_enable_reg,
768 },
769 {
770 .base = GIC_DIST_PENDING_SET,
771 .len = VGIC_NR_IRQS / 8,
772 .handle_mmio = handle_mmio_set_pending_reg,
773 },
774 {
775 .base = GIC_DIST_PENDING_CLEAR,
776 .len = VGIC_NR_IRQS / 8,
777 .handle_mmio = handle_mmio_clear_pending_reg,
778 },
779 {
780 .base = GIC_DIST_ACTIVE_SET,
781 .len = VGIC_NR_IRQS / 8,
782 .handle_mmio = handle_mmio_raz_wi,
783 },
784 {
785 .base = GIC_DIST_ACTIVE_CLEAR,
786 .len = VGIC_NR_IRQS / 8,
787 .handle_mmio = handle_mmio_raz_wi,
788 },
789 {
790 .base = GIC_DIST_PRI,
791 .len = VGIC_NR_IRQS,
792 .handle_mmio = handle_mmio_priority_reg,
793 },
794 {
795 .base = GIC_DIST_TARGET,
796 .len = VGIC_NR_IRQS,
797 .handle_mmio = handle_mmio_target_reg,
798 },
799 {
800 .base = GIC_DIST_CONFIG,
801 .len = VGIC_NR_IRQS / 4,
802 .handle_mmio = handle_mmio_cfg_reg,
803 },
804 {
805 .base = GIC_DIST_SOFTINT,
806 .len = 4,
807 .handle_mmio = handle_mmio_sgi_reg,
808 },
c07a0191
CD		 809 {
810 .base = GIC_DIST_SGI_PENDING_CLEAR,
811 .len = VGIC_NR_SGIS,
812 .handle_mmio = handle_mmio_sgi_clear,
813 },
814 {
815 .base = GIC_DIST_SGI_PENDING_SET,
816 .len = VGIC_NR_SGIS,
817 .handle_mmio = handle_mmio_sgi_set,
818 },
1a89dd91
MZ		 819 {}
820};
821
822static const
823struct mmio_range *find_matching_range(const struct mmio_range *ranges,
824 struct kvm_exit_mmio *mmio,
1006e8cb 825 phys_addr_t offset)
1a89dd91
MZ		 826{
827 const struct mmio_range *r = ranges;
1a89dd91
MZ		 828
829 while (r->len) {
1006e8cb
CD		 830 if (offset >= r->base &&
831 (offset + mmio->len) <= (r->base + r->len))
1a89dd91
MZ		 832 return r;
833 r++;
834 }
835
836 return NULL;
837}
838
839/**
840 * vgic_handle_mmio - handle an in-kernel MMIO access
841 * @vcpu: pointer to the vcpu performing the access
842 * @run: pointer to the kvm_run structure
843 * @mmio: pointer to the data describing the access
844 *
845 * returns true if the MMIO access has been performed in kernel space,
846 * and false if it needs to be emulated in user space.
847 */
848bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
849 struct kvm_exit_mmio *mmio)
850{
b47ef92a
MZ		 851 const struct mmio_range *range;
852 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
853 unsigned long base = dist->vgic_dist_base;
854 bool updated_state;
855 unsigned long offset;
856
857 if (!irqchip_in_kernel(vcpu->kvm) ||
858 mmio->phys_addr < base ||
859 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
860 return false;
861
862 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
863 if (mmio->len > 4) {
864 kvm_inject_dabt(vcpu, mmio->phys_addr);
865 return true;
866 }
867
1006e8cb
CD		 868 offset = mmio->phys_addr - base;
869 range = find_matching_range(vgic_dist_ranges, mmio, offset);
b47ef92a
MZ		 870 if (unlikely(!range || !range->handle_mmio)) {
871 pr_warn("Unhandled access %d %08llx %d\n",
872 mmio->is_write, mmio->phys_addr, mmio->len);
873 return false;
874 }
875
876 spin_lock(&vcpu->kvm->arch.vgic.lock);
877 offset = mmio->phys_addr - range->base - base;
878 updated_state = range->handle_mmio(vcpu, mmio, offset);
879 spin_unlock(&vcpu->kvm->arch.vgic.lock);
880 kvm_prepare_mmio(run, mmio);
881 kvm_handle_mmio_return(vcpu, run);
882
5863c2ce
MZ		 883 if (updated_state)
884 vgic_kick_vcpus(vcpu->kvm);
885
b47ef92a
MZ		 886 return true;
887}
888
889static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
890{
891 struct kvm *kvm = vcpu->kvm;
892 struct vgic_dist *dist = &kvm->arch.vgic;
893 int nrcpus = atomic_read(&kvm->online_vcpus);
894 u8 target_cpus;
895 int sgi, mode, c, vcpu_id;
896
897 vcpu_id = vcpu->vcpu_id;
898
899 sgi = reg & 0xf;
900 target_cpus = (reg >> 16) & 0xff;
901 mode = (reg >> 24) & 3;
902
903 switch (mode) {
904 case 0:
905 if (!target_cpus)
906 return;
91021a6c 907 break;
b47ef92a
MZ		 908
909 case 1:
910 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
911 break;
912
913 case 2:
914 target_cpus = 1 << vcpu_id;
915 break;
916 }
917
918 kvm_for_each_vcpu(c, vcpu, kvm) {
919 if (target_cpus & 1) {
920 /* Flag the SGI as pending */
921 vgic_dist_irq_set(vcpu, sgi);
922 dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
923 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
924 }
925
926 target_cpus >>= 1;
927 }
928}
929
930static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
931{
9d949dce
MZ		 932 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
933 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
934 unsigned long pending_private, pending_shared;
935 int vcpu_id;
936
937 vcpu_id = vcpu->vcpu_id;
938 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
939 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
940
941 pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
942 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
943 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
944
945 pending = vgic_bitmap_get_shared_map(&dist->irq_state);
946 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
947 bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
948 bitmap_and(pend_shared, pend_shared,
949 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
950 VGIC_NR_SHARED_IRQS);
951
952 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
953 pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
954 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
955 pending_shared < VGIC_NR_SHARED_IRQS);
b47ef92a
MZ		 956}
957
958/*
959 * Update the interrupt state and determine which CPUs have pending
960 * interrupts. Must be called with distributor lock held.
961 */
962static void vgic_update_state(struct kvm *kvm)
963{
964 struct vgic_dist *dist = &kvm->arch.vgic;
965 struct kvm_vcpu *vcpu;
966 int c;
967
968 if (!dist->enabled) {
969 set_bit(0, &dist->irq_pending_on_cpu);
970 return;
971 }
972
973 kvm_for_each_vcpu(c, vcpu, kvm) {
974 if (compute_pending_for_cpu(vcpu)) {
975 pr_debug("CPU%d has pending interrupts\n", c);
976 set_bit(c, &dist->irq_pending_on_cpu);
977 }
978 }
1a89dd91 979}
330690cd 980
8d5c6b06
MZ		 981static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
982{
983 struct vgic_lr lr_desc;
984 u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
985
986 lr_desc.irq = val & GICH_LR_VIRTUALID;
987 if (lr_desc.irq <= 15)
988 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
989 else
990 lr_desc.source = 0;
991 lr_desc.state = 0;
992
993 if (val & GICH_LR_PENDING_BIT)
994 lr_desc.state |= LR_STATE_PENDING;
995 if (val & GICH_LR_ACTIVE_BIT)
996 lr_desc.state |= LR_STATE_ACTIVE;
997 if (val & GICH_LR_EOI)
998 lr_desc.state |= LR_EOI_INT;
999
1000 return lr_desc;
1001}
1002
1003static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
1004 struct vgic_lr lr_desc)
1005{
1006 u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;
1007
1008 if (lr_desc.state & LR_STATE_PENDING)
1009 lr_val |= GICH_LR_PENDING_BIT;
1010 if (lr_desc.state & LR_STATE_ACTIVE)
1011 lr_val |= GICH_LR_ACTIVE_BIT;
1012 if (lr_desc.state & LR_EOI_INT)
1013 lr_val |= GICH_LR_EOI;
1014
1015 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
1016}
1017
69bb2c9f
MZ		 1018static void vgic_v2_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1019 struct vgic_lr lr_desc)
1020{
1021 if (!(lr_desc.state & LR_STATE_MASK))
1022 set_bit(lr, (unsigned long *)vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr);
1023}
1024
1025static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
1026{
1027 u64 val;
1028
1029#if BITS_PER_LONG == 64
1030 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[1];
1031 val <<= 32;
1032 val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[0];
1033#else
1034 val = *(u64 *)vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
1035#endif
1036 return val;
1037}
1038
8d6a0313
MZ		 1039static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
1040{
1041 u64 val;
1042
1043#if BITS_PER_LONG == 64
1044 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[1];
1045 val <<= 32;
1046 val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[0];
1047#else
1048 val = *(u64 *)vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
1049#endif
1050 return val;
1051}
1052
8d5c6b06
MZ		 1053static const struct vgic_ops vgic_ops = {
1054 .get_lr = vgic_v2_get_lr,
1055 .set_lr = vgic_v2_set_lr,
69bb2c9f
MZ		 1056 .sync_lr_elrsr = vgic_v2_sync_lr_elrsr,
1057 .get_elrsr = vgic_v2_get_elrsr,
8d6a0313 1058 .get_eisr = vgic_v2_get_eisr,
8d5c6b06
MZ		 1059};
1060
1061static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1062{
1063 return vgic_ops.get_lr(vcpu, lr);
1064}
1065
1066static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1067 struct vgic_lr vlr)
1068{
1069 vgic_ops.set_lr(vcpu, lr, vlr);
1070}
1071
69bb2c9f
MZ		 1072static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1073 struct vgic_lr vlr)
1074{
1075 vgic_ops.sync_lr_elrsr(vcpu, lr, vlr);
1076}
1077
1078static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1079{
1080 return vgic_ops.get_elrsr(vcpu);
1081}
1082
8d6a0313
MZ		 1083static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1084{
1085 return vgic_ops.get_eisr(vcpu);
1086}
1087
8d5c6b06
MZ		 1088static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1089{
1090 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1091 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1092
1093 vlr.state = 0;
1094 vgic_set_lr(vcpu, lr_nr, vlr);
1095 clear_bit(lr_nr, vgic_cpu->lr_used);
1096 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1097}
a1fcb44e
MZ		 1098
1099/*
1100 * An interrupt may have been disabled after being made pending on the
1101 * CPU interface (the classic case is a timer running while we're
1102 * rebooting the guest - the interrupt would kick as soon as the CPU
1103 * interface gets enabled, with deadly consequences).
1104 *
1105 * The solution is to examine already active LRs, and check the
1106 * interrupt is still enabled. If not, just retire it.
1107 */
1108static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1109{
1110 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1111 int lr;
1112
1113 for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
8d5c6b06 1114 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
a1fcb44e 1115
8d5c6b06
MZ		 1116 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1117 vgic_retire_lr(lr, vlr.irq, vcpu);
1118 if (vgic_irq_is_active(vcpu, vlr.irq))
1119 vgic_irq_clear_active(vcpu, vlr.irq);
a1fcb44e
MZ		 1120 }
1121 }
1122}
1123
9d949dce
MZ		 1124/*
1125 * Queue an interrupt to a CPU virtual interface. Return true on success,
1126 * or false if it wasn't possible to queue it.
1127 */
1128static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1129{
1130 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
8d5c6b06 1131 struct vgic_lr vlr;
9d949dce
MZ		 1132 int lr;
1133
1134 /* Sanitize the input... */
1135 BUG_ON(sgi_source_id & ~7);
1136 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1137 BUG_ON(irq >= VGIC_NR_IRQS);
1138
1139 kvm_debug("Queue IRQ%d\n", irq);
1140
1141 lr = vgic_cpu->vgic_irq_lr_map[irq];
1142
1143 /* Do we have an active interrupt for the same CPUID? */
8d5c6b06
MZ		 1144 if (lr != LR_EMPTY) {
1145 vlr = vgic_get_lr(vcpu, lr);
1146 if (vlr.source == sgi_source_id) {
1147 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1148 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1149 vlr.state |= LR_STATE_PENDING;
1150 vgic_set_lr(vcpu, lr, vlr);
1151 return true;
1152 }
9d949dce
MZ		 1153 }
1154
1155 /* Try to use another LR for this interrupt */
1156 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1157 vgic_cpu->nr_lr);
1158 if (lr >= vgic_cpu->nr_lr)
1159 return false;
1160
1161 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
9d949dce
MZ		 1162 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1163 set_bit(lr, vgic_cpu->lr_used);
1164
8d5c6b06
MZ		 1165 vlr.irq = irq;
1166 vlr.source = sgi_source_id;
1167 vlr.state = LR_STATE_PENDING;
9d949dce 1168 if (!vgic_irq_is_edge(vcpu, irq))
8d5c6b06
MZ		 1169 vlr.state |= LR_EOI_INT;
1170
1171 vgic_set_lr(vcpu, lr, vlr);
9d949dce
MZ		 1172
1173 return true;
1174}
1175
1176static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1177{
1178 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1179 unsigned long sources;
1180 int vcpu_id = vcpu->vcpu_id;
1181 int c;
1182
1183 sources = dist->irq_sgi_sources[vcpu_id][irq];
1184
1185 for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
1186 if (vgic_queue_irq(vcpu, c, irq))
1187 clear_bit(c, &sources);
1188 }
1189
1190 dist->irq_sgi_sources[vcpu_id][irq] = sources;
1191
1192 /*
1193 * If the sources bitmap has been cleared it means that we
1194 * could queue all the SGIs onto link registers (see the
1195 * clear_bit above), and therefore we are done with them in
1196 * our emulated gic and can get rid of them.
1197 */
1198 if (!sources) {
1199 vgic_dist_irq_clear(vcpu, irq);
1200 vgic_cpu_irq_clear(vcpu, irq);
1201 return true;
1202 }
1203
1204 return false;
1205}
1206
1207static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1208{
1209 if (vgic_irq_is_active(vcpu, irq))
1210 return true; /* level interrupt, already queued */
1211
1212 if (vgic_queue_irq(vcpu, 0, irq)) {
1213 if (vgic_irq_is_edge(vcpu, irq)) {
1214 vgic_dist_irq_clear(vcpu, irq);
1215 vgic_cpu_irq_clear(vcpu, irq);
1216 } else {
1217 vgic_irq_set_active(vcpu, irq);
1218 }
1219
1220 return true;
1221 }
1222
1223 return false;
1224}
1225
1226/*
1227 * Fill the list registers with pending interrupts before running the
1228 * guest.
1229 */
1230static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1231{
1232 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1233 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1234 int i, vcpu_id;
1235 int overflow = 0;
1236
1237 vcpu_id = vcpu->vcpu_id;
1238
1239 /*
1240 * We may not have any pending interrupt, or the interrupts
1241 * may have been serviced from another vcpu. In all cases,
1242 * move along.
1243 */
1244 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1245 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1246 goto epilog;
1247 }
1248
1249 /* SGIs */
1250 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1251 if (!vgic_queue_sgi(vcpu, i))
1252 overflow = 1;
1253 }
1254
1255 /* PPIs */
1256 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1257 if (!vgic_queue_hwirq(vcpu, i))
1258 overflow = 1;
1259 }
1260
1261 /* SPIs */
1262 for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
1263 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1264 overflow = 1;
1265 }
1266
1267epilog:
1268 if (overflow) {
eede821d 1269 vgic_cpu->vgic_v2.vgic_hcr |= GICH_HCR_UIE;
9d949dce 1270 } else {
eede821d 1271 vgic_cpu->vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
9d949dce
MZ		 1272 /*
1273 * We're about to run this VCPU, and we've consumed
1274 * everything the distributor had in store for
1275 * us. Claim we don't have anything pending. We'll
1276 * adjust that if needed while exiting.
1277 */
1278 clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
1279 }
1280}
1281
1282static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1283{
1284 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1285 bool level_pending = false;
1286
eede821d 1287 kvm_debug("MISR = %08x\n", vgic_cpu->vgic_v2.vgic_misr);
9d949dce 1288
eede821d 1289 if (vgic_cpu->vgic_v2.vgic_misr & GICH_MISR_EOI) {
9d949dce
MZ		 1290 /*
1291 * Some level interrupts have been EOIed. Clear their
1292 * active bit.
1293 */
8d6a0313
MZ		 1294 u64 eisr = vgic_get_eisr(vcpu);
1295 unsigned long *eisr_ptr = (unsigned long *)&eisr;
8d5c6b06 1296 int lr;
9d949dce 1297
8d6a0313 1298 for_each_set_bit(lr, eisr_ptr, vgic_cpu->nr_lr) {
8d5c6b06 1299 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
9d949dce 1300
8d5c6b06
MZ		 1301 vgic_irq_clear_active(vcpu, vlr.irq);
1302 WARN_ON(vlr.state & LR_STATE_MASK);
1303 vlr.state = 0;
1304 vgic_set_lr(vcpu, lr, vlr);
9d949dce
MZ		 1305
1306 /* Any additional pending interrupt? */
8d5c6b06
MZ		 1307 if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) {
1308 vgic_cpu_irq_set(vcpu, vlr.irq);
9d949dce
MZ		 1309 level_pending = true;
1310 } else {
8d5c6b06 1311 vgic_cpu_irq_clear(vcpu, vlr.irq);
9d949dce 1312 }
75da01e1
MZ		 1313
1314 /*
1315 * Despite being EOIed, the LR may not have
1316 * been marked as empty.
1317 */
69bb2c9f 1318 vgic_sync_lr_elrsr(vcpu, lr, vlr);
9d949dce
MZ		 1319 }
1320 }
1321
eede821d
MZ		 1322 if (vgic_cpu->vgic_v2.vgic_misr & GICH_MISR_U)
1323 vgic_cpu->vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
9d949dce
MZ		 1324
1325 return level_pending;
1326}
1327
1328/*
33c83cb3
MZ		 1329 * Sync back the VGIC state after a guest run. The distributor lock is
1330 * needed so we don't get preempted in the middle of the state processing.
9d949dce
MZ		 1331 */
1332static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1333{
1334 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1335 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
69bb2c9f
MZ		 1336 u64 elrsr;
1337 unsigned long *elrsr_ptr;
9d949dce
MZ		 1338 int lr, pending;
1339 bool level_pending;
1340
1341 level_pending = vgic_process_maintenance(vcpu);
69bb2c9f
MZ		 1342 elrsr = vgic_get_elrsr(vcpu);
1343 elrsr_ptr = (unsigned long *)&elrsr;
9d949dce
MZ		 1344
1345 /* Clear mappings for empty LRs */
69bb2c9f 1346 for_each_set_bit(lr, elrsr_ptr, vgic_cpu->nr_lr) {
8d5c6b06 1347 struct vgic_lr vlr;
9d949dce
MZ		 1348
1349 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1350 continue;
1351
8d5c6b06 1352 vlr = vgic_get_lr(vcpu, lr);
9d949dce 1353
8d5c6b06
MZ		 1354 BUG_ON(vlr.irq >= VGIC_NR_IRQS);
1355 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
9d949dce
MZ		 1356 }
1357
1358 /* Check if we still have something up our sleeve... */
69bb2c9f 1359 pending = find_first_zero_bit(elrsr_ptr, vgic_cpu->nr_lr);
9d949dce
MZ		 1360 if (level_pending || pending < vgic_cpu->nr_lr)
1361 set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1362}
1363
1364void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1365{
1366 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1367
1368 if (!irqchip_in_kernel(vcpu->kvm))
1369 return;
1370
1371 spin_lock(&dist->lock);
1372 __kvm_vgic_flush_hwstate(vcpu);
1373 spin_unlock(&dist->lock);
1374}
1375
1376void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1377{
33c83cb3
MZ		 1378 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1379
9d949dce
MZ		 1380 if (!irqchip_in_kernel(vcpu->kvm))
1381 return;
1382
33c83cb3 1383 spin_lock(&dist->lock);
9d949dce 1384 __kvm_vgic_sync_hwstate(vcpu);
33c83cb3 1385 spin_unlock(&dist->lock);
9d949dce
MZ		 1386}
1387
1388int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1389{
1390 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1391
1392 if (!irqchip_in_kernel(vcpu->kvm))
1393 return 0;
1394
1395 return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1396}
1397
5863c2ce
MZ		 1398static void vgic_kick_vcpus(struct kvm *kvm)
1399{
1400 struct kvm_vcpu *vcpu;
1401 int c;
1402
1403 /*
1404 * We've injected an interrupt, time to find out who deserves
1405 * a good kick...
1406 */
1407 kvm_for_each_vcpu(c, vcpu, kvm) {
1408 if (kvm_vgic_vcpu_pending_irq(vcpu))
1409 kvm_vcpu_kick(vcpu);
1410 }
1411}
1412
1413static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1414{
1415 int is_edge = vgic_irq_is_edge(vcpu, irq);
1416 int state = vgic_dist_irq_is_pending(vcpu, irq);
1417
1418 /*
1419 * Only inject an interrupt if:
1420 * - edge triggered and we have a rising edge
1421 * - level triggered and we change level
1422 */
1423 if (is_edge)
1424 return level > state;
1425 else
1426 return level != state;
1427}
1428
1429static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
1430 unsigned int irq_num, bool level)
1431{
1432 struct vgic_dist *dist = &kvm->arch.vgic;
1433 struct kvm_vcpu *vcpu;
1434 int is_edge, is_level;
1435 int enabled;
1436 bool ret = true;
1437
1438 spin_lock(&dist->lock);
1439
1440 vcpu = kvm_get_vcpu(kvm, cpuid);
1441 is_edge = vgic_irq_is_edge(vcpu, irq_num);
1442 is_level = !is_edge;
1443
1444 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1445 ret = false;
1446 goto out;
1447 }
1448
1449 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1450 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1451 vcpu = kvm_get_vcpu(kvm, cpuid);
1452 }
1453
1454 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1455
1456 if (level)
1457 vgic_dist_irq_set(vcpu, irq_num);
1458 else
1459 vgic_dist_irq_clear(vcpu, irq_num);
1460
1461 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1462
1463 if (!enabled) {
1464 ret = false;
1465 goto out;
1466 }
1467
1468 if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
1469 /*
1470 * Level interrupt in progress, will be picked up
1471 * when EOId.
1472 */
1473 ret = false;
1474 goto out;
1475 }
1476
1477 if (level) {
1478 vgic_cpu_irq_set(vcpu, irq_num);
1479 set_bit(cpuid, &dist->irq_pending_on_cpu);
1480 }
1481
1482out:
1483 spin_unlock(&dist->lock);
1484
1485 return ret;
1486}
1487
1488/**
1489 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1490 * @kvm: The VM structure pointer
1491 * @cpuid: The CPU for PPIs
1492 * @irq_num: The IRQ number that is assigned to the device
1493 * @level: Edge-triggered: true: to trigger the interrupt
1494 * false: to ignore the call
1495 * Level-sensitive true: activates an interrupt
1496 * false: deactivates an interrupt
1497 *
1498 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1499 * level-sensitive interrupts. You can think of the level parameter as 1
1500 * being HIGH and 0 being LOW and all devices being active-HIGH.
1501 */
1502int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1503 bool level)
1504{
1505 if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
1506 vgic_kick_vcpus(kvm);
1507
1508 return 0;
1509}
1510
01ac5e34
MZ		 1511static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1512{
1513 /*
1514 * We cannot rely on the vgic maintenance interrupt to be
1515 * delivered synchronously. This means we can only use it to
1516 * exit the VM, and we perform the handling of EOIed
1517 * interrupts on the exit path (see vgic_process_maintenance).
1518 */
1519 return IRQ_HANDLED;
1520}
1521
e1ba0207
CD		 1522/**
1523 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1524 * @vcpu: pointer to the vcpu struct
1525 *
1526 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1527 * this vcpu and enable the VGIC for this VCPU
1528 */
01ac5e34
MZ		 1529int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1530{
1531 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1532 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1533 int i;
1534
01ac5e34
MZ		 1535 if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
1536 return -EBUSY;
1537
1538 for (i = 0; i < VGIC_NR_IRQS; i++) {
1539 if (i < VGIC_NR_PPIS)
1540 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1541 vcpu->vcpu_id, i, 1);
1542 if (i < VGIC_NR_PRIVATE_IRQS)
1543 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1544 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1545
1546 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1547 }
1548
1549 /*
1550 * By forcing VMCR to zero, the GIC will restore the binary
1551 * points to their reset values. Anything else resets to zero
1552 * anyway.
1553 */
eede821d 1554 vgic_cpu->vgic_v2.vgic_vmcr = 0;
01ac5e34
MZ		 1555
1556 vgic_cpu->nr_lr = vgic_nr_lr;
eede821d 1557 vgic_cpu->vgic_v2.vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
01ac5e34
MZ		 1558
1559 return 0;
1560}
1561
1562static void vgic_init_maintenance_interrupt(void *info)
1563{
1564 enable_percpu_irq(vgic_maint_irq, 0);
1565}
1566
1567static int vgic_cpu_notify(struct notifier_block *self,
1568 unsigned long action, void *cpu)
1569{
1570 switch (action) {
1571 case CPU_STARTING:
1572 case CPU_STARTING_FROZEN:
1573 vgic_init_maintenance_interrupt(NULL);
1574 break;
1575 case CPU_DYING:
1576 case CPU_DYING_FROZEN:
1577 disable_percpu_irq(vgic_maint_irq);
1578 break;
1579 }
1580
1581 return NOTIFY_OK;
1582}
1583
1584static struct notifier_block vgic_cpu_nb = {
1585 .notifier_call = vgic_cpu_notify,
1586};
1587
1588int kvm_vgic_hyp_init(void)
1589{
1590 int ret;
1591 struct resource vctrl_res;
1592 struct resource vcpu_res;
1593
1594 vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
1595 if (!vgic_node) {
1596 kvm_err("error: no compatible vgic node in DT\n");
1597 return -ENODEV;
1598 }
1599
1600 vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
1601 if (!vgic_maint_irq) {
1602 kvm_err("error getting vgic maintenance irq from DT\n");
1603 ret = -ENXIO;
1604 goto out;
1605 }
1606
1607 ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
1608 "vgic", kvm_get_running_vcpus());
1609 if (ret) {
1610 kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
1611 goto out;
1612 }
1613
553f809e 1614 ret = __register_cpu_notifier(&vgic_cpu_nb);
01ac5e34
MZ		 1615 if (ret) {
1616 kvm_err("Cannot register vgic CPU notifier\n");
1617 goto out_free_irq;
1618 }
1619
1620 ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
1621 if (ret) {
1622 kvm_err("Cannot obtain VCTRL resource\n");
1623 goto out_free_irq;
1624 }
1625
1626 vgic_vctrl_base = of_iomap(vgic_node, 2);
1627 if (!vgic_vctrl_base) {
1628 kvm_err("Cannot ioremap VCTRL\n");
1629 ret = -ENOMEM;
1630 goto out_free_irq;
1631 }
1632
1633 vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
1634 vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
1635
1636 ret = create_hyp_io_mappings(vgic_vctrl_base,
1637 vgic_vctrl_base + resource_size(&vctrl_res),
1638 vctrl_res.start);
1639 if (ret) {
1640 kvm_err("Cannot map VCTRL into hyp\n");
1641 goto out_unmap;
1642 }
1643
1644 kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
1645 vctrl_res.start, vgic_maint_irq);
1646 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
1647
1648 if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
1649 kvm_err("Cannot obtain VCPU resource\n");
1650 ret = -ENXIO;
1651 goto out_unmap;
1652 }
1653 vgic_vcpu_base = vcpu_res.start;
1654
1655 goto out;
1656
1657out_unmap:
1658 iounmap(vgic_vctrl_base);
1659out_free_irq:
1660 free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
1661out:
1662 of_node_put(vgic_node);
1663 return ret;
1664}
1665
e1ba0207
CD		 1666/**
1667 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1668 * @kvm: pointer to the kvm struct
1669 *
1670 * Map the virtual CPU interface into the VM before running any VCPUs. We
1671 * can't do this at creation time, because user space must first set the
1672 * virtual CPU interface address in the guest physical address space. Also
1673 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1674 */
01ac5e34
MZ		 1675int kvm_vgic_init(struct kvm *kvm)
1676{
1677 int ret = 0, i;
1678
e1ba0207
CD		 1679 if (!irqchip_in_kernel(kvm))
1680 return 0;
1681
01ac5e34
MZ		 1682 mutex_lock(&kvm->lock);
1683
1684 if (vgic_initialized(kvm))
1685 goto out;
1686
1687 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1688 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1689 kvm_err("Need to set vgic cpu and dist addresses first\n");
1690 ret = -ENXIO;
1691 goto out;
1692 }
1693
1694 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1695 vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
1696 if (ret) {
1697 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1698 goto out;
1699 }
1700
1701 for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1702 vgic_set_target_reg(kvm, 0, i);
1703
1704 kvm->arch.vgic.ready = true;
1705out:
1706 mutex_unlock(&kvm->lock);
1707 return ret;
1708}
1709
1710int kvm_vgic_create(struct kvm *kvm)
1711{
7330672b
CD		 1712 int i, vcpu_lock_idx = -1, ret = 0;
1713 struct kvm_vcpu *vcpu;
01ac5e34
MZ		 1714
1715 mutex_lock(&kvm->lock);
1716
7330672b 1717 if (kvm->arch.vgic.vctrl_base) {
01ac5e34
MZ		 1718 ret = -EEXIST;
1719 goto out;
1720 }
1721
7330672b
CD		 1722 /*
1723 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1724 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1725 * that no other VCPUs are run while we create the vgic.
1726 */
1727 kvm_for_each_vcpu(i, vcpu, kvm) {
1728 if (!mutex_trylock(&vcpu->mutex))
1729 goto out_unlock;
1730 vcpu_lock_idx = i;
1731 }
1732
1733 kvm_for_each_vcpu(i, vcpu, kvm) {
1734 if (vcpu->arch.has_run_once) {
1735 ret = -EBUSY;
1736 goto out_unlock;
1737 }
1738 }
1739
01ac5e34
MZ		 1740 spin_lock_init(&kvm->arch.vgic.lock);
1741 kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
1742 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1743 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1744
7330672b
CD		 1745out_unlock:
1746 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1747 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1748 mutex_unlock(&vcpu->mutex);
1749 }
1750
01ac5e34
MZ		 1751out:
1752 mutex_unlock(&kvm->lock);
1753 return ret;
1754}
1755
330690cd
CD		 1756static bool vgic_ioaddr_overlap(struct kvm *kvm)
1757{
1758 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1759 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1760
1761 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1762 return 0;
1763 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1764 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1765 return -EBUSY;
1766 return 0;
1767}
1768
1769static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1770 phys_addr_t addr, phys_addr_t size)
1771{
1772 int ret;
1773
ce01e4e8
CD		 1774 if (addr & ~KVM_PHYS_MASK)
1775 return -E2BIG;
1776
1777 if (addr & (SZ_4K - 1))
1778 return -EINVAL;
1779
330690cd
CD		 1780 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1781 return -EEXIST;
1782 if (addr + size < addr)
1783 return -EINVAL;
1784
30c21170 1785 *ioaddr = addr;
330690cd
CD		 1786 ret = vgic_ioaddr_overlap(kvm);
1787 if (ret)
30c21170
HW		 1788 *ioaddr = VGIC_ADDR_UNDEF;
1789
330690cd
CD		 1790 return ret;
1791}
1792
ce01e4e8
CD		 1793/**
1794 * kvm_vgic_addr - set or get vgic VM base addresses
1795 * @kvm: pointer to the vm struct
1796 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1797 * @addr: pointer to address value
1798 * @write: if true set the address in the VM address space, if false read the
1799 * address
1800 *
1801 * Set or get the vgic base addresses for the distributor and the virtual CPU
1802 * interface in the VM physical address space. These addresses are properties
1803 * of the emulated core/SoC and therefore user space initially knows this
1804 * information.
1805 */
1806int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
330690cd
CD		 1807{
1808 int r = 0;
1809 struct vgic_dist *vgic = &kvm->arch.vgic;
1810
330690cd
CD		 1811 mutex_lock(&kvm->lock);
1812 switch (type) {
1813 case KVM_VGIC_V2_ADDR_TYPE_DIST:
ce01e4e8
CD		 1814 if (write) {
1815 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1816 *addr, KVM_VGIC_V2_DIST_SIZE);
1817 } else {
1818 *addr = vgic->vgic_dist_base;
1819 }
330690cd
CD		 1820 break;
1821 case KVM_VGIC_V2_ADDR_TYPE_CPU:
ce01e4e8
CD		 1822 if (write) {
1823 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1824 *addr, KVM_VGIC_V2_CPU_SIZE);
1825 } else {
1826 *addr = vgic->vgic_cpu_base;
1827 }
330690cd
CD		 1828 break;
1829 default:
1830 r = -ENODEV;
1831 }
1832
1833 mutex_unlock(&kvm->lock);
1834 return r;
1835}
7330672b 1836
c07a0191
CD		 1837static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
1838 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1839{
fa20f5ae
CD		 1840 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1841 u32 reg, mask = 0, shift = 0;
1842 bool updated = false;
1843
1844 switch (offset & ~0x3) {
1845 case GIC_CPU_CTRL:
1846 mask = GICH_VMCR_CTRL_MASK;
1847 shift = GICH_VMCR_CTRL_SHIFT;
1848 break;
1849 case GIC_CPU_PRIMASK:
1850 mask = GICH_VMCR_PRIMASK_MASK;
1851 shift = GICH_VMCR_PRIMASK_SHIFT;
1852 break;
1853 case GIC_CPU_BINPOINT:
1854 mask = GICH_VMCR_BINPOINT_MASK;
1855 shift = GICH_VMCR_BINPOINT_SHIFT;
1856 break;
1857 case GIC_CPU_ALIAS_BINPOINT:
1858 mask = GICH_VMCR_ALIAS_BINPOINT_MASK;
1859 shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT;
1860 break;
1861 }
1862
1863 if (!mmio->is_write) {
eede821d 1864 reg = (vgic_cpu->vgic_v2.vgic_vmcr & mask) >> shift;
fa20f5ae
CD		 1865 mmio_data_write(mmio, ~0, reg);
1866 } else {
1867 reg = mmio_data_read(mmio, ~0);
1868 reg = (reg << shift) & mask;
eede821d 1869 if (reg != (vgic_cpu->vgic_v2.vgic_vmcr & mask))
fa20f5ae 1870 updated = true;
eede821d
MZ		 1871 vgic_cpu->vgic_v2.vgic_vmcr &= ~mask;
1872 vgic_cpu->vgic_v2.vgic_vmcr |= reg;
fa20f5ae
CD		 1873 }
1874 return updated;
1875}
1876
1877static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
1878 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1879{
1880 return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
c07a0191
CD		 1881}
1882
fa20f5ae
CD		 1883static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
1884 struct kvm_exit_mmio *mmio,
1885 phys_addr_t offset)
1886{
1887 u32 reg;
1888
1889 if (mmio->is_write)
1890 return false;
1891
1892 /* GICC_IIDR */
1893 reg = (PRODUCT_ID_KVM << 20) |
1894 (GICC_ARCH_VERSION_V2 << 16) |
1895 (IMPLEMENTER_ARM << 0);
1896 mmio_data_write(mmio, ~0, reg);
1897 return false;
1898}
1899
1900/*
1901 * CPU Interface Register accesses - these are not accessed by the VM, but by
1902 * user space for saving and restoring VGIC state.
1903 */
c07a0191
CD		 1904static const struct mmio_range vgic_cpu_ranges[] = {
1905 {
1906 .base = GIC_CPU_CTRL,
1907 .len = 12,
1908 .handle_mmio = handle_cpu_mmio_misc,
1909 },
1910 {
1911 .base = GIC_CPU_ALIAS_BINPOINT,
1912 .len = 4,
fa20f5ae 1913 .handle_mmio = handle_mmio_abpr,
c07a0191
CD		 1914 },
1915 {
1916 .base = GIC_CPU_ACTIVEPRIO,
1917 .len = 16,
fa20f5ae 1918 .handle_mmio = handle_mmio_raz_wi,
c07a0191
CD		 1919 },
1920 {
1921 .base = GIC_CPU_IDENT,
1922 .len = 4,
fa20f5ae 1923 .handle_mmio = handle_cpu_mmio_ident,
c07a0191
CD		 1924 },
1925};
1926
1927static int vgic_attr_regs_access(struct kvm_device *dev,
1928 struct kvm_device_attr *attr,
1929 u32 *reg, bool is_write)
1930{
1931 const struct mmio_range *r = NULL, *ranges;
1932 phys_addr_t offset;
1933 int ret, cpuid, c;
1934 struct kvm_vcpu *vcpu, *tmp_vcpu;
1935 struct vgic_dist *vgic;
1936 struct kvm_exit_mmio mmio;
1937
1938 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1939 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
1940 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
1941
1942 mutex_lock(&dev->kvm->lock);
1943
1944 if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
1945 ret = -EINVAL;
1946 goto out;
1947 }
1948
1949 vcpu = kvm_get_vcpu(dev->kvm, cpuid);
1950 vgic = &dev->kvm->arch.vgic;
1951
1952 mmio.len = 4;
1953 mmio.is_write = is_write;
1954 if (is_write)
1955 mmio_data_write(&mmio, ~0, *reg);
1956 switch (attr->group) {
1957 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1958 mmio.phys_addr = vgic->vgic_dist_base + offset;
1959 ranges = vgic_dist_ranges;
1960 break;
1961 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
1962 mmio.phys_addr = vgic->vgic_cpu_base + offset;
1963 ranges = vgic_cpu_ranges;
1964 break;
1965 default:
1966 BUG();
1967 }
1968 r = find_matching_range(ranges, &mmio, offset);
1969
1970 if (unlikely(!r || !r->handle_mmio)) {
1971 ret = -ENXIO;
1972 goto out;
1973 }
1974
1975
1976 spin_lock(&vgic->lock);
1977
1978 /*
1979 * Ensure that no other VCPU is running by checking the vcpu->cpu
1980 * field. If no other VPCUs are running we can safely access the VGIC
1981 * state, because even if another VPU is run after this point, that
1982 * VCPU will not touch the vgic state, because it will block on
1983 * getting the vgic->lock in kvm_vgic_sync_hwstate().
1984 */
1985 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
1986 if (unlikely(tmp_vcpu->cpu != -1)) {
1987 ret = -EBUSY;
1988 goto out_vgic_unlock;
1989 }
1990 }
1991
cbd333a4
CD		 1992 /*
1993 * Move all pending IRQs from the LRs on all VCPUs so the pending
1994 * state can be properly represented in the register state accessible
1995 * through this API.
1996 */
1997 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
1998 vgic_unqueue_irqs(tmp_vcpu);
1999
c07a0191
CD		 2000 offset -= r->base;
2001 r->handle_mmio(vcpu, &mmio, offset);
2002
2003 if (!is_write)
2004 *reg = mmio_data_read(&mmio, ~0);
2005
2006 ret = 0;
2007out_vgic_unlock:
2008 spin_unlock(&vgic->lock);
2009out:
2010 mutex_unlock(&dev->kvm->lock);
2011 return ret;
2012}
2013
7330672b
CD		 2014static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2015{
ce01e4e8
CD		 2016 int r;
2017
2018 switch (attr->group) {
2019 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2020 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2021 u64 addr;
2022 unsigned long type = (unsigned long)attr->attr;
2023
2024 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2025 return -EFAULT;
2026
2027 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2028 return (r == -ENODEV) ? -ENXIO : r;
2029 }
c07a0191
CD		 2030
2031 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2032 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2033 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2034 u32 reg;
2035
2036 if (get_user(reg, uaddr))
2037 return -EFAULT;
2038
2039 return vgic_attr_regs_access(dev, attr, &reg, true);
2040 }
2041
ce01e4e8
CD		 2042 }
2043
7330672b
CD		 2044 return -ENXIO;
2045}
2046
2047static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2048{
ce01e4e8
CD		 2049 int r = -ENXIO;
2050
2051 switch (attr->group) {
2052 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2053 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2054 u64 addr;
2055 unsigned long type = (unsigned long)attr->attr;
2056
2057 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2058 if (r)
2059 return (r == -ENODEV) ? -ENXIO : r;
2060
2061 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2062 return -EFAULT;
c07a0191
CD		 2063 break;
2064 }
2065
2066 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2067 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2068 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2069 u32 reg = 0;
2070
2071 r = vgic_attr_regs_access(dev, attr, &reg, false);
2072 if (r)
2073 return r;
2074 r = put_user(reg, uaddr);
2075 break;
ce01e4e8 2076 }
c07a0191 2077
ce01e4e8
CD		 2078 }
2079
2080 return r;
7330672b
CD		 2081}
2082
c07a0191
CD		 2083static int vgic_has_attr_regs(const struct mmio_range *ranges,
2084 phys_addr_t offset)
2085{
2086 struct kvm_exit_mmio dev_attr_mmio;
2087
2088 dev_attr_mmio.len = 4;
2089 if (find_matching_range(ranges, &dev_attr_mmio, offset))
2090 return 0;
2091 else
2092 return -ENXIO;
2093}
2094
7330672b
CD		 2095static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2096{
c07a0191
CD		 2097 phys_addr_t offset;
2098
ce01e4e8
CD		 2099 switch (attr->group) {
2100 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2101 switch (attr->attr) {
2102 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2103 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2104 return 0;
2105 }
2106 break;
c07a0191
CD		 2107 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2108 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2109 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2110 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2111 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2112 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
ce01e4e8 2113 }
7330672b
CD		 2114 return -ENXIO;
2115}
2116
2117static void vgic_destroy(struct kvm_device *dev)
2118{
2119 kfree(dev);
2120}
2121
2122static int vgic_create(struct kvm_device *dev, u32 type)
2123{
2124 return kvm_vgic_create(dev->kvm);
2125}
2126
2127struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2128 .name = "kvm-arm-vgic",
2129 .create = vgic_create,
2130 .destroy = vgic_destroy,
2131 .set_attr = vgic_set_attr,
2132 .get_attr = vgic_get_attr,
2133 .has_attr = vgic_has_attr,
2134};
Linux kernel - Deliverables
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