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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
39 | * something is pending | |
227844f5 | 40 | * - VGIC pending interrupts are stored on the vgic.irq_pending vgic |
b47ef92a MZ |
41 | * bitmap (this bitmap is updated by both user land ioctls and guest |
42 | * mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers) and indicate the 'wire' state. | |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is | |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
48 | * - PPI: dist->irq_pending & dist->irq_enable |
49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
b47ef92a MZ |
50 | * - irq_spi_target is a 'formatted' version of the GICD_ICFGR |
51 | * registers, stored on each vcpu. We only keep one bit of | |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
54 | * - The same is true when injecting an interrupt, except that we only | |
55 | * consider a single interrupt at a time. The irq_spi_cpu array | |
56 | * contains the target CPU for each SPI. | |
57 | * | |
58 | * The handling of level interrupts adds some extra complexity. We | |
59 | * need to track when the interrupt has been EOIed, so we can sample | |
60 | * the 'line' again. This is achieved as such: | |
61 | * | |
62 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 63 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
64 | * will be ignored for further interrupts. The interrupt is injected |
65 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
66 | * maintenance interrupt on EOI). | |
67 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 68 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 69 | * interrupt line to be sampled again. |
faa1b46c CD |
70 | * - Note that level-triggered interrupts can also be set to pending from |
71 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
72 | * cause the interrupt to become inactive in such a situation. | |
73 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
74 | * inactive as long as the external input line is held high. | |
b47ef92a MZ |
75 | */ |
76 | ||
330690cd CD |
77 | #define VGIC_ADDR_UNDEF (-1) |
78 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) | |
79 | ||
fa20f5ae CD |
80 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
81 | #define IMPLEMENTER_ARM 0x43b | |
82 | #define GICC_ARCH_VERSION_V2 0x2 | |
83 | ||
1a89dd91 MZ |
84 | #define ACCESS_READ_VALUE (1 << 0) |
85 | #define ACCESS_READ_RAZ (0 << 0) | |
86 | #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) | |
87 | #define ACCESS_WRITE_IGNORED (0 << 1) | |
88 | #define ACCESS_WRITE_SETBIT (1 << 1) | |
89 | #define ACCESS_WRITE_CLEARBIT (2 << 1) | |
90 | #define ACCESS_WRITE_VALUE (3 << 1) | |
91 | #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) | |
92 | ||
a1fcb44e | 93 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 94 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
b47ef92a | 95 | static void vgic_update_state(struct kvm *kvm); |
5863c2ce | 96 | static void vgic_kick_vcpus(struct kvm *kvm); |
b47ef92a | 97 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
8d5c6b06 MZ |
98 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
99 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
beee38b9 MZ |
100 | static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
101 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
01ac5e34 | 102 | |
8f186d52 MZ |
103 | static const struct vgic_ops *vgic_ops; |
104 | static const struct vgic_params *vgic; | |
b47ef92a | 105 | |
9662fb48 VK |
106 | /* |
107 | * struct vgic_bitmap contains unions that provide two views of | |
108 | * the same data. In one case it is an array of registers of | |
109 | * u32's, and in the other case it is a bitmap of unsigned | |
110 | * longs. | |
111 | * | |
112 | * This does not work on 64-bit BE systems, because the bitmap access | |
113 | * will store two consecutive 32-bit words with the higher-addressed | |
114 | * register's bits at the lower index and the lower-addressed register's | |
115 | * bits at the higher index. | |
116 | * | |
117 | * Therefore, swizzle the register index when accessing the 32-bit word | |
118 | * registers to access the right register's value. | |
119 | */ | |
120 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
121 | #define REG_OFFSET_SWIZZLE 1 | |
122 | #else | |
123 | #define REG_OFFSET_SWIZZLE 0 | |
124 | #endif | |
b47ef92a MZ |
125 | |
126 | static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, | |
127 | int cpuid, u32 offset) | |
128 | { | |
129 | offset >>= 2; | |
130 | if (!offset) | |
9662fb48 | 131 | return x->percpu[cpuid].reg + (offset ^ REG_OFFSET_SWIZZLE); |
b47ef92a | 132 | else |
9662fb48 | 133 | return x->shared.reg + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
134 | } |
135 | ||
136 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
137 | int cpuid, int irq) | |
138 | { | |
139 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
140 | return test_bit(irq, x->percpu[cpuid].reg_ul); | |
141 | ||
142 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul); | |
143 | } | |
144 | ||
145 | static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, | |
146 | int irq, int val) | |
147 | { | |
148 | unsigned long *reg; | |
149 | ||
150 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
151 | reg = x->percpu[cpuid].reg_ul; | |
152 | } else { | |
153 | reg = x->shared.reg_ul; | |
154 | irq -= VGIC_NR_PRIVATE_IRQS; | |
155 | } | |
156 | ||
157 | if (val) | |
158 | set_bit(irq, reg); | |
159 | else | |
160 | clear_bit(irq, reg); | |
161 | } | |
162 | ||
163 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
164 | { | |
165 | if (unlikely(cpuid >= VGIC_MAX_CPUS)) | |
166 | return NULL; | |
167 | return x->percpu[cpuid].reg_ul; | |
168 | } | |
169 | ||
170 | static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) | |
171 | { | |
172 | return x->shared.reg_ul; | |
173 | } | |
174 | ||
175 | static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) | |
176 | { | |
177 | offset >>= 2; | |
178 | BUG_ON(offset > (VGIC_NR_IRQS / 4)); | |
8d98915b | 179 | if (offset < 8) |
b47ef92a MZ |
180 | return x->percpu[cpuid] + offset; |
181 | else | |
182 | return x->shared + offset - 8; | |
183 | } | |
184 | ||
185 | #define VGIC_CFG_LEVEL 0 | |
186 | #define VGIC_CFG_EDGE 1 | |
187 | ||
188 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
189 | { | |
190 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
191 | int irq_val; | |
192 | ||
193 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
194 | return irq_val == VGIC_CFG_EDGE; | |
195 | } | |
196 | ||
197 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
198 | { | |
199 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
200 | ||
201 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
202 | } | |
203 | ||
dbf20f9d | 204 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
205 | { |
206 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
207 | ||
dbf20f9d | 208 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
209 | } |
210 | ||
dbf20f9d | 211 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
212 | { |
213 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
214 | ||
dbf20f9d | 215 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
216 | } |
217 | ||
dbf20f9d | 218 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
219 | { |
220 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
221 | ||
dbf20f9d | 222 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
223 | } |
224 | ||
faa1b46c CD |
225 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
226 | { | |
227 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
228 | ||
229 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
230 | } | |
231 | ||
232 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
233 | { | |
234 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
235 | ||
236 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
237 | } | |
238 | ||
239 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
240 | { | |
241 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
242 | ||
243 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
244 | } | |
245 | ||
246 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
247 | { | |
248 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
249 | ||
250 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
251 | } | |
252 | ||
253 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
254 | { | |
255 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
256 | ||
257 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
258 | } | |
259 | ||
9d949dce MZ |
260 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
261 | { | |
262 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
263 | ||
227844f5 | 264 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
265 | } |
266 | ||
227844f5 | 267 | static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
268 | { |
269 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
270 | ||
227844f5 | 271 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
272 | } |
273 | ||
227844f5 | 274 | static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
275 | { |
276 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
277 | ||
227844f5 | 278 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
279 | } |
280 | ||
281 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
282 | { | |
283 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
284 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
285 | else | |
286 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
287 | vcpu->arch.vgic_cpu.pending_shared); | |
288 | } | |
289 | ||
290 | static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
291 | { | |
292 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
293 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
294 | else | |
295 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
296 | vcpu->arch.vgic_cpu.pending_shared); | |
297 | } | |
298 | ||
dbf20f9d CD |
299 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
300 | { | |
301 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
302 | } | |
303 | ||
1a89dd91 MZ |
304 | static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) |
305 | { | |
1c9f0471 | 306 | return le32_to_cpu(*((u32 *)mmio->data)) & mask; |
1a89dd91 MZ |
307 | } |
308 | ||
309 | static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) | |
310 | { | |
1c9f0471 | 311 | *((u32 *)mmio->data) = cpu_to_le32(value) & mask; |
1a89dd91 MZ |
312 | } |
313 | ||
314 | /** | |
315 | * vgic_reg_access - access vgic register | |
316 | * @mmio: pointer to the data describing the mmio access | |
317 | * @reg: pointer to the virtual backing of vgic distributor data | |
318 | * @offset: least significant 2 bits used for word offset | |
319 | * @mode: ACCESS_ mode (see defines above) | |
320 | * | |
321 | * Helper to make vgic register access easier using one of the access | |
322 | * modes defined for vgic register access | |
323 | * (read,raz,write-ignored,setbit,clearbit,write) | |
324 | */ | |
325 | static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, | |
326 | phys_addr_t offset, int mode) | |
327 | { | |
328 | int word_offset = (offset & 3) * 8; | |
329 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
330 | u32 regval; | |
331 | ||
332 | /* | |
333 | * Any alignment fault should have been delivered to the guest | |
334 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
335 | */ | |
336 | ||
337 | if (reg) { | |
338 | regval = *reg; | |
339 | } else { | |
340 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
341 | regval = 0; | |
342 | } | |
343 | ||
344 | if (mmio->is_write) { | |
345 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
346 | switch (ACCESS_WRITE_MASK(mode)) { | |
347 | case ACCESS_WRITE_IGNORED: | |
348 | return; | |
349 | ||
350 | case ACCESS_WRITE_SETBIT: | |
351 | regval |= data; | |
352 | break; | |
353 | ||
354 | case ACCESS_WRITE_CLEARBIT: | |
355 | regval &= ~data; | |
356 | break; | |
357 | ||
358 | case ACCESS_WRITE_VALUE: | |
359 | regval = (regval & ~(mask << word_offset)) | data; | |
360 | break; | |
361 | } | |
362 | *reg = regval; | |
363 | } else { | |
364 | switch (ACCESS_READ_MASK(mode)) { | |
365 | case ACCESS_READ_RAZ: | |
366 | regval = 0; | |
367 | /* fall through */ | |
368 | ||
369 | case ACCESS_READ_VALUE: | |
370 | mmio_data_write(mmio, mask, regval >> word_offset); | |
371 | } | |
372 | } | |
373 | } | |
374 | ||
b47ef92a MZ |
375 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
376 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
377 | { | |
378 | u32 reg; | |
379 | u32 word_offset = offset & 3; | |
380 | ||
381 | switch (offset & ~3) { | |
fa20f5ae | 382 | case 0: /* GICD_CTLR */ |
b47ef92a MZ |
383 | reg = vcpu->kvm->arch.vgic.enabled; |
384 | vgic_reg_access(mmio, ®, word_offset, | |
385 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
386 | if (mmio->is_write) { | |
387 | vcpu->kvm->arch.vgic.enabled = reg & 1; | |
388 | vgic_update_state(vcpu->kvm); | |
389 | return true; | |
390 | } | |
391 | break; | |
392 | ||
fa20f5ae | 393 | case 4: /* GICD_TYPER */ |
b47ef92a MZ |
394 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
395 | reg |= (VGIC_NR_IRQS >> 5) - 1; | |
396 | vgic_reg_access(mmio, ®, word_offset, | |
397 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
398 | break; | |
399 | ||
fa20f5ae CD |
400 | case 8: /* GICD_IIDR */ |
401 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
b47ef92a MZ |
402 | vgic_reg_access(mmio, ®, word_offset, |
403 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
404 | break; | |
405 | } | |
406 | ||
407 | return false; | |
408 | } | |
409 | ||
410 | static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, | |
411 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
412 | { | |
413 | vgic_reg_access(mmio, NULL, offset, | |
414 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
415 | return false; | |
416 | } | |
417 | ||
418 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, | |
419 | struct kvm_exit_mmio *mmio, | |
420 | phys_addr_t offset) | |
421 | { | |
422 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
423 | vcpu->vcpu_id, offset); | |
424 | vgic_reg_access(mmio, reg, offset, | |
425 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
426 | if (mmio->is_write) { | |
427 | vgic_update_state(vcpu->kvm); | |
428 | return true; | |
429 | } | |
430 | ||
431 | return false; | |
432 | } | |
433 | ||
434 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, | |
435 | struct kvm_exit_mmio *mmio, | |
436 | phys_addr_t offset) | |
437 | { | |
438 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
439 | vcpu->vcpu_id, offset); | |
440 | vgic_reg_access(mmio, reg, offset, | |
441 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
442 | if (mmio->is_write) { | |
443 | if (offset < 4) /* Force SGI enabled */ | |
444 | *reg |= 0xffff; | |
a1fcb44e | 445 | vgic_retire_disabled_irqs(vcpu); |
b47ef92a MZ |
446 | vgic_update_state(vcpu->kvm); |
447 | return true; | |
448 | } | |
449 | ||
450 | return false; | |
451 | } | |
452 | ||
453 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, | |
454 | struct kvm_exit_mmio *mmio, | |
455 | phys_addr_t offset) | |
456 | { | |
9da48b55 | 457 | u32 *reg, orig; |
faa1b46c CD |
458 | u32 level_mask; |
459 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
460 | ||
461 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset); | |
462 | level_mask = (~(*reg)); | |
463 | ||
464 | /* Mark both level and edge triggered irqs as pending */ | |
465 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 466 | orig = *reg; |
b47ef92a MZ |
467 | vgic_reg_access(mmio, reg, offset, |
468 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
faa1b46c | 469 | |
b47ef92a | 470 | if (mmio->is_write) { |
faa1b46c CD |
471 | /* Set the soft-pending flag only for level-triggered irqs */ |
472 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
473 | vcpu->vcpu_id, offset); | |
474 | vgic_reg_access(mmio, reg, offset, | |
475 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
476 | *reg &= level_mask; | |
477 | ||
9da48b55 CD |
478 | /* Ignore writes to SGIs */ |
479 | if (offset < 2) { | |
480 | *reg &= ~0xffff; | |
481 | *reg |= orig & 0xffff; | |
482 | } | |
483 | ||
b47ef92a MZ |
484 | vgic_update_state(vcpu->kvm); |
485 | return true; | |
486 | } | |
487 | ||
488 | return false; | |
489 | } | |
490 | ||
491 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, | |
492 | struct kvm_exit_mmio *mmio, | |
493 | phys_addr_t offset) | |
494 | { | |
faa1b46c | 495 | u32 *level_active; |
9da48b55 | 496 | u32 *reg, orig; |
faa1b46c CD |
497 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
498 | ||
499 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 500 | orig = *reg; |
b47ef92a MZ |
501 | vgic_reg_access(mmio, reg, offset, |
502 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
503 | if (mmio->is_write) { | |
faa1b46c CD |
504 | /* Re-set level triggered level-active interrupts */ |
505 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
506 | vcpu->vcpu_id, offset); | |
507 | reg = vgic_bitmap_get_reg(&dist->irq_pending, | |
508 | vcpu->vcpu_id, offset); | |
509 | *reg |= *level_active; | |
510 | ||
9da48b55 CD |
511 | /* Ignore writes to SGIs */ |
512 | if (offset < 2) { | |
513 | *reg &= ~0xffff; | |
514 | *reg |= orig & 0xffff; | |
515 | } | |
516 | ||
faa1b46c CD |
517 | /* Clear soft-pending flags */ |
518 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
519 | vcpu->vcpu_id, offset); | |
520 | vgic_reg_access(mmio, reg, offset, | |
521 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
522 | ||
b47ef92a MZ |
523 | vgic_update_state(vcpu->kvm); |
524 | return true; | |
525 | } | |
526 | ||
527 | return false; | |
528 | } | |
529 | ||
530 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, | |
531 | struct kvm_exit_mmio *mmio, | |
532 | phys_addr_t offset) | |
533 | { | |
534 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, | |
535 | vcpu->vcpu_id, offset); | |
536 | vgic_reg_access(mmio, reg, offset, | |
537 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
538 | return false; | |
539 | } | |
540 | ||
541 | #define GICD_ITARGETSR_SIZE 32 | |
542 | #define GICD_CPUTARGETS_BITS 8 | |
543 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) | |
544 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) | |
545 | { | |
546 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986af8e0 | 547 | int i; |
b47ef92a MZ |
548 | u32 val = 0; |
549 | ||
550 | irq -= VGIC_NR_PRIVATE_IRQS; | |
551 | ||
986af8e0 MZ |
552 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
553 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); | |
b47ef92a MZ |
554 | |
555 | return val; | |
556 | } | |
557 | ||
558 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) | |
559 | { | |
560 | struct vgic_dist *dist = &kvm->arch.vgic; | |
561 | struct kvm_vcpu *vcpu; | |
562 | int i, c; | |
563 | unsigned long *bmap; | |
564 | u32 target; | |
565 | ||
566 | irq -= VGIC_NR_PRIVATE_IRQS; | |
567 | ||
568 | /* | |
569 | * Pick the LSB in each byte. This ensures we target exactly | |
570 | * one vcpu per IRQ. If the byte is null, assume we target | |
571 | * CPU0. | |
572 | */ | |
573 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { | |
574 | int shift = i * GICD_CPUTARGETS_BITS; | |
575 | target = ffs((val >> shift) & 0xffU); | |
576 | target = target ? (target - 1) : 0; | |
577 | dist->irq_spi_cpu[irq + i] = target; | |
578 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
579 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); | |
580 | if (c == target) | |
581 | set_bit(irq + i, bmap); | |
582 | else | |
583 | clear_bit(irq + i, bmap); | |
584 | } | |
585 | } | |
586 | } | |
587 | ||
588 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, | |
589 | struct kvm_exit_mmio *mmio, | |
590 | phys_addr_t offset) | |
591 | { | |
592 | u32 reg; | |
593 | ||
594 | /* We treat the banked interrupts targets as read-only */ | |
595 | if (offset < 32) { | |
596 | u32 roreg = 1 << vcpu->vcpu_id; | |
597 | roreg |= roreg << 8; | |
598 | roreg |= roreg << 16; | |
599 | ||
600 | vgic_reg_access(mmio, &roreg, offset, | |
601 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
602 | return false; | |
603 | } | |
604 | ||
605 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); | |
606 | vgic_reg_access(mmio, ®, offset, | |
607 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
608 | if (mmio->is_write) { | |
609 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); | |
610 | vgic_update_state(vcpu->kvm); | |
611 | return true; | |
612 | } | |
613 | ||
614 | return false; | |
615 | } | |
616 | ||
617 | static u32 vgic_cfg_expand(u16 val) | |
618 | { | |
619 | u32 res = 0; | |
620 | int i; | |
621 | ||
622 | /* | |
623 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
624 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
625 | */ | |
626 | for (i = 0; i < 16; i++) | |
627 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
628 | ||
629 | return res; | |
630 | } | |
631 | ||
632 | static u16 vgic_cfg_compress(u32 val) | |
633 | { | |
634 | u16 res = 0; | |
635 | int i; | |
636 | ||
637 | /* | |
638 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
639 | * abcd...mnop which is what we really care about. | |
640 | */ | |
641 | for (i = 0; i < 16; i++) | |
642 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
643 | ||
644 | return res; | |
645 | } | |
646 | ||
647 | /* | |
648 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
649 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
650 | * two above functions to compress/expand the bits | |
651 | */ | |
652 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, | |
653 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
654 | { | |
655 | u32 val; | |
6545eae3 MZ |
656 | u32 *reg; |
657 | ||
6545eae3 | 658 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
f2ae85b2 | 659 | vcpu->vcpu_id, offset >> 1); |
6545eae3 | 660 | |
f2ae85b2 | 661 | if (offset & 4) |
b47ef92a MZ |
662 | val = *reg >> 16; |
663 | else | |
664 | val = *reg & 0xffff; | |
665 | ||
666 | val = vgic_cfg_expand(val); | |
667 | vgic_reg_access(mmio, &val, offset, | |
668 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
669 | if (mmio->is_write) { | |
f2ae85b2 | 670 | if (offset < 8) { |
b47ef92a MZ |
671 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
672 | return false; | |
673 | } | |
674 | ||
675 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 676 | if (offset & 4) { |
b47ef92a MZ |
677 | *reg &= 0xffff; |
678 | *reg |= val << 16; | |
679 | } else { | |
680 | *reg &= 0xffff << 16; | |
681 | *reg |= val; | |
682 | } | |
683 | } | |
684 | ||
685 | return false; | |
686 | } | |
687 | ||
688 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, | |
689 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
690 | { | |
691 | u32 reg; | |
692 | vgic_reg_access(mmio, ®, offset, | |
693 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); | |
694 | if (mmio->is_write) { | |
695 | vgic_dispatch_sgi(vcpu, reg); | |
696 | vgic_update_state(vcpu->kvm); | |
697 | return true; | |
698 | } | |
699 | ||
700 | return false; | |
701 | } | |
702 | ||
cbd333a4 CD |
703 | /** |
704 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
705 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
706 | * | |
707 | * Move any pending IRQs that have already been assigned to LRs back to the | |
708 | * emulated distributor state so that the complete emulated state can be read | |
709 | * from the main emulation structures without investigating the LRs. | |
710 | * | |
711 | * Note that IRQs in the active state in the LRs get their pending state moved | |
712 | * to the distributor but the active state stays in the LRs, because we don't | |
713 | * track the active state on the distributor side. | |
714 | */ | |
715 | static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) | |
716 | { | |
717 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
718 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
719 | int vcpu_id = vcpu->vcpu_id; | |
8d5c6b06 | 720 | int i; |
cbd333a4 CD |
721 | |
722 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 723 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
724 | |
725 | /* | |
726 | * There are three options for the state bits: | |
727 | * | |
728 | * 01: pending | |
729 | * 10: active | |
730 | * 11: pending and active | |
731 | * | |
732 | * If the LR holds only an active interrupt (not pending) then | |
733 | * just leave it alone. | |
734 | */ | |
8d5c6b06 | 735 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
736 | continue; |
737 | ||
738 | /* | |
739 | * Reestablish the pending state on the distributor and the | |
740 | * CPU interface. It may have already been pending, but that | |
741 | * is fine, then we are only setting a few bits that were | |
742 | * already set. | |
743 | */ | |
227844f5 | 744 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
8d5c6b06 MZ |
745 | if (lr.irq < VGIC_NR_SGIS) |
746 | dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source; | |
747 | lr.state &= ~LR_STATE_PENDING; | |
748 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
749 | |
750 | /* | |
751 | * If there's no state left on the LR (it could still be | |
752 | * active), then the LR does not hold any useful info and can | |
753 | * be marked as free for other use. | |
754 | */ | |
cced50c9 | 755 | if (!(lr.state & LR_STATE_MASK)) { |
8d5c6b06 | 756 | vgic_retire_lr(i, lr.irq, vcpu); |
cced50c9 CD |
757 | vgic_irq_clear_queued(vcpu, lr.irq); |
758 | } | |
cbd333a4 CD |
759 | |
760 | /* Finally update the VGIC state. */ | |
761 | vgic_update_state(vcpu->kvm); | |
762 | } | |
763 | } | |
764 | ||
90a5355e CD |
765 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
766 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, | |
767 | struct kvm_exit_mmio *mmio, | |
768 | phys_addr_t offset) | |
c07a0191 | 769 | { |
90a5355e CD |
770 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
771 | int sgi; | |
772 | int min_sgi = (offset & ~0x3) * 4; | |
773 | int max_sgi = min_sgi + 3; | |
774 | int vcpu_id = vcpu->vcpu_id; | |
775 | u32 reg = 0; | |
776 | ||
777 | /* Copy source SGIs from distributor side */ | |
778 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
779 | int shift = 8 * (sgi - min_sgi); | |
780 | reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift; | |
781 | } | |
782 | ||
783 | mmio_data_write(mmio, ~0, reg); | |
c07a0191 CD |
784 | return false; |
785 | } | |
786 | ||
90a5355e CD |
787 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
788 | struct kvm_exit_mmio *mmio, | |
789 | phys_addr_t offset, bool set) | |
790 | { | |
791 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
792 | int sgi; | |
793 | int min_sgi = (offset & ~0x3) * 4; | |
794 | int max_sgi = min_sgi + 3; | |
795 | int vcpu_id = vcpu->vcpu_id; | |
796 | u32 reg; | |
797 | bool updated = false; | |
798 | ||
799 | reg = mmio_data_read(mmio, ~0); | |
800 | ||
801 | /* Clear pending SGIs on the distributor */ | |
802 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
803 | u8 mask = reg >> (8 * (sgi - min_sgi)); | |
804 | if (set) { | |
805 | if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask) | |
806 | updated = true; | |
807 | dist->irq_sgi_sources[vcpu_id][sgi] |= mask; | |
808 | } else { | |
809 | if (dist->irq_sgi_sources[vcpu_id][sgi] & mask) | |
810 | updated = true; | |
811 | dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask; | |
812 | } | |
813 | } | |
814 | ||
815 | if (updated) | |
816 | vgic_update_state(vcpu->kvm); | |
817 | ||
818 | return updated; | |
819 | } | |
820 | ||
c07a0191 CD |
821 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
822 | struct kvm_exit_mmio *mmio, | |
823 | phys_addr_t offset) | |
824 | { | |
90a5355e CD |
825 | if (!mmio->is_write) |
826 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
827 | else | |
828 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); | |
829 | } | |
830 | ||
831 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, | |
832 | struct kvm_exit_mmio *mmio, | |
833 | phys_addr_t offset) | |
834 | { | |
835 | if (!mmio->is_write) | |
836 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
837 | else | |
838 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); | |
c07a0191 CD |
839 | } |
840 | ||
1a89dd91 MZ |
841 | /* |
842 | * I would have liked to use the kvm_bus_io_*() API instead, but it | |
843 | * cannot cope with banked registers (only the VM pointer is passed | |
844 | * around, and we need the vcpu). One of these days, someone please | |
845 | * fix it! | |
846 | */ | |
847 | struct mmio_range { | |
848 | phys_addr_t base; | |
849 | unsigned long len; | |
850 | bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, | |
851 | phys_addr_t offset); | |
852 | }; | |
853 | ||
1006e8cb | 854 | static const struct mmio_range vgic_dist_ranges[] = { |
b47ef92a MZ |
855 | { |
856 | .base = GIC_DIST_CTRL, | |
857 | .len = 12, | |
858 | .handle_mmio = handle_mmio_misc, | |
859 | }, | |
860 | { | |
861 | .base = GIC_DIST_IGROUP, | |
862 | .len = VGIC_NR_IRQS / 8, | |
863 | .handle_mmio = handle_mmio_raz_wi, | |
864 | }, | |
865 | { | |
866 | .base = GIC_DIST_ENABLE_SET, | |
867 | .len = VGIC_NR_IRQS / 8, | |
868 | .handle_mmio = handle_mmio_set_enable_reg, | |
869 | }, | |
870 | { | |
871 | .base = GIC_DIST_ENABLE_CLEAR, | |
872 | .len = VGIC_NR_IRQS / 8, | |
873 | .handle_mmio = handle_mmio_clear_enable_reg, | |
874 | }, | |
875 | { | |
876 | .base = GIC_DIST_PENDING_SET, | |
877 | .len = VGIC_NR_IRQS / 8, | |
878 | .handle_mmio = handle_mmio_set_pending_reg, | |
879 | }, | |
880 | { | |
881 | .base = GIC_DIST_PENDING_CLEAR, | |
882 | .len = VGIC_NR_IRQS / 8, | |
883 | .handle_mmio = handle_mmio_clear_pending_reg, | |
884 | }, | |
885 | { | |
886 | .base = GIC_DIST_ACTIVE_SET, | |
887 | .len = VGIC_NR_IRQS / 8, | |
888 | .handle_mmio = handle_mmio_raz_wi, | |
889 | }, | |
890 | { | |
891 | .base = GIC_DIST_ACTIVE_CLEAR, | |
892 | .len = VGIC_NR_IRQS / 8, | |
893 | .handle_mmio = handle_mmio_raz_wi, | |
894 | }, | |
895 | { | |
896 | .base = GIC_DIST_PRI, | |
897 | .len = VGIC_NR_IRQS, | |
898 | .handle_mmio = handle_mmio_priority_reg, | |
899 | }, | |
900 | { | |
901 | .base = GIC_DIST_TARGET, | |
902 | .len = VGIC_NR_IRQS, | |
903 | .handle_mmio = handle_mmio_target_reg, | |
904 | }, | |
905 | { | |
906 | .base = GIC_DIST_CONFIG, | |
907 | .len = VGIC_NR_IRQS / 4, | |
908 | .handle_mmio = handle_mmio_cfg_reg, | |
909 | }, | |
910 | { | |
911 | .base = GIC_DIST_SOFTINT, | |
912 | .len = 4, | |
913 | .handle_mmio = handle_mmio_sgi_reg, | |
914 | }, | |
c07a0191 CD |
915 | { |
916 | .base = GIC_DIST_SGI_PENDING_CLEAR, | |
917 | .len = VGIC_NR_SGIS, | |
918 | .handle_mmio = handle_mmio_sgi_clear, | |
919 | }, | |
920 | { | |
921 | .base = GIC_DIST_SGI_PENDING_SET, | |
922 | .len = VGIC_NR_SGIS, | |
923 | .handle_mmio = handle_mmio_sgi_set, | |
924 | }, | |
1a89dd91 MZ |
925 | {} |
926 | }; | |
927 | ||
928 | static const | |
929 | struct mmio_range *find_matching_range(const struct mmio_range *ranges, | |
930 | struct kvm_exit_mmio *mmio, | |
1006e8cb | 931 | phys_addr_t offset) |
1a89dd91 MZ |
932 | { |
933 | const struct mmio_range *r = ranges; | |
1a89dd91 MZ |
934 | |
935 | while (r->len) { | |
1006e8cb CD |
936 | if (offset >= r->base && |
937 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
938 | return r; |
939 | r++; | |
940 | } | |
941 | ||
942 | return NULL; | |
943 | } | |
944 | ||
945 | /** | |
946 | * vgic_handle_mmio - handle an in-kernel MMIO access | |
947 | * @vcpu: pointer to the vcpu performing the access | |
948 | * @run: pointer to the kvm_run structure | |
949 | * @mmio: pointer to the data describing the access | |
950 | * | |
951 | * returns true if the MMIO access has been performed in kernel space, | |
952 | * and false if it needs to be emulated in user space. | |
953 | */ | |
954 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
955 | struct kvm_exit_mmio *mmio) | |
956 | { | |
b47ef92a MZ |
957 | const struct mmio_range *range; |
958 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
959 | unsigned long base = dist->vgic_dist_base; | |
960 | bool updated_state; | |
961 | unsigned long offset; | |
962 | ||
963 | if (!irqchip_in_kernel(vcpu->kvm) || | |
964 | mmio->phys_addr < base || | |
965 | (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE)) | |
966 | return false; | |
967 | ||
968 | /* We don't support ldrd / strd or ldm / stm to the emulated vgic */ | |
969 | if (mmio->len > 4) { | |
970 | kvm_inject_dabt(vcpu, mmio->phys_addr); | |
971 | return true; | |
972 | } | |
973 | ||
1006e8cb CD |
974 | offset = mmio->phys_addr - base; |
975 | range = find_matching_range(vgic_dist_ranges, mmio, offset); | |
b47ef92a MZ |
976 | if (unlikely(!range || !range->handle_mmio)) { |
977 | pr_warn("Unhandled access %d %08llx %d\n", | |
978 | mmio->is_write, mmio->phys_addr, mmio->len); | |
979 | return false; | |
980 | } | |
981 | ||
982 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
983 | offset = mmio->phys_addr - range->base - base; | |
984 | updated_state = range->handle_mmio(vcpu, mmio, offset); | |
985 | spin_unlock(&vcpu->kvm->arch.vgic.lock); | |
986 | kvm_prepare_mmio(run, mmio); | |
987 | kvm_handle_mmio_return(vcpu, run); | |
988 | ||
5863c2ce MZ |
989 | if (updated_state) |
990 | vgic_kick_vcpus(vcpu->kvm); | |
991 | ||
b47ef92a MZ |
992 | return true; |
993 | } | |
994 | ||
995 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) | |
996 | { | |
997 | struct kvm *kvm = vcpu->kvm; | |
998 | struct vgic_dist *dist = &kvm->arch.vgic; | |
999 | int nrcpus = atomic_read(&kvm->online_vcpus); | |
1000 | u8 target_cpus; | |
1001 | int sgi, mode, c, vcpu_id; | |
1002 | ||
1003 | vcpu_id = vcpu->vcpu_id; | |
1004 | ||
1005 | sgi = reg & 0xf; | |
1006 | target_cpus = (reg >> 16) & 0xff; | |
1007 | mode = (reg >> 24) & 3; | |
1008 | ||
1009 | switch (mode) { | |
1010 | case 0: | |
1011 | if (!target_cpus) | |
1012 | return; | |
91021a6c | 1013 | break; |
b47ef92a MZ |
1014 | |
1015 | case 1: | |
1016 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; | |
1017 | break; | |
1018 | ||
1019 | case 2: | |
1020 | target_cpus = 1 << vcpu_id; | |
1021 | break; | |
1022 | } | |
1023 | ||
1024 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1025 | if (target_cpus & 1) { | |
1026 | /* Flag the SGI as pending */ | |
227844f5 | 1027 | vgic_dist_irq_set_pending(vcpu, sgi); |
b47ef92a MZ |
1028 | dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id; |
1029 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); | |
1030 | } | |
1031 | ||
1032 | target_cpus >>= 1; | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) | |
1037 | { | |
9d949dce MZ |
1038 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1039 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
1040 | unsigned long pending_private, pending_shared; | |
1041 | int vcpu_id; | |
1042 | ||
1043 | vcpu_id = vcpu->vcpu_id; | |
1044 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
1045 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
1046 | ||
227844f5 | 1047 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
1048 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
1049 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
1050 | ||
227844f5 | 1051 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce MZ |
1052 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
1053 | bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS); | |
1054 | bitmap_and(pend_shared, pend_shared, | |
1055 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
1056 | VGIC_NR_SHARED_IRQS); | |
1057 | ||
1058 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
1059 | pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS); | |
1060 | return (pending_private < VGIC_NR_PRIVATE_IRQS || | |
1061 | pending_shared < VGIC_NR_SHARED_IRQS); | |
b47ef92a MZ |
1062 | } |
1063 | ||
1064 | /* | |
1065 | * Update the interrupt state and determine which CPUs have pending | |
1066 | * interrupts. Must be called with distributor lock held. | |
1067 | */ | |
1068 | static void vgic_update_state(struct kvm *kvm) | |
1069 | { | |
1070 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1071 | struct kvm_vcpu *vcpu; | |
1072 | int c; | |
1073 | ||
1074 | if (!dist->enabled) { | |
1075 | set_bit(0, &dist->irq_pending_on_cpu); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1080 | if (compute_pending_for_cpu(vcpu)) { | |
1081 | pr_debug("CPU%d has pending interrupts\n", c); | |
1082 | set_bit(c, &dist->irq_pending_on_cpu); | |
1083 | } | |
1084 | } | |
1a89dd91 | 1085 | } |
330690cd | 1086 | |
8d5c6b06 MZ |
1087 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
1088 | { | |
8f186d52 | 1089 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
1090 | } |
1091 | ||
1092 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
1093 | struct vgic_lr vlr) | |
1094 | { | |
8f186d52 | 1095 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
1096 | } |
1097 | ||
69bb2c9f MZ |
1098 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
1099 | struct vgic_lr vlr) | |
1100 | { | |
8f186d52 | 1101 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
1102 | } |
1103 | ||
1104 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
1105 | { | |
8f186d52 | 1106 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
1107 | } |
1108 | ||
8d6a0313 MZ |
1109 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
1110 | { | |
8f186d52 | 1111 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1112 | } |
1113 | ||
495dd859 MZ |
1114 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1115 | { | |
8f186d52 | 1116 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1117 | } |
1118 | ||
909d9b50 MZ |
1119 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1120 | { | |
8f186d52 | 1121 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1122 | } |
1123 | ||
1124 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1125 | { | |
8f186d52 | 1126 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1127 | } |
1128 | ||
beee38b9 MZ |
1129 | static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
1130 | { | |
8f186d52 | 1131 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1132 | } |
1133 | ||
1134 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) | |
1135 | { | |
8f186d52 | 1136 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1137 | } |
1138 | ||
da8dafd1 MZ |
1139 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1140 | { | |
8f186d52 | 1141 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1142 | } |
1143 | ||
8d5c6b06 MZ |
1144 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1145 | { | |
1146 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1147 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1148 | ||
1149 | vlr.state = 0; | |
1150 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1151 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1152 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1153 | } | |
a1fcb44e MZ |
1154 | |
1155 | /* | |
1156 | * An interrupt may have been disabled after being made pending on the | |
1157 | * CPU interface (the classic case is a timer running while we're | |
1158 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1159 | * interface gets enabled, with deadly consequences). | |
1160 | * | |
1161 | * The solution is to examine already active LRs, and check the | |
1162 | * interrupt is still enabled. If not, just retire it. | |
1163 | */ | |
1164 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1165 | { | |
1166 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1167 | int lr; | |
1168 | ||
8f186d52 | 1169 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1170 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1171 | |
8d5c6b06 MZ |
1172 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1173 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1174 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1175 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1176 | } |
1177 | } | |
1178 | } | |
1179 | ||
9d949dce MZ |
1180 | /* |
1181 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1182 | * or false if it wasn't possible to queue it. | |
1183 | */ | |
1184 | static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |
1185 | { | |
1186 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
8d5c6b06 | 1187 | struct vgic_lr vlr; |
9d949dce MZ |
1188 | int lr; |
1189 | ||
1190 | /* Sanitize the input... */ | |
1191 | BUG_ON(sgi_source_id & ~7); | |
1192 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
1193 | BUG_ON(irq >= VGIC_NR_IRQS); | |
1194 | ||
1195 | kvm_debug("Queue IRQ%d\n", irq); | |
1196 | ||
1197 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1198 | ||
1199 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1200 | if (lr != LR_EMPTY) { |
1201 | vlr = vgic_get_lr(vcpu, lr); | |
1202 | if (vlr.source == sgi_source_id) { | |
1203 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1204 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
1205 | vlr.state |= LR_STATE_PENDING; | |
1206 | vgic_set_lr(vcpu, lr, vlr); | |
1207 | return true; | |
1208 | } | |
9d949dce MZ |
1209 | } |
1210 | ||
1211 | /* Try to use another LR for this interrupt */ | |
1212 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1213 | vgic->nr_lr); |
1214 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1215 | return false; |
1216 | ||
1217 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1218 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1219 | set_bit(lr, vgic_cpu->lr_used); | |
1220 | ||
8d5c6b06 MZ |
1221 | vlr.irq = irq; |
1222 | vlr.source = sgi_source_id; | |
1223 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 1224 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
1225 | vlr.state |= LR_EOI_INT; |
1226 | ||
1227 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1228 | |
1229 | return true; | |
1230 | } | |
1231 | ||
1232 | static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
1233 | { | |
1234 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1235 | unsigned long sources; | |
1236 | int vcpu_id = vcpu->vcpu_id; | |
1237 | int c; | |
1238 | ||
1239 | sources = dist->irq_sgi_sources[vcpu_id][irq]; | |
1240 | ||
1241 | for_each_set_bit(c, &sources, VGIC_MAX_CPUS) { | |
1242 | if (vgic_queue_irq(vcpu, c, irq)) | |
1243 | clear_bit(c, &sources); | |
1244 | } | |
1245 | ||
1246 | dist->irq_sgi_sources[vcpu_id][irq] = sources; | |
1247 | ||
1248 | /* | |
1249 | * If the sources bitmap has been cleared it means that we | |
1250 | * could queue all the SGIs onto link registers (see the | |
1251 | * clear_bit above), and therefore we are done with them in | |
1252 | * our emulated gic and can get rid of them. | |
1253 | */ | |
1254 | if (!sources) { | |
227844f5 | 1255 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1256 | vgic_cpu_irq_clear(vcpu, irq); |
1257 | return true; | |
1258 | } | |
1259 | ||
1260 | return false; | |
1261 | } | |
1262 | ||
1263 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) | |
1264 | { | |
dbf20f9d | 1265 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1266 | return true; /* level interrupt, already queued */ |
1267 | ||
1268 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1269 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1270 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1271 | vgic_cpu_irq_clear(vcpu, irq); |
1272 | } else { | |
dbf20f9d | 1273 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1274 | } |
1275 | ||
1276 | return true; | |
1277 | } | |
1278 | ||
1279 | return false; | |
1280 | } | |
1281 | ||
1282 | /* | |
1283 | * Fill the list registers with pending interrupts before running the | |
1284 | * guest. | |
1285 | */ | |
1286 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1287 | { | |
1288 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1289 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1290 | int i, vcpu_id; | |
1291 | int overflow = 0; | |
1292 | ||
1293 | vcpu_id = vcpu->vcpu_id; | |
1294 | ||
1295 | /* | |
1296 | * We may not have any pending interrupt, or the interrupts | |
1297 | * may have been serviced from another vcpu. In all cases, | |
1298 | * move along. | |
1299 | */ | |
1300 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1301 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1302 | goto epilog; | |
1303 | } | |
1304 | ||
1305 | /* SGIs */ | |
1306 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
1307 | if (!vgic_queue_sgi(vcpu, i)) | |
1308 | overflow = 1; | |
1309 | } | |
1310 | ||
1311 | /* PPIs */ | |
1312 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1313 | if (!vgic_queue_hwirq(vcpu, i)) | |
1314 | overflow = 1; | |
1315 | } | |
1316 | ||
1317 | /* SPIs */ | |
1318 | for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) { | |
1319 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) | |
1320 | overflow = 1; | |
1321 | } | |
1322 | ||
1323 | epilog: | |
1324 | if (overflow) { | |
909d9b50 | 1325 | vgic_enable_underflow(vcpu); |
9d949dce | 1326 | } else { |
909d9b50 | 1327 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1328 | /* |
1329 | * We're about to run this VCPU, and we've consumed | |
1330 | * everything the distributor had in store for | |
1331 | * us. Claim we don't have anything pending. We'll | |
1332 | * adjust that if needed while exiting. | |
1333 | */ | |
1334 | clear_bit(vcpu_id, &dist->irq_pending_on_cpu); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1339 | { | |
495dd859 | 1340 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1341 | bool level_pending = false; |
1342 | ||
495dd859 | 1343 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1344 | |
495dd859 | 1345 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1346 | /* |
1347 | * Some level interrupts have been EOIed. Clear their | |
1348 | * active bit. | |
1349 | */ | |
8d6a0313 MZ |
1350 | u64 eisr = vgic_get_eisr(vcpu); |
1351 | unsigned long *eisr_ptr = (unsigned long *)&eisr; | |
8d5c6b06 | 1352 | int lr; |
9d949dce | 1353 | |
8f186d52 | 1354 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1355 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1356 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1357 | |
dbf20f9d | 1358 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1359 | WARN_ON(vlr.state & LR_STATE_MASK); |
1360 | vlr.state = 0; | |
1361 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1362 | |
faa1b46c CD |
1363 | /* |
1364 | * If the IRQ was EOIed it was also ACKed and we we | |
1365 | * therefore assume we can clear the soft pending | |
1366 | * state (should it had been set) for this interrupt. | |
1367 | * | |
1368 | * Note: if the IRQ soft pending state was set after | |
1369 | * the IRQ was acked, it actually shouldn't be | |
1370 | * cleared, but we have no way of knowing that unless | |
1371 | * we start trapping ACKs when the soft-pending state | |
1372 | * is set. | |
1373 | */ | |
1374 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1375 | ||
9d949dce | 1376 | /* Any additional pending interrupt? */ |
faa1b46c | 1377 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1378 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1379 | level_pending = true; |
1380 | } else { | |
faa1b46c | 1381 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1382 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1383 | } |
75da01e1 MZ |
1384 | |
1385 | /* | |
1386 | * Despite being EOIed, the LR may not have | |
1387 | * been marked as empty. | |
1388 | */ | |
69bb2c9f | 1389 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1390 | } |
1391 | } | |
1392 | ||
495dd859 | 1393 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1394 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1395 | |
1396 | return level_pending; | |
1397 | } | |
1398 | ||
1399 | /* | |
33c83cb3 MZ |
1400 | * Sync back the VGIC state after a guest run. The distributor lock is |
1401 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1402 | */ |
1403 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1404 | { | |
1405 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1406 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1407 | u64 elrsr; |
1408 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1409 | int lr, pending; |
1410 | bool level_pending; | |
1411 | ||
1412 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f MZ |
1413 | elrsr = vgic_get_elrsr(vcpu); |
1414 | elrsr_ptr = (unsigned long *)&elrsr; | |
9d949dce MZ |
1415 | |
1416 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1417 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1418 | struct vgic_lr vlr; |
9d949dce MZ |
1419 | |
1420 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1421 | continue; | |
1422 | ||
8d5c6b06 | 1423 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1424 | |
8d5c6b06 MZ |
1425 | BUG_ON(vlr.irq >= VGIC_NR_IRQS); |
1426 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; | |
9d949dce MZ |
1427 | } |
1428 | ||
1429 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1430 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1431 | if (level_pending || pending < vgic->nr_lr) | |
9d949dce MZ |
1432 | set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); |
1433 | } | |
1434 | ||
1435 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1436 | { | |
1437 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1438 | ||
1439 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1440 | return; | |
1441 | ||
1442 | spin_lock(&dist->lock); | |
1443 | __kvm_vgic_flush_hwstate(vcpu); | |
1444 | spin_unlock(&dist->lock); | |
1445 | } | |
1446 | ||
1447 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1448 | { | |
33c83cb3 MZ |
1449 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1450 | ||
9d949dce MZ |
1451 | if (!irqchip_in_kernel(vcpu->kvm)) |
1452 | return; | |
1453 | ||
33c83cb3 | 1454 | spin_lock(&dist->lock); |
9d949dce | 1455 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1456 | spin_unlock(&dist->lock); |
9d949dce MZ |
1457 | } |
1458 | ||
1459 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1460 | { | |
1461 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1462 | ||
1463 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1464 | return 0; | |
1465 | ||
1466 | return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); | |
1467 | } | |
1468 | ||
5863c2ce MZ |
1469 | static void vgic_kick_vcpus(struct kvm *kvm) |
1470 | { | |
1471 | struct kvm_vcpu *vcpu; | |
1472 | int c; | |
1473 | ||
1474 | /* | |
1475 | * We've injected an interrupt, time to find out who deserves | |
1476 | * a good kick... | |
1477 | */ | |
1478 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1479 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1480 | kvm_vcpu_kick(vcpu); | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1485 | { | |
227844f5 | 1486 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1487 | |
1488 | /* | |
1489 | * Only inject an interrupt if: | |
1490 | * - edge triggered and we have a rising edge | |
1491 | * - level triggered and we change level | |
1492 | */ | |
faa1b46c CD |
1493 | if (edge_triggered) { |
1494 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1495 | return level > state; |
faa1b46c CD |
1496 | } else { |
1497 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1498 | return level != state; |
faa1b46c | 1499 | } |
5863c2ce MZ |
1500 | } |
1501 | ||
227844f5 | 1502 | static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1503 | unsigned int irq_num, bool level) |
1504 | { | |
1505 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1506 | struct kvm_vcpu *vcpu; | |
227844f5 | 1507 | int edge_triggered, level_triggered; |
5863c2ce MZ |
1508 | int enabled; |
1509 | bool ret = true; | |
1510 | ||
1511 | spin_lock(&dist->lock); | |
1512 | ||
1513 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1514 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1515 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1516 | |
1517 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1518 | ret = false; | |
1519 | goto out; | |
1520 | } | |
1521 | ||
1522 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1523 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
1524 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1525 | } | |
1526 | ||
1527 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1528 | ||
faa1b46c CD |
1529 | if (level) { |
1530 | if (level_triggered) | |
1531 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1532 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1533 | } else { |
1534 | if (level_triggered) { | |
1535 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1536 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1537 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
1538 | } else { | |
1539 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
1540 | } | |
1541 | } | |
5863c2ce MZ |
1542 | |
1543 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1544 | ||
1545 | if (!enabled) { | |
1546 | ret = false; | |
1547 | goto out; | |
1548 | } | |
1549 | ||
dbf20f9d | 1550 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1551 | /* |
1552 | * Level interrupt in progress, will be picked up | |
1553 | * when EOId. | |
1554 | */ | |
1555 | ret = false; | |
1556 | goto out; | |
1557 | } | |
1558 | ||
1559 | if (level) { | |
1560 | vgic_cpu_irq_set(vcpu, irq_num); | |
1561 | set_bit(cpuid, &dist->irq_pending_on_cpu); | |
1562 | } | |
1563 | ||
1564 | out: | |
1565 | spin_unlock(&dist->lock); | |
1566 | ||
1567 | return ret; | |
1568 | } | |
1569 | ||
1570 | /** | |
1571 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1572 | * @kvm: The VM structure pointer | |
1573 | * @cpuid: The CPU for PPIs | |
1574 | * @irq_num: The IRQ number that is assigned to the device | |
1575 | * @level: Edge-triggered: true: to trigger the interrupt | |
1576 | * false: to ignore the call | |
1577 | * Level-sensitive true: activates an interrupt | |
1578 | * false: deactivates an interrupt | |
1579 | * | |
1580 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1581 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1582 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1583 | */ | |
1584 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1585 | bool level) | |
1586 | { | |
227844f5 | 1587 | if (vgic_update_irq_pending(kvm, cpuid, irq_num, level)) |
5863c2ce MZ |
1588 | vgic_kick_vcpus(kvm); |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
01ac5e34 MZ |
1593 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1594 | { | |
1595 | /* | |
1596 | * We cannot rely on the vgic maintenance interrupt to be | |
1597 | * delivered synchronously. This means we can only use it to | |
1598 | * exit the VM, and we perform the handling of EOIed | |
1599 | * interrupts on the exit path (see vgic_process_maintenance). | |
1600 | */ | |
1601 | return IRQ_HANDLED; | |
1602 | } | |
1603 | ||
e1ba0207 CD |
1604 | /** |
1605 | * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state | |
1606 | * @vcpu: pointer to the vcpu struct | |
1607 | * | |
1608 | * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to | |
1609 | * this vcpu and enable the VGIC for this VCPU | |
1610 | */ | |
01ac5e34 MZ |
1611 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) |
1612 | { | |
1613 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1614 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1615 | int i; | |
1616 | ||
01ac5e34 MZ |
1617 | if (vcpu->vcpu_id >= VGIC_MAX_CPUS) |
1618 | return -EBUSY; | |
1619 | ||
1620 | for (i = 0; i < VGIC_NR_IRQS; i++) { | |
1621 | if (i < VGIC_NR_PPIS) | |
1622 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1623 | vcpu->vcpu_id, i, 1); | |
1624 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1625 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1626 | vcpu->vcpu_id, i, VGIC_CFG_EDGE); | |
1627 | ||
1628 | vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY; | |
1629 | } | |
1630 | ||
1631 | /* | |
ca85f623 MZ |
1632 | * Store the number of LRs per vcpu, so we don't have to go |
1633 | * all the way to the distributor structure to find out. Only | |
1634 | * assembly code should use this one. | |
01ac5e34 | 1635 | */ |
8f186d52 | 1636 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1637 | |
da8dafd1 | 1638 | vgic_enable(vcpu); |
01ac5e34 MZ |
1639 | |
1640 | return 0; | |
1641 | } | |
1642 | ||
e1ba0207 CD |
1643 | /** |
1644 | * kvm_vgic_init - Initialize global VGIC state before running any VCPUs | |
1645 | * @kvm: pointer to the kvm struct | |
1646 | * | |
1647 | * Map the virtual CPU interface into the VM before running any VCPUs. We | |
1648 | * can't do this at creation time, because user space must first set the | |
1649 | * virtual CPU interface address in the guest physical address space. Also | |
1650 | * initialize the ITARGETSRn regs to 0 on the emulated distributor. | |
1651 | */ | |
01ac5e34 MZ |
1652 | int kvm_vgic_init(struct kvm *kvm) |
1653 | { | |
1654 | int ret = 0, i; | |
1655 | ||
e1ba0207 CD |
1656 | if (!irqchip_in_kernel(kvm)) |
1657 | return 0; | |
1658 | ||
01ac5e34 MZ |
1659 | mutex_lock(&kvm->lock); |
1660 | ||
1661 | if (vgic_initialized(kvm)) | |
1662 | goto out; | |
1663 | ||
1664 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || | |
1665 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { | |
1666 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
1667 | ret = -ENXIO; | |
1668 | goto out; | |
1669 | } | |
1670 | ||
1671 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, | |
8f186d52 | 1672 | vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE); |
01ac5e34 MZ |
1673 | if (ret) { |
1674 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
1675 | goto out; | |
1676 | } | |
1677 | ||
1678 | for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4) | |
1679 | vgic_set_target_reg(kvm, 0, i); | |
1680 | ||
1681 | kvm->arch.vgic.ready = true; | |
1682 | out: | |
1683 | mutex_unlock(&kvm->lock); | |
1684 | return ret; | |
1685 | } | |
1686 | ||
1687 | int kvm_vgic_create(struct kvm *kvm) | |
1688 | { | |
7330672b CD |
1689 | int i, vcpu_lock_idx = -1, ret = 0; |
1690 | struct kvm_vcpu *vcpu; | |
01ac5e34 MZ |
1691 | |
1692 | mutex_lock(&kvm->lock); | |
1693 | ||
7330672b | 1694 | if (kvm->arch.vgic.vctrl_base) { |
01ac5e34 MZ |
1695 | ret = -EEXIST; |
1696 | goto out; | |
1697 | } | |
1698 | ||
7330672b CD |
1699 | /* |
1700 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1701 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1702 | * that no other VCPUs are run while we create the vgic. | |
1703 | */ | |
1704 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1705 | if (!mutex_trylock(&vcpu->mutex)) | |
1706 | goto out_unlock; | |
1707 | vcpu_lock_idx = i; | |
1708 | } | |
1709 | ||
1710 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1711 | if (vcpu->arch.has_run_once) { | |
1712 | ret = -EBUSY; | |
1713 | goto out_unlock; | |
1714 | } | |
1715 | } | |
1716 | ||
01ac5e34 | 1717 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1718 | kvm->arch.vgic.in_kernel = true; |
8f186d52 | 1719 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1720 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1721 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
1722 | ||
7330672b CD |
1723 | out_unlock: |
1724 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1725 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1726 | mutex_unlock(&vcpu->mutex); | |
1727 | } | |
1728 | ||
01ac5e34 MZ |
1729 | out: |
1730 | mutex_unlock(&kvm->lock); | |
1731 | return ret; | |
1732 | } | |
1733 | ||
1fa451bc | 1734 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
1735 | { |
1736 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1737 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1738 | ||
1739 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1740 | return 0; | |
1741 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1742 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1743 | return -EBUSY; | |
1744 | return 0; | |
1745 | } | |
1746 | ||
1747 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1748 | phys_addr_t addr, phys_addr_t size) | |
1749 | { | |
1750 | int ret; | |
1751 | ||
ce01e4e8 CD |
1752 | if (addr & ~KVM_PHYS_MASK) |
1753 | return -E2BIG; | |
1754 | ||
1755 | if (addr & (SZ_4K - 1)) | |
1756 | return -EINVAL; | |
1757 | ||
330690cd CD |
1758 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1759 | return -EEXIST; | |
1760 | if (addr + size < addr) | |
1761 | return -EINVAL; | |
1762 | ||
30c21170 | 1763 | *ioaddr = addr; |
330690cd CD |
1764 | ret = vgic_ioaddr_overlap(kvm); |
1765 | if (ret) | |
30c21170 HW |
1766 | *ioaddr = VGIC_ADDR_UNDEF; |
1767 | ||
330690cd CD |
1768 | return ret; |
1769 | } | |
1770 | ||
ce01e4e8 CD |
1771 | /** |
1772 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1773 | * @kvm: pointer to the vm struct | |
1774 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX | |
1775 | * @addr: pointer to address value | |
1776 | * @write: if true set the address in the VM address space, if false read the | |
1777 | * address | |
1778 | * | |
1779 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1780 | * interface in the VM physical address space. These addresses are properties | |
1781 | * of the emulated core/SoC and therefore user space initially knows this | |
1782 | * information. | |
1783 | */ | |
1784 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1785 | { |
1786 | int r = 0; | |
1787 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
1788 | ||
330690cd CD |
1789 | mutex_lock(&kvm->lock); |
1790 | switch (type) { | |
1791 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ce01e4e8 CD |
1792 | if (write) { |
1793 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, | |
1794 | *addr, KVM_VGIC_V2_DIST_SIZE); | |
1795 | } else { | |
1796 | *addr = vgic->vgic_dist_base; | |
1797 | } | |
330690cd CD |
1798 | break; |
1799 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ce01e4e8 CD |
1800 | if (write) { |
1801 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, | |
1802 | *addr, KVM_VGIC_V2_CPU_SIZE); | |
1803 | } else { | |
1804 | *addr = vgic->vgic_cpu_base; | |
1805 | } | |
330690cd CD |
1806 | break; |
1807 | default: | |
1808 | r = -ENODEV; | |
1809 | } | |
1810 | ||
1811 | mutex_unlock(&kvm->lock); | |
1812 | return r; | |
1813 | } | |
7330672b | 1814 | |
c07a0191 CD |
1815 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
1816 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1817 | { | |
fa20f5ae | 1818 | bool updated = false; |
beee38b9 MZ |
1819 | struct vgic_vmcr vmcr; |
1820 | u32 *vmcr_field; | |
1821 | u32 reg; | |
1822 | ||
1823 | vgic_get_vmcr(vcpu, &vmcr); | |
fa20f5ae CD |
1824 | |
1825 | switch (offset & ~0x3) { | |
1826 | case GIC_CPU_CTRL: | |
beee38b9 | 1827 | vmcr_field = &vmcr.ctlr; |
fa20f5ae CD |
1828 | break; |
1829 | case GIC_CPU_PRIMASK: | |
beee38b9 | 1830 | vmcr_field = &vmcr.pmr; |
fa20f5ae CD |
1831 | break; |
1832 | case GIC_CPU_BINPOINT: | |
beee38b9 | 1833 | vmcr_field = &vmcr.bpr; |
fa20f5ae CD |
1834 | break; |
1835 | case GIC_CPU_ALIAS_BINPOINT: | |
beee38b9 | 1836 | vmcr_field = &vmcr.abpr; |
fa20f5ae | 1837 | break; |
beee38b9 MZ |
1838 | default: |
1839 | BUG(); | |
fa20f5ae CD |
1840 | } |
1841 | ||
1842 | if (!mmio->is_write) { | |
beee38b9 | 1843 | reg = *vmcr_field; |
fa20f5ae CD |
1844 | mmio_data_write(mmio, ~0, reg); |
1845 | } else { | |
1846 | reg = mmio_data_read(mmio, ~0); | |
beee38b9 MZ |
1847 | if (reg != *vmcr_field) { |
1848 | *vmcr_field = reg; | |
1849 | vgic_set_vmcr(vcpu, &vmcr); | |
fa20f5ae | 1850 | updated = true; |
beee38b9 | 1851 | } |
fa20f5ae CD |
1852 | } |
1853 | return updated; | |
1854 | } | |
1855 | ||
1856 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, | |
1857 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1858 | { | |
1859 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); | |
c07a0191 CD |
1860 | } |
1861 | ||
fa20f5ae CD |
1862 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
1863 | struct kvm_exit_mmio *mmio, | |
1864 | phys_addr_t offset) | |
1865 | { | |
1866 | u32 reg; | |
1867 | ||
1868 | if (mmio->is_write) | |
1869 | return false; | |
1870 | ||
1871 | /* GICC_IIDR */ | |
1872 | reg = (PRODUCT_ID_KVM << 20) | | |
1873 | (GICC_ARCH_VERSION_V2 << 16) | | |
1874 | (IMPLEMENTER_ARM << 0); | |
1875 | mmio_data_write(mmio, ~0, reg); | |
1876 | return false; | |
1877 | } | |
1878 | ||
1879 | /* | |
1880 | * CPU Interface Register accesses - these are not accessed by the VM, but by | |
1881 | * user space for saving and restoring VGIC state. | |
1882 | */ | |
c07a0191 CD |
1883 | static const struct mmio_range vgic_cpu_ranges[] = { |
1884 | { | |
1885 | .base = GIC_CPU_CTRL, | |
1886 | .len = 12, | |
1887 | .handle_mmio = handle_cpu_mmio_misc, | |
1888 | }, | |
1889 | { | |
1890 | .base = GIC_CPU_ALIAS_BINPOINT, | |
1891 | .len = 4, | |
fa20f5ae | 1892 | .handle_mmio = handle_mmio_abpr, |
c07a0191 CD |
1893 | }, |
1894 | { | |
1895 | .base = GIC_CPU_ACTIVEPRIO, | |
1896 | .len = 16, | |
fa20f5ae | 1897 | .handle_mmio = handle_mmio_raz_wi, |
c07a0191 CD |
1898 | }, |
1899 | { | |
1900 | .base = GIC_CPU_IDENT, | |
1901 | .len = 4, | |
fa20f5ae | 1902 | .handle_mmio = handle_cpu_mmio_ident, |
c07a0191 CD |
1903 | }, |
1904 | }; | |
1905 | ||
1906 | static int vgic_attr_regs_access(struct kvm_device *dev, | |
1907 | struct kvm_device_attr *attr, | |
1908 | u32 *reg, bool is_write) | |
1909 | { | |
1910 | const struct mmio_range *r = NULL, *ranges; | |
1911 | phys_addr_t offset; | |
1912 | int ret, cpuid, c; | |
1913 | struct kvm_vcpu *vcpu, *tmp_vcpu; | |
1914 | struct vgic_dist *vgic; | |
1915 | struct kvm_exit_mmio mmio; | |
1916 | ||
1917 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
1918 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> | |
1919 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; | |
1920 | ||
1921 | mutex_lock(&dev->kvm->lock); | |
1922 | ||
1923 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { | |
1924 | ret = -EINVAL; | |
1925 | goto out; | |
1926 | } | |
1927 | ||
1928 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); | |
1929 | vgic = &dev->kvm->arch.vgic; | |
1930 | ||
1931 | mmio.len = 4; | |
1932 | mmio.is_write = is_write; | |
1933 | if (is_write) | |
1934 | mmio_data_write(&mmio, ~0, *reg); | |
1935 | switch (attr->group) { | |
1936 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1937 | mmio.phys_addr = vgic->vgic_dist_base + offset; | |
1938 | ranges = vgic_dist_ranges; | |
1939 | break; | |
1940 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
1941 | mmio.phys_addr = vgic->vgic_cpu_base + offset; | |
1942 | ranges = vgic_cpu_ranges; | |
1943 | break; | |
1944 | default: | |
1945 | BUG(); | |
1946 | } | |
1947 | r = find_matching_range(ranges, &mmio, offset); | |
1948 | ||
1949 | if (unlikely(!r || !r->handle_mmio)) { | |
1950 | ret = -ENXIO; | |
1951 | goto out; | |
1952 | } | |
1953 | ||
1954 | ||
1955 | spin_lock(&vgic->lock); | |
1956 | ||
1957 | /* | |
1958 | * Ensure that no other VCPU is running by checking the vcpu->cpu | |
1959 | * field. If no other VPCUs are running we can safely access the VGIC | |
1960 | * state, because even if another VPU is run after this point, that | |
1961 | * VCPU will not touch the vgic state, because it will block on | |
1962 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). | |
1963 | */ | |
1964 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { | |
1965 | if (unlikely(tmp_vcpu->cpu != -1)) { | |
1966 | ret = -EBUSY; | |
1967 | goto out_vgic_unlock; | |
1968 | } | |
1969 | } | |
1970 | ||
cbd333a4 CD |
1971 | /* |
1972 | * Move all pending IRQs from the LRs on all VCPUs so the pending | |
1973 | * state can be properly represented in the register state accessible | |
1974 | * through this API. | |
1975 | */ | |
1976 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) | |
1977 | vgic_unqueue_irqs(tmp_vcpu); | |
1978 | ||
c07a0191 CD |
1979 | offset -= r->base; |
1980 | r->handle_mmio(vcpu, &mmio, offset); | |
1981 | ||
1982 | if (!is_write) | |
1983 | *reg = mmio_data_read(&mmio, ~0); | |
1984 | ||
1985 | ret = 0; | |
1986 | out_vgic_unlock: | |
1987 | spin_unlock(&vgic->lock); | |
1988 | out: | |
1989 | mutex_unlock(&dev->kvm->lock); | |
1990 | return ret; | |
1991 | } | |
1992 | ||
7330672b CD |
1993 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
1994 | { | |
ce01e4e8 CD |
1995 | int r; |
1996 | ||
1997 | switch (attr->group) { | |
1998 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1999 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2000 | u64 addr; | |
2001 | unsigned long type = (unsigned long)attr->attr; | |
2002 | ||
2003 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
2004 | return -EFAULT; | |
2005 | ||
2006 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
2007 | return (r == -ENODEV) ? -ENXIO : r; | |
2008 | } | |
c07a0191 CD |
2009 | |
2010 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2011 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2012 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2013 | u32 reg; | |
2014 | ||
2015 | if (get_user(reg, uaddr)) | |
2016 | return -EFAULT; | |
2017 | ||
2018 | return vgic_attr_regs_access(dev, attr, ®, true); | |
2019 | } | |
2020 | ||
ce01e4e8 CD |
2021 | } |
2022 | ||
7330672b CD |
2023 | return -ENXIO; |
2024 | } | |
2025 | ||
2026 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
2027 | { | |
ce01e4e8 CD |
2028 | int r = -ENXIO; |
2029 | ||
2030 | switch (attr->group) { | |
2031 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2032 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2033 | u64 addr; | |
2034 | unsigned long type = (unsigned long)attr->attr; | |
2035 | ||
2036 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
2037 | if (r) | |
2038 | return (r == -ENODEV) ? -ENXIO : r; | |
2039 | ||
2040 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
2041 | return -EFAULT; | |
c07a0191 CD |
2042 | break; |
2043 | } | |
2044 | ||
2045 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2046 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2047 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2048 | u32 reg = 0; | |
2049 | ||
2050 | r = vgic_attr_regs_access(dev, attr, ®, false); | |
2051 | if (r) | |
2052 | return r; | |
2053 | r = put_user(reg, uaddr); | |
2054 | break; | |
ce01e4e8 | 2055 | } |
c07a0191 | 2056 | |
ce01e4e8 CD |
2057 | } |
2058 | ||
2059 | return r; | |
7330672b CD |
2060 | } |
2061 | ||
c07a0191 CD |
2062 | static int vgic_has_attr_regs(const struct mmio_range *ranges, |
2063 | phys_addr_t offset) | |
2064 | { | |
2065 | struct kvm_exit_mmio dev_attr_mmio; | |
2066 | ||
2067 | dev_attr_mmio.len = 4; | |
2068 | if (find_matching_range(ranges, &dev_attr_mmio, offset)) | |
2069 | return 0; | |
2070 | else | |
2071 | return -ENXIO; | |
2072 | } | |
2073 | ||
7330672b CD |
2074 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2075 | { | |
c07a0191 CD |
2076 | phys_addr_t offset; |
2077 | ||
ce01e4e8 CD |
2078 | switch (attr->group) { |
2079 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
2080 | switch (attr->attr) { | |
2081 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
2082 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
2083 | return 0; | |
2084 | } | |
2085 | break; | |
c07a0191 CD |
2086 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
2087 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2088 | return vgic_has_attr_regs(vgic_dist_ranges, offset); | |
2089 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2090 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2091 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); | |
ce01e4e8 | 2092 | } |
7330672b CD |
2093 | return -ENXIO; |
2094 | } | |
2095 | ||
2096 | static void vgic_destroy(struct kvm_device *dev) | |
2097 | { | |
2098 | kfree(dev); | |
2099 | } | |
2100 | ||
2101 | static int vgic_create(struct kvm_device *dev, u32 type) | |
2102 | { | |
2103 | return kvm_vgic_create(dev->kvm); | |
2104 | } | |
2105 | ||
c06a841b | 2106 | static struct kvm_device_ops kvm_arm_vgic_v2_ops = { |
7330672b CD |
2107 | .name = "kvm-arm-vgic", |
2108 | .create = vgic_create, | |
2109 | .destroy = vgic_destroy, | |
2110 | .set_attr = vgic_set_attr, | |
2111 | .get_attr = vgic_get_attr, | |
2112 | .has_attr = vgic_has_attr, | |
2113 | }; | |
c06a841b WD |
2114 | |
2115 | static void vgic_init_maintenance_interrupt(void *info) | |
2116 | { | |
2117 | enable_percpu_irq(vgic->maint_irq, 0); | |
2118 | } | |
2119 | ||
2120 | static int vgic_cpu_notify(struct notifier_block *self, | |
2121 | unsigned long action, void *cpu) | |
2122 | { | |
2123 | switch (action) { | |
2124 | case CPU_STARTING: | |
2125 | case CPU_STARTING_FROZEN: | |
2126 | vgic_init_maintenance_interrupt(NULL); | |
2127 | break; | |
2128 | case CPU_DYING: | |
2129 | case CPU_DYING_FROZEN: | |
2130 | disable_percpu_irq(vgic->maint_irq); | |
2131 | break; | |
2132 | } | |
2133 | ||
2134 | return NOTIFY_OK; | |
2135 | } | |
2136 | ||
2137 | static struct notifier_block vgic_cpu_nb = { | |
2138 | .notifier_call = vgic_cpu_notify, | |
2139 | }; | |
2140 | ||
2141 | static const struct of_device_id vgic_ids[] = { | |
2142 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
2143 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
2144 | {}, | |
2145 | }; | |
2146 | ||
2147 | int kvm_vgic_hyp_init(void) | |
2148 | { | |
2149 | const struct of_device_id *matched_id; | |
a875dafc CD |
2150 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2151 | const struct vgic_params **); | |
c06a841b WD |
2152 | struct device_node *vgic_node; |
2153 | int ret; | |
2154 | ||
2155 | vgic_node = of_find_matching_node_and_match(NULL, | |
2156 | vgic_ids, &matched_id); | |
2157 | if (!vgic_node) { | |
2158 | kvm_err("error: no compatible GIC node found\n"); | |
2159 | return -ENODEV; | |
2160 | } | |
2161 | ||
2162 | vgic_probe = matched_id->data; | |
2163 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2164 | if (ret) | |
2165 | return ret; | |
2166 | ||
2167 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2168 | "vgic", kvm_get_running_vcpus()); | |
2169 | if (ret) { | |
2170 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2171 | return ret; | |
2172 | } | |
2173 | ||
2174 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2175 | if (ret) { | |
2176 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2177 | goto out_free_irq; | |
2178 | } | |
2179 | ||
2180 | /* Callback into for arch code for setup */ | |
2181 | vgic_arch_setup(vgic); | |
2182 | ||
2183 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
2184 | ||
2185 | return kvm_register_device_ops(&kvm_arm_vgic_v2_ops, | |
2186 | KVM_DEV_TYPE_ARM_VGIC_V2); | |
2187 | ||
2188 | out_free_irq: | |
2189 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2190 | return ret; | |
2191 | } |