Commit | Line | Data |
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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
174178fe | 34 | #include <trace/events/kvm.h> |
1a89dd91 | 35 | |
b47ef92a MZ |
36 | /* |
37 | * How the whole thing works (courtesy of Christoffer Dall): | |
38 | * | |
39 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
7e362919 CD |
40 | * something is pending on the CPU interface. |
41 | * - Interrupts that are pending on the distributor are stored on the | |
42 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land | |
43 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the | |
44 | * arch. timers). | |
b47ef92a MZ |
45 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
46 | * recalculated | |
47 | * - To calculate the oracle, we need info for each cpu from | |
48 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
49 | * - PPI: dist->irq_pending & dist->irq_enable |
50 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
7e362919 | 51 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
b47ef92a MZ |
52 | * registers, stored on each vcpu. We only keep one bit of |
53 | * information per interrupt, making sure that only one vcpu can | |
54 | * accept the interrupt. | |
7e362919 | 55 | * - If any of the above state changes, we must recalculate the oracle. |
b47ef92a MZ |
56 | * - The same is true when injecting an interrupt, except that we only |
57 | * consider a single interrupt at a time. The irq_spi_cpu array | |
58 | * contains the target CPU for each SPI. | |
59 | * | |
60 | * The handling of level interrupts adds some extra complexity. We | |
61 | * need to track when the interrupt has been EOIed, so we can sample | |
62 | * the 'line' again. This is achieved as such: | |
63 | * | |
64 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 65 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
66 | * will be ignored for further interrupts. The interrupt is injected |
67 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
68 | * maintenance interrupt on EOI). | |
69 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 70 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 71 | * interrupt line to be sampled again. |
faa1b46c CD |
72 | * - Note that level-triggered interrupts can also be set to pending from |
73 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
74 | * cause the interrupt to become inactive in such a situation. | |
75 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
76 | * inactive as long as the external input line is held high. | |
b47ef92a MZ |
77 | */ |
78 | ||
83215812 | 79 | #include "vgic.h" |
330690cd | 80 | |
a1fcb44e | 81 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 82 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
83 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
84 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
01ac5e34 | 85 | |
8f186d52 MZ |
86 | static const struct vgic_ops *vgic_ops; |
87 | static const struct vgic_params *vgic; | |
b47ef92a | 88 | |
b26e5fda AP |
89 | static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) |
90 | { | |
91 | vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source); | |
92 | } | |
93 | ||
94 | static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
95 | { | |
96 | return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); | |
97 | } | |
98 | ||
99 | int kvm_vgic_map_resources(struct kvm *kvm) | |
100 | { | |
101 | return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); | |
102 | } | |
103 | ||
9662fb48 | 104 | /* |
c1bfb577 MZ |
105 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
106 | * extracts u32s out of them. | |
9662fb48 VK |
107 | * |
108 | * This does not work on 64-bit BE systems, because the bitmap access | |
109 | * will store two consecutive 32-bit words with the higher-addressed | |
110 | * register's bits at the lower index and the lower-addressed register's | |
111 | * bits at the higher index. | |
112 | * | |
113 | * Therefore, swizzle the register index when accessing the 32-bit word | |
114 | * registers to access the right register's value. | |
115 | */ | |
116 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
117 | #define REG_OFFSET_SWIZZLE 1 | |
118 | #else | |
119 | #define REG_OFFSET_SWIZZLE 0 | |
120 | #endif | |
b47ef92a | 121 | |
c1bfb577 MZ |
122 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
123 | { | |
124 | int nr_longs; | |
125 | ||
126 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); | |
127 | ||
128 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); | |
129 | if (!b->private) | |
130 | return -ENOMEM; | |
131 | ||
132 | b->shared = b->private + nr_cpus; | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static void vgic_free_bitmap(struct vgic_bitmap *b) | |
138 | { | |
139 | kfree(b->private); | |
140 | b->private = NULL; | |
141 | b->shared = NULL; | |
142 | } | |
143 | ||
2df36a5d CD |
144 | /* |
145 | * Call this function to convert a u64 value to an unsigned long * bitmask | |
146 | * in a way that works on both 32-bit and 64-bit LE and BE platforms. | |
147 | * | |
148 | * Warning: Calling this function may modify *val. | |
149 | */ | |
150 | static unsigned long *u64_to_bitmask(u64 *val) | |
151 | { | |
152 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 | |
153 | *val = (*val >> 32) | (*val << 32); | |
154 | #endif | |
155 | return (unsigned long *)val; | |
156 | } | |
157 | ||
83215812 | 158 | u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) |
b47ef92a MZ |
159 | { |
160 | offset >>= 2; | |
161 | if (!offset) | |
c1bfb577 | 162 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
b47ef92a | 163 | else |
c1bfb577 | 164 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
165 | } |
166 | ||
167 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
168 | int cpuid, int irq) | |
169 | { | |
170 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
c1bfb577 | 171 | return test_bit(irq, x->private + cpuid); |
b47ef92a | 172 | |
c1bfb577 | 173 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
b47ef92a MZ |
174 | } |
175 | ||
83215812 AP |
176 | void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, |
177 | int irq, int val) | |
b47ef92a MZ |
178 | { |
179 | unsigned long *reg; | |
180 | ||
181 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
c1bfb577 | 182 | reg = x->private + cpuid; |
b47ef92a | 183 | } else { |
c1bfb577 | 184 | reg = x->shared; |
b47ef92a MZ |
185 | irq -= VGIC_NR_PRIVATE_IRQS; |
186 | } | |
187 | ||
188 | if (val) | |
189 | set_bit(irq, reg); | |
190 | else | |
191 | clear_bit(irq, reg); | |
192 | } | |
193 | ||
194 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
195 | { | |
c1bfb577 | 196 | return x->private + cpuid; |
b47ef92a MZ |
197 | } |
198 | ||
83215812 | 199 | unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) |
b47ef92a | 200 | { |
c1bfb577 MZ |
201 | return x->shared; |
202 | } | |
203 | ||
204 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) | |
205 | { | |
206 | int size; | |
207 | ||
208 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; | |
209 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
210 | ||
211 | x->private = kzalloc(size, GFP_KERNEL); | |
212 | if (!x->private) | |
213 | return -ENOMEM; | |
214 | ||
215 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | static void vgic_free_bytemap(struct vgic_bytemap *b) | |
220 | { | |
221 | kfree(b->private); | |
222 | b->private = NULL; | |
223 | b->shared = NULL; | |
b47ef92a MZ |
224 | } |
225 | ||
83215812 | 226 | u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) |
b47ef92a | 227 | { |
c1bfb577 MZ |
228 | u32 *reg; |
229 | ||
230 | if (offset < VGIC_NR_PRIVATE_IRQS) { | |
231 | reg = x->private; | |
232 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; | |
233 | } else { | |
234 | reg = x->shared; | |
235 | offset -= VGIC_NR_PRIVATE_IRQS; | |
236 | } | |
237 | ||
238 | return reg + (offset / sizeof(u32)); | |
b47ef92a MZ |
239 | } |
240 | ||
241 | #define VGIC_CFG_LEVEL 0 | |
242 | #define VGIC_CFG_EDGE 1 | |
243 | ||
244 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
245 | { | |
246 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
247 | int irq_val; | |
248 | ||
249 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
250 | return irq_val == VGIC_CFG_EDGE; | |
251 | } | |
252 | ||
253 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
254 | { | |
255 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
256 | ||
257 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
258 | } | |
259 | ||
dbf20f9d | 260 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
261 | { |
262 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
263 | ||
dbf20f9d | 264 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
265 | } |
266 | ||
47a98b15 CD |
267 | static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq) |
268 | { | |
269 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
270 | ||
271 | return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq); | |
272 | } | |
273 | ||
dbf20f9d | 274 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
275 | { |
276 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
277 | ||
dbf20f9d | 278 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
279 | } |
280 | ||
dbf20f9d | 281 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
282 | { |
283 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
284 | ||
dbf20f9d | 285 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
286 | } |
287 | ||
47a98b15 CD |
288 | static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq) |
289 | { | |
290 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
291 | ||
292 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1); | |
293 | } | |
294 | ||
295 | static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq) | |
296 | { | |
297 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
298 | ||
299 | vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0); | |
300 | } | |
301 | ||
faa1b46c CD |
302 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
303 | { | |
304 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
305 | ||
306 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
307 | } | |
308 | ||
309 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
310 | { | |
311 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
312 | ||
313 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
314 | } | |
315 | ||
316 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
317 | { | |
318 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
319 | ||
320 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
321 | } | |
322 | ||
323 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
324 | { | |
325 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
326 | ||
327 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
328 | } | |
329 | ||
330 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
331 | { | |
332 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
333 | ||
334 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
335 | } | |
336 | ||
9d949dce MZ |
337 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
338 | { | |
339 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
340 | ||
227844f5 | 341 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
342 | } |
343 | ||
83215812 | 344 | void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
345 | { |
346 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
347 | ||
227844f5 | 348 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
349 | } |
350 | ||
83215812 | 351 | void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
352 | { |
353 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
354 | ||
227844f5 | 355 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
356 | } |
357 | ||
358 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
359 | { | |
360 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
361 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
362 | else | |
363 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
364 | vcpu->arch.vgic_cpu.pending_shared); | |
365 | } | |
366 | ||
83215812 | 367 | void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
368 | { |
369 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
370 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
371 | else | |
372 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
373 | vcpu->arch.vgic_cpu.pending_shared); | |
374 | } | |
375 | ||
dbf20f9d CD |
376 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
377 | { | |
378 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
379 | } | |
380 | ||
1a89dd91 MZ |
381 | /** |
382 | * vgic_reg_access - access vgic register | |
383 | * @mmio: pointer to the data describing the mmio access | |
384 | * @reg: pointer to the virtual backing of vgic distributor data | |
385 | * @offset: least significant 2 bits used for word offset | |
386 | * @mode: ACCESS_ mode (see defines above) | |
387 | * | |
388 | * Helper to make vgic register access easier using one of the access | |
389 | * modes defined for vgic register access | |
390 | * (read,raz,write-ignored,setbit,clearbit,write) | |
391 | */ | |
83215812 AP |
392 | void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, |
393 | phys_addr_t offset, int mode) | |
1a89dd91 MZ |
394 | { |
395 | int word_offset = (offset & 3) * 8; | |
396 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
397 | u32 regval; | |
398 | ||
399 | /* | |
400 | * Any alignment fault should have been delivered to the guest | |
401 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
402 | */ | |
403 | ||
404 | if (reg) { | |
405 | regval = *reg; | |
406 | } else { | |
407 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
408 | regval = 0; | |
409 | } | |
410 | ||
411 | if (mmio->is_write) { | |
412 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
413 | switch (ACCESS_WRITE_MASK(mode)) { | |
414 | case ACCESS_WRITE_IGNORED: | |
415 | return; | |
416 | ||
417 | case ACCESS_WRITE_SETBIT: | |
418 | regval |= data; | |
419 | break; | |
420 | ||
421 | case ACCESS_WRITE_CLEARBIT: | |
422 | regval &= ~data; | |
423 | break; | |
424 | ||
425 | case ACCESS_WRITE_VALUE: | |
426 | regval = (regval & ~(mask << word_offset)) | data; | |
427 | break; | |
428 | } | |
429 | *reg = regval; | |
430 | } else { | |
431 | switch (ACCESS_READ_MASK(mode)) { | |
432 | case ACCESS_READ_RAZ: | |
433 | regval = 0; | |
434 | /* fall through */ | |
435 | ||
436 | case ACCESS_READ_VALUE: | |
437 | mmio_data_write(mmio, mask, regval >> word_offset); | |
438 | } | |
439 | } | |
440 | } | |
441 | ||
83215812 AP |
442 | bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, |
443 | phys_addr_t offset) | |
b47ef92a MZ |
444 | { |
445 | vgic_reg_access(mmio, NULL, offset, | |
446 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
447 | return false; | |
448 | } | |
449 | ||
83215812 AP |
450 | bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, |
451 | phys_addr_t offset, int vcpu_id, int access) | |
b47ef92a | 452 | { |
d97f683d AP |
453 | u32 *reg; |
454 | int mode = ACCESS_READ_VALUE | access; | |
455 | struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id); | |
456 | ||
457 | reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset); | |
458 | vgic_reg_access(mmio, reg, offset, mode); | |
b47ef92a | 459 | if (mmio->is_write) { |
d97f683d AP |
460 | if (access & ACCESS_WRITE_CLEARBIT) { |
461 | if (offset < 4) /* Force SGI enabled */ | |
462 | *reg |= 0xffff; | |
463 | vgic_retire_disabled_irqs(target_vcpu); | |
464 | } | |
465 | vgic_update_state(kvm); | |
b47ef92a MZ |
466 | return true; |
467 | } | |
468 | ||
469 | return false; | |
470 | } | |
471 | ||
83215812 AP |
472 | bool vgic_handle_set_pending_reg(struct kvm *kvm, |
473 | struct kvm_exit_mmio *mmio, | |
474 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 475 | { |
9da48b55 | 476 | u32 *reg, orig; |
faa1b46c | 477 | u32 level_mask; |
d97f683d AP |
478 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT; |
479 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 480 | |
d97f683d | 481 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset); |
faa1b46c CD |
482 | level_mask = (~(*reg)); |
483 | ||
484 | /* Mark both level and edge triggered irqs as pending */ | |
d97f683d | 485 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 486 | orig = *reg; |
d97f683d | 487 | vgic_reg_access(mmio, reg, offset, mode); |
faa1b46c | 488 | |
b47ef92a | 489 | if (mmio->is_write) { |
faa1b46c CD |
490 | /* Set the soft-pending flag only for level-triggered irqs */ |
491 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
492 | vcpu_id, offset); |
493 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c CD |
494 | *reg &= level_mask; |
495 | ||
9da48b55 CD |
496 | /* Ignore writes to SGIs */ |
497 | if (offset < 2) { | |
498 | *reg &= ~0xffff; | |
499 | *reg |= orig & 0xffff; | |
500 | } | |
501 | ||
d97f683d | 502 | vgic_update_state(kvm); |
b47ef92a MZ |
503 | return true; |
504 | } | |
505 | ||
506 | return false; | |
507 | } | |
508 | ||
83215812 AP |
509 | bool vgic_handle_clear_pending_reg(struct kvm *kvm, |
510 | struct kvm_exit_mmio *mmio, | |
511 | phys_addr_t offset, int vcpu_id) | |
b47ef92a | 512 | { |
faa1b46c | 513 | u32 *level_active; |
9da48b55 | 514 | u32 *reg, orig; |
d97f683d AP |
515 | int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT; |
516 | struct vgic_dist *dist = &kvm->arch.vgic; | |
faa1b46c | 517 | |
d97f683d | 518 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); |
9da48b55 | 519 | orig = *reg; |
d97f683d | 520 | vgic_reg_access(mmio, reg, offset, mode); |
b47ef92a | 521 | if (mmio->is_write) { |
faa1b46c CD |
522 | /* Re-set level triggered level-active interrupts */ |
523 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
d97f683d AP |
524 | vcpu_id, offset); |
525 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset); | |
faa1b46c CD |
526 | *reg |= *level_active; |
527 | ||
9da48b55 CD |
528 | /* Ignore writes to SGIs */ |
529 | if (offset < 2) { | |
530 | *reg &= ~0xffff; | |
531 | *reg |= orig & 0xffff; | |
532 | } | |
533 | ||
faa1b46c CD |
534 | /* Clear soft-pending flags */ |
535 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
d97f683d AP |
536 | vcpu_id, offset); |
537 | vgic_reg_access(mmio, reg, offset, mode); | |
faa1b46c | 538 | |
d97f683d | 539 | vgic_update_state(kvm); |
b47ef92a MZ |
540 | return true; |
541 | } | |
b47ef92a MZ |
542 | return false; |
543 | } | |
544 | ||
47a98b15 CD |
545 | bool vgic_handle_set_active_reg(struct kvm *kvm, |
546 | struct kvm_exit_mmio *mmio, | |
547 | phys_addr_t offset, int vcpu_id) | |
548 | { | |
549 | u32 *reg; | |
550 | struct vgic_dist *dist = &kvm->arch.vgic; | |
551 | ||
552 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); | |
553 | vgic_reg_access(mmio, reg, offset, | |
554 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
555 | ||
556 | if (mmio->is_write) { | |
557 | vgic_update_state(kvm); | |
558 | return true; | |
559 | } | |
560 | ||
561 | return false; | |
562 | } | |
563 | ||
564 | bool vgic_handle_clear_active_reg(struct kvm *kvm, | |
565 | struct kvm_exit_mmio *mmio, | |
566 | phys_addr_t offset, int vcpu_id) | |
567 | { | |
568 | u32 *reg; | |
569 | struct vgic_dist *dist = &kvm->arch.vgic; | |
570 | ||
571 | reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); | |
572 | vgic_reg_access(mmio, reg, offset, | |
573 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
574 | ||
575 | if (mmio->is_write) { | |
576 | vgic_update_state(kvm); | |
577 | return true; | |
578 | } | |
579 | ||
580 | return false; | |
581 | } | |
582 | ||
b47ef92a MZ |
583 | static u32 vgic_cfg_expand(u16 val) |
584 | { | |
585 | u32 res = 0; | |
586 | int i; | |
587 | ||
588 | /* | |
589 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
590 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
591 | */ | |
592 | for (i = 0; i < 16; i++) | |
593 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
594 | ||
595 | return res; | |
596 | } | |
597 | ||
598 | static u16 vgic_cfg_compress(u32 val) | |
599 | { | |
600 | u16 res = 0; | |
601 | int i; | |
602 | ||
603 | /* | |
604 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
605 | * abcd...mnop which is what we really care about. | |
606 | */ | |
607 | for (i = 0; i < 16; i++) | |
608 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
609 | ||
610 | return res; | |
611 | } | |
612 | ||
613 | /* | |
614 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
615 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
616 | * two above functions to compress/expand the bits | |
617 | */ | |
83215812 AP |
618 | bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, |
619 | phys_addr_t offset) | |
b47ef92a MZ |
620 | { |
621 | u32 val; | |
6545eae3 | 622 | |
f2ae85b2 | 623 | if (offset & 4) |
b47ef92a MZ |
624 | val = *reg >> 16; |
625 | else | |
626 | val = *reg & 0xffff; | |
627 | ||
628 | val = vgic_cfg_expand(val); | |
629 | vgic_reg_access(mmio, &val, offset, | |
630 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
631 | if (mmio->is_write) { | |
f2ae85b2 | 632 | if (offset < 8) { |
b47ef92a MZ |
633 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
634 | return false; | |
635 | } | |
636 | ||
637 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 638 | if (offset & 4) { |
b47ef92a MZ |
639 | *reg &= 0xffff; |
640 | *reg |= val << 16; | |
641 | } else { | |
642 | *reg &= 0xffff << 16; | |
643 | *reg |= val; | |
644 | } | |
645 | } | |
646 | ||
647 | return false; | |
648 | } | |
649 | ||
cbd333a4 | 650 | /** |
47a98b15 | 651 | * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor |
cbd333a4 CD |
652 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs |
653 | * | |
47a98b15 | 654 | * Move any IRQs that have already been assigned to LRs back to the |
cbd333a4 CD |
655 | * emulated distributor state so that the complete emulated state can be read |
656 | * from the main emulation structures without investigating the LRs. | |
cbd333a4 | 657 | */ |
83215812 | 658 | void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) |
cbd333a4 | 659 | { |
cbd333a4 | 660 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; |
8d5c6b06 | 661 | int i; |
cbd333a4 CD |
662 | |
663 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 664 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
665 | |
666 | /* | |
667 | * There are three options for the state bits: | |
668 | * | |
669 | * 01: pending | |
670 | * 10: active | |
671 | * 11: pending and active | |
cbd333a4 | 672 | */ |
47a98b15 CD |
673 | BUG_ON(!(lr.state & LR_STATE_MASK)); |
674 | ||
675 | /* Reestablish SGI source for pending and active IRQs */ | |
676 | if (lr.irq < VGIC_NR_SGIS) | |
677 | add_sgi_source(vcpu, lr.irq, lr.source); | |
678 | ||
679 | /* | |
680 | * If the LR holds an active (10) or a pending and active (11) | |
681 | * interrupt then move the active state to the | |
682 | * distributor tracking bit. | |
683 | */ | |
684 | if (lr.state & LR_STATE_ACTIVE) { | |
685 | vgic_irq_set_active(vcpu, lr.irq); | |
686 | lr.state &= ~LR_STATE_ACTIVE; | |
687 | } | |
cbd333a4 CD |
688 | |
689 | /* | |
690 | * Reestablish the pending state on the distributor and the | |
691 | * CPU interface. It may have already been pending, but that | |
692 | * is fine, then we are only setting a few bits that were | |
693 | * already set. | |
694 | */ | |
47a98b15 CD |
695 | if (lr.state & LR_STATE_PENDING) { |
696 | vgic_dist_irq_set_pending(vcpu, lr.irq); | |
697 | lr.state &= ~LR_STATE_PENDING; | |
698 | } | |
699 | ||
8d5c6b06 | 700 | vgic_set_lr(vcpu, i, lr); |
cbd333a4 CD |
701 | |
702 | /* | |
47a98b15 | 703 | * Mark the LR as free for other use. |
cbd333a4 | 704 | */ |
47a98b15 CD |
705 | BUG_ON(lr.state & LR_STATE_MASK); |
706 | vgic_retire_lr(i, lr.irq, vcpu); | |
707 | vgic_irq_clear_queued(vcpu, lr.irq); | |
cbd333a4 CD |
708 | |
709 | /* Finally update the VGIC state. */ | |
710 | vgic_update_state(vcpu->kvm); | |
711 | } | |
712 | } | |
713 | ||
83215812 | 714 | const |
cf50a1eb | 715 | struct vgic_io_range *vgic_find_range(const struct vgic_io_range *ranges, |
9f199d0a | 716 | int len, gpa_t offset) |
1a89dd91 | 717 | { |
9f199d0a AP |
718 | while (ranges->len) { |
719 | if (offset >= ranges->base && | |
720 | (offset + len) <= (ranges->base + ranges->len)) | |
721 | return ranges; | |
722 | ranges++; | |
1a89dd91 MZ |
723 | } |
724 | ||
725 | return NULL; | |
726 | } | |
727 | ||
c3c91836 | 728 | static bool vgic_validate_access(const struct vgic_dist *dist, |
cf50a1eb | 729 | const struct vgic_io_range *range, |
c3c91836 MZ |
730 | unsigned long offset) |
731 | { | |
732 | int irq; | |
733 | ||
734 | if (!range->bits_per_irq) | |
735 | return true; /* Not an irq-based access */ | |
736 | ||
737 | irq = offset * 8 / range->bits_per_irq; | |
738 | if (irq >= dist->nr_irqs) | |
739 | return false; | |
740 | ||
741 | return true; | |
742 | } | |
743 | ||
05bc8aaf AP |
744 | /* |
745 | * Call the respective handler function for the given range. | |
746 | * We split up any 64 bit accesses into two consecutive 32 bit | |
747 | * handler calls and merge the result afterwards. | |
748 | * We do this in a little endian fashion regardless of the host's | |
749 | * or guest's endianness, because the GIC is always LE and the rest of | |
750 | * the code (vgic_reg_access) also puts it in a LE fashion already. | |
751 | * At this point we have already identified the handle function, so | |
752 | * range points to that one entry and offset is relative to this. | |
753 | */ | |
754 | static bool call_range_handler(struct kvm_vcpu *vcpu, | |
755 | struct kvm_exit_mmio *mmio, | |
756 | unsigned long offset, | |
cf50a1eb | 757 | const struct vgic_io_range *range) |
05bc8aaf AP |
758 | { |
759 | u32 *data32 = (void *)mmio->data; | |
760 | struct kvm_exit_mmio mmio32; | |
761 | bool ret; | |
762 | ||
763 | if (likely(mmio->len <= 4)) | |
764 | return range->handle_mmio(vcpu, mmio, offset); | |
765 | ||
766 | /* | |
767 | * Any access bigger than 4 bytes (that we currently handle in KVM) | |
768 | * is actually 8 bytes long, caused by a 64-bit access | |
769 | */ | |
770 | ||
771 | mmio32.len = 4; | |
772 | mmio32.is_write = mmio->is_write; | |
9fedf146 | 773 | mmio32.private = mmio->private; |
05bc8aaf AP |
774 | |
775 | mmio32.phys_addr = mmio->phys_addr + 4; | |
776 | if (mmio->is_write) | |
777 | *(u32 *)mmio32.data = data32[1]; | |
778 | ret = range->handle_mmio(vcpu, &mmio32, offset + 4); | |
779 | if (!mmio->is_write) | |
780 | data32[1] = *(u32 *)mmio32.data; | |
781 | ||
782 | mmio32.phys_addr = mmio->phys_addr; | |
783 | if (mmio->is_write) | |
784 | *(u32 *)mmio32.data = data32[0]; | |
785 | ret |= range->handle_mmio(vcpu, &mmio32, offset); | |
786 | if (!mmio->is_write) | |
787 | data32[0] = *(u32 *)mmio32.data; | |
788 | ||
789 | return ret; | |
790 | } | |
791 | ||
1a89dd91 | 792 | /** |
96415257 | 793 | * vgic_handle_mmio_range - handle an in-kernel MMIO access |
1a89dd91 MZ |
794 | * @vcpu: pointer to the vcpu performing the access |
795 | * @run: pointer to the kvm_run structure | |
796 | * @mmio: pointer to the data describing the access | |
96415257 AP |
797 | * @ranges: array of MMIO ranges in a given region |
798 | * @mmio_base: base address of that region | |
1a89dd91 | 799 | * |
96415257 | 800 | * returns true if the MMIO access could be performed |
1a89dd91 | 801 | */ |
83215812 | 802 | bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, |
96415257 | 803 | struct kvm_exit_mmio *mmio, |
cf50a1eb | 804 | const struct vgic_io_range *ranges, |
96415257 | 805 | unsigned long mmio_base) |
1a89dd91 | 806 | { |
cf50a1eb | 807 | const struct vgic_io_range *range; |
b47ef92a | 808 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
b47ef92a MZ |
809 | bool updated_state; |
810 | unsigned long offset; | |
811 | ||
96415257 | 812 | offset = mmio->phys_addr - mmio_base; |
9f199d0a | 813 | range = vgic_find_range(ranges, mmio->len, offset); |
b47ef92a MZ |
814 | if (unlikely(!range || !range->handle_mmio)) { |
815 | pr_warn("Unhandled access %d %08llx %d\n", | |
816 | mmio->is_write, mmio->phys_addr, mmio->len); | |
817 | return false; | |
818 | } | |
819 | ||
820 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
96415257 | 821 | offset -= range->base; |
c3c91836 | 822 | if (vgic_validate_access(dist, range, offset)) { |
05bc8aaf | 823 | updated_state = call_range_handler(vcpu, mmio, offset, range); |
c3c91836 | 824 | } else { |
05bc8aaf AP |
825 | if (!mmio->is_write) |
826 | memset(mmio->data, 0, mmio->len); | |
c3c91836 MZ |
827 | updated_state = false; |
828 | } | |
b47ef92a MZ |
829 | spin_unlock(&vcpu->kvm->arch.vgic.lock); |
830 | kvm_prepare_mmio(run, mmio); | |
831 | kvm_handle_mmio_return(vcpu, run); | |
832 | ||
5863c2ce MZ |
833 | if (updated_state) |
834 | vgic_kick_vcpus(vcpu->kvm); | |
835 | ||
b47ef92a MZ |
836 | return true; |
837 | } | |
838 | ||
96415257 AP |
839 | /** |
840 | * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation | |
841 | * @vcpu: pointer to the vcpu performing the access | |
842 | * @run: pointer to the kvm_run structure | |
843 | * @mmio: pointer to the data describing the access | |
844 | * | |
845 | * returns true if the MMIO access has been performed in kernel space, | |
846 | * and false if it needs to be emulated in user space. | |
b26e5fda | 847 | * Calls the actual handling routine for the selected VGIC model. |
96415257 AP |
848 | */ |
849 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
850 | struct kvm_exit_mmio *mmio) | |
851 | { | |
852 | if (!irqchip_in_kernel(vcpu->kvm)) | |
853 | return false; | |
854 | ||
b26e5fda AP |
855 | /* |
856 | * This will currently call either vgic_v2_handle_mmio() or | |
857 | * vgic_v3_handle_mmio(), which in turn will call | |
858 | * vgic_handle_mmio_range() defined above. | |
859 | */ | |
860 | return vcpu->kvm->arch.vgic.vm_ops.handle_mmio(vcpu, run, mmio); | |
96415257 AP |
861 | } |
862 | ||
fb65ab63 MZ |
863 | static int vgic_nr_shared_irqs(struct vgic_dist *dist) |
864 | { | |
865 | return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
866 | } | |
867 | ||
47a98b15 CD |
868 | static int compute_active_for_cpu(struct kvm_vcpu *vcpu) |
869 | { | |
870 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
871 | unsigned long *active, *enabled, *act_percpu, *act_shared; | |
872 | unsigned long active_private, active_shared; | |
873 | int nr_shared = vgic_nr_shared_irqs(dist); | |
874 | int vcpu_id; | |
875 | ||
876 | vcpu_id = vcpu->vcpu_id; | |
877 | act_percpu = vcpu->arch.vgic_cpu.active_percpu; | |
878 | act_shared = vcpu->arch.vgic_cpu.active_shared; | |
879 | ||
880 | active = vgic_bitmap_get_cpu_map(&dist->irq_active, vcpu_id); | |
881 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); | |
882 | bitmap_and(act_percpu, active, enabled, VGIC_NR_PRIVATE_IRQS); | |
883 | ||
884 | active = vgic_bitmap_get_shared_map(&dist->irq_active); | |
885 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); | |
886 | bitmap_and(act_shared, active, enabled, nr_shared); | |
887 | bitmap_and(act_shared, act_shared, | |
888 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
889 | nr_shared); | |
890 | ||
891 | active_private = find_first_bit(act_percpu, VGIC_NR_PRIVATE_IRQS); | |
892 | active_shared = find_first_bit(act_shared, nr_shared); | |
893 | ||
894 | return (active_private < VGIC_NR_PRIVATE_IRQS || | |
895 | active_shared < nr_shared); | |
896 | } | |
897 | ||
b47ef92a MZ |
898 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) |
899 | { | |
9d949dce MZ |
900 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
901 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
902 | unsigned long pending_private, pending_shared; | |
fb65ab63 | 903 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
904 | int vcpu_id; |
905 | ||
906 | vcpu_id = vcpu->vcpu_id; | |
907 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
908 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
909 | ||
227844f5 | 910 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
911 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
912 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
913 | ||
227844f5 | 914 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce | 915 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
fb65ab63 | 916 | bitmap_and(pend_shared, pending, enabled, nr_shared); |
9d949dce MZ |
917 | bitmap_and(pend_shared, pend_shared, |
918 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
fb65ab63 | 919 | nr_shared); |
9d949dce MZ |
920 | |
921 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
fb65ab63 | 922 | pending_shared = find_first_bit(pend_shared, nr_shared); |
9d949dce | 923 | return (pending_private < VGIC_NR_PRIVATE_IRQS || |
fb65ab63 | 924 | pending_shared < vgic_nr_shared_irqs(dist)); |
b47ef92a MZ |
925 | } |
926 | ||
927 | /* | |
928 | * Update the interrupt state and determine which CPUs have pending | |
47a98b15 | 929 | * or active interrupts. Must be called with distributor lock held. |
b47ef92a | 930 | */ |
83215812 | 931 | void vgic_update_state(struct kvm *kvm) |
b47ef92a MZ |
932 | { |
933 | struct vgic_dist *dist = &kvm->arch.vgic; | |
934 | struct kvm_vcpu *vcpu; | |
935 | int c; | |
936 | ||
937 | if (!dist->enabled) { | |
c1bfb577 | 938 | set_bit(0, dist->irq_pending_on_cpu); |
b47ef92a MZ |
939 | return; |
940 | } | |
941 | ||
942 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
47a98b15 | 943 | if (compute_pending_for_cpu(vcpu)) |
c1bfb577 | 944 | set_bit(c, dist->irq_pending_on_cpu); |
47a98b15 CD |
945 | |
946 | if (compute_active_for_cpu(vcpu)) | |
947 | set_bit(c, dist->irq_active_on_cpu); | |
948 | else | |
949 | clear_bit(c, dist->irq_active_on_cpu); | |
b47ef92a | 950 | } |
1a89dd91 | 951 | } |
330690cd | 952 | |
8d5c6b06 MZ |
953 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
954 | { | |
8f186d52 | 955 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
956 | } |
957 | ||
958 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
959 | struct vgic_lr vlr) | |
960 | { | |
8f186d52 | 961 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
962 | } |
963 | ||
69bb2c9f MZ |
964 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
965 | struct vgic_lr vlr) | |
966 | { | |
8f186d52 | 967 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
968 | } |
969 | ||
970 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
971 | { | |
8f186d52 | 972 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
973 | } |
974 | ||
8d6a0313 MZ |
975 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
976 | { | |
8f186d52 | 977 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
978 | } |
979 | ||
495dd859 MZ |
980 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
981 | { | |
8f186d52 | 982 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
983 | } |
984 | ||
909d9b50 MZ |
985 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
986 | { | |
8f186d52 | 987 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
988 | } |
989 | ||
990 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
991 | { | |
8f186d52 | 992 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
993 | } |
994 | ||
83215812 | 995 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 996 | { |
8f186d52 | 997 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
998 | } |
999 | ||
83215812 | 1000 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
beee38b9 | 1001 | { |
8f186d52 | 1002 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1003 | } |
1004 | ||
da8dafd1 MZ |
1005 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1006 | { | |
8f186d52 | 1007 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1008 | } |
1009 | ||
8d5c6b06 MZ |
1010 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1011 | { | |
1012 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1013 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1014 | ||
1015 | vlr.state = 0; | |
1016 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1017 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1018 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1019 | } | |
a1fcb44e MZ |
1020 | |
1021 | /* | |
1022 | * An interrupt may have been disabled after being made pending on the | |
1023 | * CPU interface (the classic case is a timer running while we're | |
1024 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1025 | * interface gets enabled, with deadly consequences). | |
1026 | * | |
1027 | * The solution is to examine already active LRs, and check the | |
1028 | * interrupt is still enabled. If not, just retire it. | |
1029 | */ | |
1030 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1031 | { | |
1032 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1033 | int lr; | |
1034 | ||
8f186d52 | 1035 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1036 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1037 | |
8d5c6b06 MZ |
1038 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1039 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1040 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1041 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1042 | } |
1043 | } | |
1044 | } | |
1045 | ||
71760950 AB |
1046 | static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, |
1047 | int lr_nr, struct vgic_lr vlr) | |
1048 | { | |
47a98b15 CD |
1049 | if (vgic_irq_is_active(vcpu, irq)) { |
1050 | vlr.state |= LR_STATE_ACTIVE; | |
1051 | kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state); | |
1052 | vgic_irq_clear_active(vcpu, irq); | |
1053 | vgic_update_state(vcpu->kvm); | |
1054 | } else if (vgic_dist_irq_is_pending(vcpu, irq)) { | |
71760950 AB |
1055 | vlr.state |= LR_STATE_PENDING; |
1056 | kvm_debug("Set pending: 0x%x\n", vlr.state); | |
1057 | } | |
1058 | ||
1059 | if (!vgic_irq_is_edge(vcpu, irq)) | |
1060 | vlr.state |= LR_EOI_INT; | |
1061 | ||
1062 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1063 | } | |
1064 | ||
9d949dce MZ |
1065 | /* |
1066 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1067 | * or false if it wasn't possible to queue it. | |
1d916229 | 1068 | * sgi_source must be zero for any non-SGI interrupts. |
9d949dce | 1069 | */ |
83215812 | 1070 | bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) |
9d949dce MZ |
1071 | { |
1072 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
5fb66da6 | 1073 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
8d5c6b06 | 1074 | struct vgic_lr vlr; |
9d949dce MZ |
1075 | int lr; |
1076 | ||
1077 | /* Sanitize the input... */ | |
1078 | BUG_ON(sgi_source_id & ~7); | |
1079 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
5fb66da6 | 1080 | BUG_ON(irq >= dist->nr_irqs); |
9d949dce MZ |
1081 | |
1082 | kvm_debug("Queue IRQ%d\n", irq); | |
1083 | ||
1084 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1085 | ||
1086 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1087 | if (lr != LR_EMPTY) { |
1088 | vlr = vgic_get_lr(vcpu, lr); | |
1089 | if (vlr.source == sgi_source_id) { | |
1090 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1091 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
71760950 | 1092 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); |
8d5c6b06 MZ |
1093 | return true; |
1094 | } | |
9d949dce MZ |
1095 | } |
1096 | ||
1097 | /* Try to use another LR for this interrupt */ | |
1098 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1099 | vgic->nr_lr); |
1100 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1101 | return false; |
1102 | ||
1103 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1104 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1105 | set_bit(lr, vgic_cpu->lr_used); | |
1106 | ||
8d5c6b06 MZ |
1107 | vlr.irq = irq; |
1108 | vlr.source = sgi_source_id; | |
71760950 AB |
1109 | vlr.state = 0; |
1110 | vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); | |
9d949dce MZ |
1111 | |
1112 | return true; | |
1113 | } | |
1114 | ||
9d949dce MZ |
1115 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) |
1116 | { | |
dbf20f9d | 1117 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1118 | return true; /* level interrupt, already queued */ |
1119 | ||
1120 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1121 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1122 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1123 | vgic_cpu_irq_clear(vcpu, irq); |
1124 | } else { | |
dbf20f9d | 1125 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1126 | } |
1127 | ||
1128 | return true; | |
1129 | } | |
1130 | ||
1131 | return false; | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Fill the list registers with pending interrupts before running the | |
1136 | * guest. | |
1137 | */ | |
1138 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1139 | { | |
1140 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1141 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
47a98b15 | 1142 | unsigned long *pa_percpu, *pa_shared; |
9d949dce MZ |
1143 | int i, vcpu_id; |
1144 | int overflow = 0; | |
47a98b15 | 1145 | int nr_shared = vgic_nr_shared_irqs(dist); |
9d949dce MZ |
1146 | |
1147 | vcpu_id = vcpu->vcpu_id; | |
1148 | ||
47a98b15 CD |
1149 | pa_percpu = vcpu->arch.vgic_cpu.pend_act_percpu; |
1150 | pa_shared = vcpu->arch.vgic_cpu.pend_act_shared; | |
1151 | ||
1152 | bitmap_or(pa_percpu, vgic_cpu->pending_percpu, vgic_cpu->active_percpu, | |
1153 | VGIC_NR_PRIVATE_IRQS); | |
1154 | bitmap_or(pa_shared, vgic_cpu->pending_shared, vgic_cpu->active_shared, | |
1155 | nr_shared); | |
9d949dce MZ |
1156 | /* |
1157 | * We may not have any pending interrupt, or the interrupts | |
1158 | * may have been serviced from another vcpu. In all cases, | |
1159 | * move along. | |
1160 | */ | |
47a98b15 | 1161 | if (!kvm_vgic_vcpu_pending_irq(vcpu) && !kvm_vgic_vcpu_active_irq(vcpu)) |
9d949dce | 1162 | goto epilog; |
9d949dce MZ |
1163 | |
1164 | /* SGIs */ | |
47a98b15 | 1165 | for_each_set_bit(i, pa_percpu, VGIC_NR_SGIS) { |
b26e5fda | 1166 | if (!queue_sgi(vcpu, i)) |
9d949dce MZ |
1167 | overflow = 1; |
1168 | } | |
1169 | ||
1170 | /* PPIs */ | |
47a98b15 | 1171 | for_each_set_bit_from(i, pa_percpu, VGIC_NR_PRIVATE_IRQS) { |
9d949dce MZ |
1172 | if (!vgic_queue_hwirq(vcpu, i)) |
1173 | overflow = 1; | |
1174 | } | |
1175 | ||
1176 | /* SPIs */ | |
47a98b15 | 1177 | for_each_set_bit(i, pa_shared, nr_shared) { |
9d949dce MZ |
1178 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) |
1179 | overflow = 1; | |
1180 | } | |
1181 | ||
47a98b15 CD |
1182 | |
1183 | ||
1184 | ||
9d949dce MZ |
1185 | epilog: |
1186 | if (overflow) { | |
909d9b50 | 1187 | vgic_enable_underflow(vcpu); |
9d949dce | 1188 | } else { |
909d9b50 | 1189 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1190 | /* |
1191 | * We're about to run this VCPU, and we've consumed | |
1192 | * everything the distributor had in store for | |
1193 | * us. Claim we don't have anything pending. We'll | |
1194 | * adjust that if needed while exiting. | |
1195 | */ | |
c1bfb577 | 1196 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1197 | } |
1198 | } | |
1199 | ||
1200 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1201 | { | |
495dd859 | 1202 | u32 status = vgic_get_interrupt_status(vcpu); |
649cf739 | 1203 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
9d949dce | 1204 | bool level_pending = false; |
174178fe | 1205 | struct kvm *kvm = vcpu->kvm; |
9d949dce | 1206 | |
495dd859 | 1207 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1208 | |
495dd859 | 1209 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1210 | /* |
1211 | * Some level interrupts have been EOIed. Clear their | |
1212 | * active bit. | |
1213 | */ | |
8d6a0313 | 1214 | u64 eisr = vgic_get_eisr(vcpu); |
2df36a5d | 1215 | unsigned long *eisr_ptr = u64_to_bitmask(&eisr); |
8d5c6b06 | 1216 | int lr; |
9d949dce | 1217 | |
8f186d52 | 1218 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1219 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1220 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1221 | |
649cf739 | 1222 | spin_lock(&dist->lock); |
dbf20f9d | 1223 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1224 | WARN_ON(vlr.state & LR_STATE_MASK); |
1225 | vlr.state = 0; | |
1226 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1227 | |
faa1b46c CD |
1228 | /* |
1229 | * If the IRQ was EOIed it was also ACKed and we we | |
1230 | * therefore assume we can clear the soft pending | |
1231 | * state (should it had been set) for this interrupt. | |
1232 | * | |
1233 | * Note: if the IRQ soft pending state was set after | |
1234 | * the IRQ was acked, it actually shouldn't be | |
1235 | * cleared, but we have no way of knowing that unless | |
1236 | * we start trapping ACKs when the soft-pending state | |
1237 | * is set. | |
1238 | */ | |
1239 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1240 | ||
174178fe EA |
1241 | /* |
1242 | * kvm_notify_acked_irq calls kvm_set_irq() | |
1243 | * to reset the IRQ level. Need to release the | |
1244 | * lock for kvm_set_irq to grab it. | |
1245 | */ | |
1246 | spin_unlock(&dist->lock); | |
1247 | ||
1248 | kvm_notify_acked_irq(kvm, 0, | |
1249 | vlr.irq - VGIC_NR_PRIVATE_IRQS); | |
1250 | spin_lock(&dist->lock); | |
1251 | ||
9d949dce | 1252 | /* Any additional pending interrupt? */ |
faa1b46c | 1253 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1254 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1255 | level_pending = true; |
1256 | } else { | |
faa1b46c | 1257 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1258 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1259 | } |
75da01e1 | 1260 | |
649cf739 EA |
1261 | spin_unlock(&dist->lock); |
1262 | ||
75da01e1 MZ |
1263 | /* |
1264 | * Despite being EOIed, the LR may not have | |
1265 | * been marked as empty. | |
1266 | */ | |
69bb2c9f | 1267 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1268 | } |
1269 | } | |
1270 | ||
495dd859 | 1271 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1272 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1273 | |
1274 | return level_pending; | |
1275 | } | |
1276 | ||
649cf739 | 1277 | /* Sync back the VGIC state after a guest run */ |
9d949dce MZ |
1278 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) |
1279 | { | |
1280 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1281 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1282 | u64 elrsr; |
1283 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1284 | int lr, pending; |
1285 | bool level_pending; | |
1286 | ||
1287 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f | 1288 | elrsr = vgic_get_elrsr(vcpu); |
2df36a5d | 1289 | elrsr_ptr = u64_to_bitmask(&elrsr); |
9d949dce MZ |
1290 | |
1291 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1292 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1293 | struct vgic_lr vlr; |
9d949dce MZ |
1294 | |
1295 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1296 | continue; | |
1297 | ||
8d5c6b06 | 1298 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1299 | |
5fb66da6 | 1300 | BUG_ON(vlr.irq >= dist->nr_irqs); |
8d5c6b06 | 1301 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; |
9d949dce MZ |
1302 | } |
1303 | ||
1304 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1305 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1306 | if (level_pending || pending < vgic->nr_lr) | |
c1bfb577 | 1307 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1308 | } |
1309 | ||
1310 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1311 | { | |
1312 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1313 | ||
1314 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1315 | return; | |
1316 | ||
1317 | spin_lock(&dist->lock); | |
1318 | __kvm_vgic_flush_hwstate(vcpu); | |
1319 | spin_unlock(&dist->lock); | |
1320 | } | |
1321 | ||
1322 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1323 | { | |
1324 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1325 | return; | |
1326 | ||
1327 | __kvm_vgic_sync_hwstate(vcpu); | |
1328 | } | |
1329 | ||
1330 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1331 | { | |
1332 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1333 | ||
1334 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1335 | return 0; | |
1336 | ||
c1bfb577 | 1337 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1338 | } |
1339 | ||
47a98b15 CD |
1340 | int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu) |
1341 | { | |
1342 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1343 | ||
1344 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1345 | return 0; | |
1346 | ||
1347 | return test_bit(vcpu->vcpu_id, dist->irq_active_on_cpu); | |
1348 | } | |
1349 | ||
1350 | ||
83215812 | 1351 | void vgic_kick_vcpus(struct kvm *kvm) |
5863c2ce MZ |
1352 | { |
1353 | struct kvm_vcpu *vcpu; | |
1354 | int c; | |
1355 | ||
1356 | /* | |
1357 | * We've injected an interrupt, time to find out who deserves | |
1358 | * a good kick... | |
1359 | */ | |
1360 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1361 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1362 | kvm_vcpu_kick(vcpu); | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1367 | { | |
227844f5 | 1368 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1369 | |
1370 | /* | |
1371 | * Only inject an interrupt if: | |
1372 | * - edge triggered and we have a rising edge | |
1373 | * - level triggered and we change level | |
1374 | */ | |
faa1b46c CD |
1375 | if (edge_triggered) { |
1376 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1377 | return level > state; |
faa1b46c CD |
1378 | } else { |
1379 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1380 | return level != state; |
faa1b46c | 1381 | } |
5863c2ce MZ |
1382 | } |
1383 | ||
016ed39c | 1384 | static int vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1385 | unsigned int irq_num, bool level) |
1386 | { | |
1387 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1388 | struct kvm_vcpu *vcpu; | |
227844f5 | 1389 | int edge_triggered, level_triggered; |
5863c2ce | 1390 | int enabled; |
a0675c25 | 1391 | bool ret = true, can_inject = true; |
5863c2ce MZ |
1392 | |
1393 | spin_lock(&dist->lock); | |
1394 | ||
1395 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1396 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1397 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1398 | |
1399 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1400 | ret = false; | |
1401 | goto out; | |
1402 | } | |
1403 | ||
1404 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1405 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
a0675c25 AP |
1406 | if (cpuid == VCPU_NOT_ALLOCATED) { |
1407 | /* Pretend we use CPU0, and prevent injection */ | |
1408 | cpuid = 0; | |
1409 | can_inject = false; | |
1410 | } | |
5863c2ce MZ |
1411 | vcpu = kvm_get_vcpu(kvm, cpuid); |
1412 | } | |
1413 | ||
1414 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1415 | ||
faa1b46c CD |
1416 | if (level) { |
1417 | if (level_triggered) | |
1418 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1419 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1420 | } else { |
1421 | if (level_triggered) { | |
1422 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1423 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1424 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
faa1b46c | 1425 | } |
7d39f9e3 | 1426 | |
1427 | ret = false; | |
1428 | goto out; | |
faa1b46c | 1429 | } |
5863c2ce MZ |
1430 | |
1431 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1432 | ||
a0675c25 | 1433 | if (!enabled || !can_inject) { |
5863c2ce MZ |
1434 | ret = false; |
1435 | goto out; | |
1436 | } | |
1437 | ||
dbf20f9d | 1438 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1439 | /* |
1440 | * Level interrupt in progress, will be picked up | |
1441 | * when EOId. | |
1442 | */ | |
1443 | ret = false; | |
1444 | goto out; | |
1445 | } | |
1446 | ||
1447 | if (level) { | |
1448 | vgic_cpu_irq_set(vcpu, irq_num); | |
c1bfb577 | 1449 | set_bit(cpuid, dist->irq_pending_on_cpu); |
5863c2ce MZ |
1450 | } |
1451 | ||
1452 | out: | |
1453 | spin_unlock(&dist->lock); | |
1454 | ||
016ed39c | 1455 | return ret ? cpuid : -EINVAL; |
5863c2ce MZ |
1456 | } |
1457 | ||
1458 | /** | |
1459 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1460 | * @kvm: The VM structure pointer | |
1461 | * @cpuid: The CPU for PPIs | |
1462 | * @irq_num: The IRQ number that is assigned to the device | |
1463 | * @level: Edge-triggered: true: to trigger the interrupt | |
1464 | * false: to ignore the call | |
1465 | * Level-sensitive true: activates an interrupt | |
1466 | * false: deactivates an interrupt | |
1467 | * | |
1468 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1469 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1470 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1471 | */ | |
1472 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1473 | bool level) | |
1474 | { | |
ca7d9c82 | 1475 | int ret = 0; |
016ed39c | 1476 | int vcpu_id; |
5863c2ce | 1477 | |
ca7d9c82 | 1478 | if (unlikely(!vgic_initialized(kvm))) { |
59892136 AP |
1479 | /* |
1480 | * We only provide the automatic initialization of the VGIC | |
1481 | * for the legacy case of a GICv2. Any other type must | |
1482 | * be explicitly initialized once setup with the respective | |
1483 | * KVM device call. | |
1484 | */ | |
1485 | if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) { | |
1486 | ret = -EBUSY; | |
1487 | goto out; | |
1488 | } | |
ca7d9c82 CD |
1489 | mutex_lock(&kvm->lock); |
1490 | ret = vgic_init(kvm); | |
1491 | mutex_unlock(&kvm->lock); | |
1492 | ||
1493 | if (ret) | |
1494 | goto out; | |
016ed39c | 1495 | } |
5863c2ce | 1496 | |
ca7d9c82 CD |
1497 | vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level); |
1498 | if (vcpu_id >= 0) { | |
1499 | /* kick the specified vcpu */ | |
1500 | kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id)); | |
1501 | } | |
1502 | ||
1503 | out: | |
1504 | return ret; | |
5863c2ce MZ |
1505 | } |
1506 | ||
01ac5e34 MZ |
1507 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1508 | { | |
1509 | /* | |
1510 | * We cannot rely on the vgic maintenance interrupt to be | |
1511 | * delivered synchronously. This means we can only use it to | |
1512 | * exit the VM, and we perform the handling of EOIed | |
1513 | * interrupts on the exit path (see vgic_process_maintenance). | |
1514 | */ | |
1515 | return IRQ_HANDLED; | |
1516 | } | |
1517 | ||
c1bfb577 MZ |
1518 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
1519 | { | |
1520 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1521 | ||
1522 | kfree(vgic_cpu->pending_shared); | |
47a98b15 CD |
1523 | kfree(vgic_cpu->active_shared); |
1524 | kfree(vgic_cpu->pend_act_shared); | |
c1bfb577 MZ |
1525 | kfree(vgic_cpu->vgic_irq_lr_map); |
1526 | vgic_cpu->pending_shared = NULL; | |
47a98b15 CD |
1527 | vgic_cpu->active_shared = NULL; |
1528 | vgic_cpu->pend_act_shared = NULL; | |
c1bfb577 MZ |
1529 | vgic_cpu->vgic_irq_lr_map = NULL; |
1530 | } | |
1531 | ||
1532 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) | |
1533 | { | |
1534 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1535 | ||
1536 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; | |
1537 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); | |
47a98b15 CD |
1538 | vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL); |
1539 | vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL); | |
6d3cfbe2 | 1540 | vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL); |
c1bfb577 | 1541 | |
47a98b15 CD |
1542 | if (!vgic_cpu->pending_shared |
1543 | || !vgic_cpu->active_shared | |
1544 | || !vgic_cpu->pend_act_shared | |
1545 | || !vgic_cpu->vgic_irq_lr_map) { | |
c1bfb577 MZ |
1546 | kvm_vgic_vcpu_destroy(vcpu); |
1547 | return -ENOMEM; | |
1548 | } | |
1549 | ||
6d3cfbe2 | 1550 | memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); |
01ac5e34 MZ |
1551 | |
1552 | /* | |
ca85f623 MZ |
1553 | * Store the number of LRs per vcpu, so we don't have to go |
1554 | * all the way to the distributor structure to find out. Only | |
1555 | * assembly code should use this one. | |
01ac5e34 | 1556 | */ |
8f186d52 | 1557 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1558 | |
6d3cfbe2 | 1559 | return 0; |
01ac5e34 MZ |
1560 | } |
1561 | ||
3caa2d8c AP |
1562 | /** |
1563 | * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW | |
1564 | * | |
1565 | * The host's GIC naturally limits the maximum amount of VCPUs a guest | |
1566 | * can use. | |
1567 | */ | |
1568 | int kvm_vgic_get_max_vcpus(void) | |
1569 | { | |
1570 | return vgic->max_gic_vcpus; | |
1571 | } | |
1572 | ||
c1bfb577 MZ |
1573 | void kvm_vgic_destroy(struct kvm *kvm) |
1574 | { | |
1575 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1576 | struct kvm_vcpu *vcpu; | |
1577 | int i; | |
1578 | ||
1579 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1580 | kvm_vgic_vcpu_destroy(vcpu); | |
1581 | ||
1582 | vgic_free_bitmap(&dist->irq_enabled); | |
1583 | vgic_free_bitmap(&dist->irq_level); | |
1584 | vgic_free_bitmap(&dist->irq_pending); | |
1585 | vgic_free_bitmap(&dist->irq_soft_pend); | |
1586 | vgic_free_bitmap(&dist->irq_queued); | |
1587 | vgic_free_bitmap(&dist->irq_cfg); | |
1588 | vgic_free_bytemap(&dist->irq_priority); | |
1589 | if (dist->irq_spi_target) { | |
1590 | for (i = 0; i < dist->nr_cpus; i++) | |
1591 | vgic_free_bitmap(&dist->irq_spi_target[i]); | |
1592 | } | |
1593 | kfree(dist->irq_sgi_sources); | |
1594 | kfree(dist->irq_spi_cpu); | |
a0675c25 | 1595 | kfree(dist->irq_spi_mpidr); |
c1bfb577 MZ |
1596 | kfree(dist->irq_spi_target); |
1597 | kfree(dist->irq_pending_on_cpu); | |
47a98b15 | 1598 | kfree(dist->irq_active_on_cpu); |
c1bfb577 MZ |
1599 | dist->irq_sgi_sources = NULL; |
1600 | dist->irq_spi_cpu = NULL; | |
1601 | dist->irq_spi_target = NULL; | |
1602 | dist->irq_pending_on_cpu = NULL; | |
47a98b15 | 1603 | dist->irq_active_on_cpu = NULL; |
1f57be28 | 1604 | dist->nr_cpus = 0; |
c1bfb577 MZ |
1605 | } |
1606 | ||
1607 | /* | |
1608 | * Allocate and initialize the various data structures. Must be called | |
1609 | * with kvm->lock held! | |
1610 | */ | |
83215812 | 1611 | int vgic_init(struct kvm *kvm) |
c1bfb577 MZ |
1612 | { |
1613 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1614 | struct kvm_vcpu *vcpu; | |
1615 | int nr_cpus, nr_irqs; | |
6d3cfbe2 | 1616 | int ret, i, vcpu_id; |
c1bfb577 | 1617 | |
1f57be28 | 1618 | if (vgic_initialized(kvm)) |
4956f2bc MZ |
1619 | return 0; |
1620 | ||
1621 | nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus); | |
1622 | if (!nr_cpus) /* No vcpus? Can't be good... */ | |
66b030e4 | 1623 | return -ENODEV; |
5fb66da6 | 1624 | |
4956f2bc MZ |
1625 | /* |
1626 | * If nobody configured the number of interrupts, use the | |
1627 | * legacy one. | |
1628 | */ | |
5fb66da6 MZ |
1629 | if (!dist->nr_irqs) |
1630 | dist->nr_irqs = VGIC_NR_IRQS_LEGACY; | |
1631 | ||
1632 | nr_irqs = dist->nr_irqs; | |
c1bfb577 MZ |
1633 | |
1634 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); | |
1635 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); | |
1636 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); | |
1637 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); | |
1638 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); | |
47a98b15 | 1639 | ret |= vgic_init_bitmap(&dist->irq_active, nr_cpus, nr_irqs); |
c1bfb577 MZ |
1640 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); |
1641 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); | |
1642 | ||
1643 | if (ret) | |
1644 | goto out; | |
1645 | ||
1646 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); | |
1647 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); | |
1648 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, | |
1649 | GFP_KERNEL); | |
1650 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), | |
1651 | GFP_KERNEL); | |
47a98b15 CD |
1652 | dist->irq_active_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), |
1653 | GFP_KERNEL); | |
c1bfb577 MZ |
1654 | if (!dist->irq_sgi_sources || |
1655 | !dist->irq_spi_cpu || | |
1656 | !dist->irq_spi_target || | |
47a98b15 CD |
1657 | !dist->irq_pending_on_cpu || |
1658 | !dist->irq_active_on_cpu) { | |
c1bfb577 MZ |
1659 | ret = -ENOMEM; |
1660 | goto out; | |
1661 | } | |
1662 | ||
1663 | for (i = 0; i < nr_cpus; i++) | |
1664 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], | |
1665 | nr_cpus, nr_irqs); | |
1666 | ||
1667 | if (ret) | |
1668 | goto out; | |
1669 | ||
b26e5fda AP |
1670 | ret = kvm->arch.vgic.vm_ops.init_model(kvm); |
1671 | if (ret) | |
1672 | goto out; | |
6d3cfbe2 PM |
1673 | |
1674 | kvm_for_each_vcpu(vcpu_id, vcpu, kvm) { | |
c1bfb577 MZ |
1675 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); |
1676 | if (ret) { | |
1677 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); | |
1678 | break; | |
1679 | } | |
c1bfb577 | 1680 | |
6d3cfbe2 PM |
1681 | for (i = 0; i < dist->nr_irqs; i++) { |
1682 | if (i < VGIC_NR_PPIS) | |
1683 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1684 | vcpu->vcpu_id, i, 1); | |
1685 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1686 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1687 | vcpu->vcpu_id, i, | |
1688 | VGIC_CFG_EDGE); | |
1689 | } | |
1690 | ||
1691 | vgic_enable(vcpu); | |
1692 | } | |
4956f2bc | 1693 | |
c1bfb577 MZ |
1694 | out: |
1695 | if (ret) | |
1696 | kvm_vgic_destroy(kvm); | |
1697 | ||
1698 | return ret; | |
1699 | } | |
1700 | ||
b26e5fda AP |
1701 | static int init_vgic_model(struct kvm *kvm, int type) |
1702 | { | |
1703 | switch (type) { | |
1704 | case KVM_DEV_TYPE_ARM_VGIC_V2: | |
1705 | vgic_v2_init_emulation(kvm); | |
1706 | break; | |
b5d84ff6 AP |
1707 | #ifdef CONFIG_ARM_GIC_V3 |
1708 | case KVM_DEV_TYPE_ARM_VGIC_V3: | |
1709 | vgic_v3_init_emulation(kvm); | |
1710 | break; | |
1711 | #endif | |
b26e5fda AP |
1712 | default: |
1713 | return -ENODEV; | |
1714 | } | |
1715 | ||
3caa2d8c AP |
1716 | if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus) |
1717 | return -E2BIG; | |
1718 | ||
b26e5fda AP |
1719 | return 0; |
1720 | } | |
1721 | ||
59892136 | 1722 | int kvm_vgic_create(struct kvm *kvm, u32 type) |
01ac5e34 | 1723 | { |
6b50f540 | 1724 | int i, vcpu_lock_idx = -1, ret; |
7330672b | 1725 | struct kvm_vcpu *vcpu; |
01ac5e34 MZ |
1726 | |
1727 | mutex_lock(&kvm->lock); | |
1728 | ||
4ce7ebdf | 1729 | if (irqchip_in_kernel(kvm)) { |
01ac5e34 MZ |
1730 | ret = -EEXIST; |
1731 | goto out; | |
1732 | } | |
1733 | ||
b5d84ff6 AP |
1734 | /* |
1735 | * This function is also called by the KVM_CREATE_IRQCHIP handler, | |
1736 | * which had no chance yet to check the availability of the GICv2 | |
1737 | * emulation. So check this here again. KVM_CREATE_DEVICE does | |
1738 | * the proper checks already. | |
1739 | */ | |
1740 | if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) | |
1741 | return -ENODEV; | |
1742 | ||
7330672b CD |
1743 | /* |
1744 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1745 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1746 | * that no other VCPUs are run while we create the vgic. | |
1747 | */ | |
6b50f540 | 1748 | ret = -EBUSY; |
7330672b CD |
1749 | kvm_for_each_vcpu(i, vcpu, kvm) { |
1750 | if (!mutex_trylock(&vcpu->mutex)) | |
1751 | goto out_unlock; | |
1752 | vcpu_lock_idx = i; | |
1753 | } | |
1754 | ||
1755 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6b50f540 | 1756 | if (vcpu->arch.has_run_once) |
7330672b | 1757 | goto out_unlock; |
7330672b | 1758 | } |
6b50f540 | 1759 | ret = 0; |
7330672b | 1760 | |
b26e5fda AP |
1761 | ret = init_vgic_model(kvm, type); |
1762 | if (ret) | |
1763 | goto out_unlock; | |
1764 | ||
01ac5e34 | 1765 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1766 | kvm->arch.vgic.in_kernel = true; |
59892136 | 1767 | kvm->arch.vgic.vgic_model = type; |
8f186d52 | 1768 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1769 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1770 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
a0675c25 | 1771 | kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; |
01ac5e34 | 1772 | |
7330672b CD |
1773 | out_unlock: |
1774 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1775 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1776 | mutex_unlock(&vcpu->mutex); | |
1777 | } | |
1778 | ||
01ac5e34 MZ |
1779 | out: |
1780 | mutex_unlock(&kvm->lock); | |
1781 | return ret; | |
1782 | } | |
1783 | ||
1fa451bc | 1784 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
1785 | { |
1786 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1787 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1788 | ||
1789 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1790 | return 0; | |
1791 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1792 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1793 | return -EBUSY; | |
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1798 | phys_addr_t addr, phys_addr_t size) | |
1799 | { | |
1800 | int ret; | |
1801 | ||
ce01e4e8 CD |
1802 | if (addr & ~KVM_PHYS_MASK) |
1803 | return -E2BIG; | |
1804 | ||
1805 | if (addr & (SZ_4K - 1)) | |
1806 | return -EINVAL; | |
1807 | ||
330690cd CD |
1808 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1809 | return -EEXIST; | |
1810 | if (addr + size < addr) | |
1811 | return -EINVAL; | |
1812 | ||
30c21170 | 1813 | *ioaddr = addr; |
330690cd CD |
1814 | ret = vgic_ioaddr_overlap(kvm); |
1815 | if (ret) | |
30c21170 HW |
1816 | *ioaddr = VGIC_ADDR_UNDEF; |
1817 | ||
330690cd CD |
1818 | return ret; |
1819 | } | |
1820 | ||
ce01e4e8 CD |
1821 | /** |
1822 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1823 | * @kvm: pointer to the vm struct | |
ac3d3735 | 1824 | * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX |
ce01e4e8 CD |
1825 | * @addr: pointer to address value |
1826 | * @write: if true set the address in the VM address space, if false read the | |
1827 | * address | |
1828 | * | |
1829 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1830 | * interface in the VM physical address space. These addresses are properties | |
1831 | * of the emulated core/SoC and therefore user space initially knows this | |
1832 | * information. | |
1833 | */ | |
1834 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1835 | { |
1836 | int r = 0; | |
1837 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
ac3d3735 AP |
1838 | int type_needed; |
1839 | phys_addr_t *addr_ptr, block_size; | |
4fa96afd | 1840 | phys_addr_t alignment; |
330690cd | 1841 | |
330690cd CD |
1842 | mutex_lock(&kvm->lock); |
1843 | switch (type) { | |
1844 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ac3d3735 AP |
1845 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
1846 | addr_ptr = &vgic->vgic_dist_base; | |
1847 | block_size = KVM_VGIC_V2_DIST_SIZE; | |
4fa96afd | 1848 | alignment = SZ_4K; |
330690cd CD |
1849 | break; |
1850 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ac3d3735 AP |
1851 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V2; |
1852 | addr_ptr = &vgic->vgic_cpu_base; | |
1853 | block_size = KVM_VGIC_V2_CPU_SIZE; | |
4fa96afd | 1854 | alignment = SZ_4K; |
330690cd | 1855 | break; |
ac3d3735 AP |
1856 | #ifdef CONFIG_ARM_GIC_V3 |
1857 | case KVM_VGIC_V3_ADDR_TYPE_DIST: | |
1858 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
1859 | addr_ptr = &vgic->vgic_dist_base; | |
1860 | block_size = KVM_VGIC_V3_DIST_SIZE; | |
4fa96afd | 1861 | alignment = SZ_64K; |
ac3d3735 AP |
1862 | break; |
1863 | case KVM_VGIC_V3_ADDR_TYPE_REDIST: | |
1864 | type_needed = KVM_DEV_TYPE_ARM_VGIC_V3; | |
1865 | addr_ptr = &vgic->vgic_redist_base; | |
1866 | block_size = KVM_VGIC_V3_REDIST_SIZE; | |
4fa96afd | 1867 | alignment = SZ_64K; |
ac3d3735 AP |
1868 | break; |
1869 | #endif | |
330690cd CD |
1870 | default: |
1871 | r = -ENODEV; | |
ac3d3735 AP |
1872 | goto out; |
1873 | } | |
1874 | ||
1875 | if (vgic->vgic_model != type_needed) { | |
1876 | r = -ENODEV; | |
1877 | goto out; | |
330690cd CD |
1878 | } |
1879 | ||
4fa96afd AP |
1880 | if (write) { |
1881 | if (!IS_ALIGNED(*addr, alignment)) | |
1882 | r = -EINVAL; | |
1883 | else | |
1884 | r = vgic_ioaddr_assign(kvm, addr_ptr, *addr, | |
1885 | block_size); | |
1886 | } else { | |
ac3d3735 | 1887 | *addr = *addr_ptr; |
4fa96afd | 1888 | } |
ac3d3735 AP |
1889 | |
1890 | out: | |
330690cd CD |
1891 | mutex_unlock(&kvm->lock); |
1892 | return r; | |
1893 | } | |
7330672b | 1894 | |
83215812 | 1895 | int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 1896 | { |
ce01e4e8 CD |
1897 | int r; |
1898 | ||
1899 | switch (attr->group) { | |
1900 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1901 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1902 | u64 addr; | |
1903 | unsigned long type = (unsigned long)attr->attr; | |
1904 | ||
1905 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
1906 | return -EFAULT; | |
1907 | ||
1908 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
1909 | return (r == -ENODEV) ? -ENXIO : r; | |
1910 | } | |
a98f26f1 MZ |
1911 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
1912 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1913 | u32 val; | |
1914 | int ret = 0; | |
1915 | ||
1916 | if (get_user(val, uaddr)) | |
1917 | return -EFAULT; | |
1918 | ||
1919 | /* | |
1920 | * We require: | |
1921 | * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs | |
1922 | * - at most 1024 interrupts | |
1923 | * - a multiple of 32 interrupts | |
1924 | */ | |
1925 | if (val < (VGIC_NR_PRIVATE_IRQS + 32) || | |
1926 | val > VGIC_MAX_IRQS || | |
1927 | (val & 31)) | |
1928 | return -EINVAL; | |
1929 | ||
1930 | mutex_lock(&dev->kvm->lock); | |
1931 | ||
c52edf5f | 1932 | if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs) |
a98f26f1 MZ |
1933 | ret = -EBUSY; |
1934 | else | |
1935 | dev->kvm->arch.vgic.nr_irqs = val; | |
1936 | ||
1937 | mutex_unlock(&dev->kvm->lock); | |
1938 | ||
1939 | return ret; | |
1940 | } | |
065c0034 EA |
1941 | case KVM_DEV_ARM_VGIC_GRP_CTRL: { |
1942 | switch (attr->attr) { | |
1943 | case KVM_DEV_ARM_VGIC_CTRL_INIT: | |
1944 | r = vgic_init(dev->kvm); | |
1945 | return r; | |
1946 | } | |
1947 | break; | |
1948 | } | |
ce01e4e8 CD |
1949 | } |
1950 | ||
7330672b CD |
1951 | return -ENXIO; |
1952 | } | |
1953 | ||
83215812 | 1954 | int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
7330672b | 1955 | { |
ce01e4e8 CD |
1956 | int r = -ENXIO; |
1957 | ||
1958 | switch (attr->group) { | |
1959 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1960 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1961 | u64 addr; | |
1962 | unsigned long type = (unsigned long)attr->attr; | |
1963 | ||
1964 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
1965 | if (r) | |
1966 | return (r == -ENODEV) ? -ENXIO : r; | |
1967 | ||
1968 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
1969 | return -EFAULT; | |
c07a0191 CD |
1970 | break; |
1971 | } | |
b60da146 AP |
1972 | case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: { |
1973 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1974 | ||
1975 | r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr); | |
1976 | break; | |
1977 | } | |
1978 | ||
1979 | } | |
1980 | ||
1981 | return r; | |
1982 | } | |
1983 | ||
cf50a1eb | 1984 | int vgic_has_attr_regs(const struct vgic_io_range *ranges, phys_addr_t offset) |
c07a0191 | 1985 | { |
9f199d0a | 1986 | if (vgic_find_range(ranges, 4, offset)) |
c07a0191 CD |
1987 | return 0; |
1988 | else | |
1989 | return -ENXIO; | |
1990 | } | |
1991 | ||
c06a841b WD |
1992 | static void vgic_init_maintenance_interrupt(void *info) |
1993 | { | |
1994 | enable_percpu_irq(vgic->maint_irq, 0); | |
1995 | } | |
1996 | ||
1997 | static int vgic_cpu_notify(struct notifier_block *self, | |
1998 | unsigned long action, void *cpu) | |
1999 | { | |
2000 | switch (action) { | |
2001 | case CPU_STARTING: | |
2002 | case CPU_STARTING_FROZEN: | |
2003 | vgic_init_maintenance_interrupt(NULL); | |
2004 | break; | |
2005 | case CPU_DYING: | |
2006 | case CPU_DYING_FROZEN: | |
2007 | disable_percpu_irq(vgic->maint_irq); | |
2008 | break; | |
2009 | } | |
2010 | ||
2011 | return NOTIFY_OK; | |
2012 | } | |
2013 | ||
2014 | static struct notifier_block vgic_cpu_nb = { | |
2015 | .notifier_call = vgic_cpu_notify, | |
2016 | }; | |
2017 | ||
2018 | static const struct of_device_id vgic_ids[] = { | |
0f372475 MR |
2019 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, |
2020 | { .compatible = "arm,cortex-a7-gic", .data = vgic_v2_probe, }, | |
2021 | { .compatible = "arm,gic-400", .data = vgic_v2_probe, }, | |
2022 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
c06a841b WD |
2023 | {}, |
2024 | }; | |
2025 | ||
2026 | int kvm_vgic_hyp_init(void) | |
2027 | { | |
2028 | const struct of_device_id *matched_id; | |
a875dafc CD |
2029 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2030 | const struct vgic_params **); | |
c06a841b WD |
2031 | struct device_node *vgic_node; |
2032 | int ret; | |
2033 | ||
2034 | vgic_node = of_find_matching_node_and_match(NULL, | |
2035 | vgic_ids, &matched_id); | |
2036 | if (!vgic_node) { | |
2037 | kvm_err("error: no compatible GIC node found\n"); | |
2038 | return -ENODEV; | |
2039 | } | |
2040 | ||
2041 | vgic_probe = matched_id->data; | |
2042 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2043 | if (ret) | |
2044 | return ret; | |
2045 | ||
2046 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2047 | "vgic", kvm_get_running_vcpus()); | |
2048 | if (ret) { | |
2049 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2050 | return ret; | |
2051 | } | |
2052 | ||
2053 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2054 | if (ret) { | |
2055 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2056 | goto out_free_irq; | |
2057 | } | |
2058 | ||
2059 | /* Callback into for arch code for setup */ | |
2060 | vgic_arch_setup(vgic); | |
2061 | ||
2062 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
2063 | ||
ea2f83a7 | 2064 | return 0; |
c06a841b WD |
2065 | |
2066 | out_free_irq: | |
2067 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2068 | return ret; | |
2069 | } | |
174178fe EA |
2070 | |
2071 | int kvm_irq_map_gsi(struct kvm *kvm, | |
2072 | struct kvm_kernel_irq_routing_entry *entries, | |
2073 | int gsi) | |
2074 | { | |
2075 | return gsi; | |
2076 | } | |
2077 | ||
2078 | int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin) | |
2079 | { | |
2080 | return pin; | |
2081 | } | |
2082 | ||
2083 | int kvm_set_irq(struct kvm *kvm, int irq_source_id, | |
2084 | u32 irq, int level, bool line_status) | |
2085 | { | |
2086 | unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS; | |
2087 | ||
2088 | trace_kvm_set_irq(irq, level, irq_source_id); | |
2089 | ||
2090 | BUG_ON(!vgic_initialized(kvm)); | |
2091 | ||
2092 | if (spi > kvm->arch.vgic.nr_irqs) | |
2093 | return -EINVAL; | |
2094 | return kvm_vgic_inject_irq(kvm, 0, spi, level); | |
2095 | ||
2096 | } | |
2097 | ||
2098 | /* MSI not implemented yet */ | |
2099 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, | |
2100 | struct kvm *kvm, int irq_source_id, | |
2101 | int level, bool line_status) | |
2102 | { | |
2103 | return 0; | |
2104 | } |