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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
7e362919 CD |
39 | * something is pending on the CPU interface. |
40 | * - Interrupts that are pending on the distributor are stored on the | |
41 | * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land | |
42 | * ioctls and guest mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers). | |
b47ef92a MZ |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
48 | * - PPI: dist->irq_pending & dist->irq_enable |
49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
7e362919 | 50 | * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn |
b47ef92a MZ |
51 | * registers, stored on each vcpu. We only keep one bit of |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
7e362919 | 54 | * - If any of the above state changes, we must recalculate the oracle. |
b47ef92a MZ |
55 | * - The same is true when injecting an interrupt, except that we only |
56 | * consider a single interrupt at a time. The irq_spi_cpu array | |
57 | * contains the target CPU for each SPI. | |
58 | * | |
59 | * The handling of level interrupts adds some extra complexity. We | |
60 | * need to track when the interrupt has been EOIed, so we can sample | |
61 | * the 'line' again. This is achieved as such: | |
62 | * | |
63 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 64 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
65 | * will be ignored for further interrupts. The interrupt is injected |
66 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
67 | * maintenance interrupt on EOI). | |
68 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 69 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a | 70 | * interrupt line to be sampled again. |
faa1b46c CD |
71 | * - Note that level-triggered interrupts can also be set to pending from |
72 | * writes to GICD_ISPENDRn and lowering the external input line does not | |
73 | * cause the interrupt to become inactive in such a situation. | |
74 | * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become | |
75 | * inactive as long as the external input line is held high. | |
b47ef92a MZ |
76 | */ |
77 | ||
330690cd CD |
78 | #define VGIC_ADDR_UNDEF (-1) |
79 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) | |
80 | ||
fa20f5ae CD |
81 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
82 | #define IMPLEMENTER_ARM 0x43b | |
83 | #define GICC_ARCH_VERSION_V2 0x2 | |
84 | ||
1a89dd91 MZ |
85 | #define ACCESS_READ_VALUE (1 << 0) |
86 | #define ACCESS_READ_RAZ (0 << 0) | |
87 | #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) | |
88 | #define ACCESS_WRITE_IGNORED (0 << 1) | |
89 | #define ACCESS_WRITE_SETBIT (1 << 1) | |
90 | #define ACCESS_WRITE_CLEARBIT (2 << 1) | |
91 | #define ACCESS_WRITE_VALUE (3 << 1) | |
92 | #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) | |
93 | ||
a1fcb44e | 94 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 95 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
b47ef92a | 96 | static void vgic_update_state(struct kvm *kvm); |
5863c2ce | 97 | static void vgic_kick_vcpus(struct kvm *kvm); |
c1bfb577 | 98 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi); |
b47ef92a | 99 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
8d5c6b06 MZ |
100 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
101 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
beee38b9 MZ |
102 | static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
103 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
01ac5e34 | 104 | |
8f186d52 MZ |
105 | static const struct vgic_ops *vgic_ops; |
106 | static const struct vgic_params *vgic; | |
b47ef92a | 107 | |
9662fb48 | 108 | /* |
c1bfb577 MZ |
109 | * struct vgic_bitmap contains a bitmap made of unsigned longs, but |
110 | * extracts u32s out of them. | |
9662fb48 VK |
111 | * |
112 | * This does not work on 64-bit BE systems, because the bitmap access | |
113 | * will store two consecutive 32-bit words with the higher-addressed | |
114 | * register's bits at the lower index and the lower-addressed register's | |
115 | * bits at the higher index. | |
116 | * | |
117 | * Therefore, swizzle the register index when accessing the 32-bit word | |
118 | * registers to access the right register's value. | |
119 | */ | |
120 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
121 | #define REG_OFFSET_SWIZZLE 1 | |
122 | #else | |
123 | #define REG_OFFSET_SWIZZLE 0 | |
124 | #endif | |
b47ef92a | 125 | |
c1bfb577 MZ |
126 | static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) |
127 | { | |
128 | int nr_longs; | |
129 | ||
130 | nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); | |
131 | ||
132 | b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); | |
133 | if (!b->private) | |
134 | return -ENOMEM; | |
135 | ||
136 | b->shared = b->private + nr_cpus; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static void vgic_free_bitmap(struct vgic_bitmap *b) | |
142 | { | |
143 | kfree(b->private); | |
144 | b->private = NULL; | |
145 | b->shared = NULL; | |
146 | } | |
147 | ||
b47ef92a MZ |
148 | static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, |
149 | int cpuid, u32 offset) | |
150 | { | |
151 | offset >>= 2; | |
152 | if (!offset) | |
c1bfb577 | 153 | return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; |
b47ef92a | 154 | else |
c1bfb577 | 155 | return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
156 | } |
157 | ||
158 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
159 | int cpuid, int irq) | |
160 | { | |
161 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
c1bfb577 | 162 | return test_bit(irq, x->private + cpuid); |
b47ef92a | 163 | |
c1bfb577 | 164 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); |
b47ef92a MZ |
165 | } |
166 | ||
167 | static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, | |
168 | int irq, int val) | |
169 | { | |
170 | unsigned long *reg; | |
171 | ||
172 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
c1bfb577 | 173 | reg = x->private + cpuid; |
b47ef92a | 174 | } else { |
c1bfb577 | 175 | reg = x->shared; |
b47ef92a MZ |
176 | irq -= VGIC_NR_PRIVATE_IRQS; |
177 | } | |
178 | ||
179 | if (val) | |
180 | set_bit(irq, reg); | |
181 | else | |
182 | clear_bit(irq, reg); | |
183 | } | |
184 | ||
185 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
186 | { | |
c1bfb577 | 187 | return x->private + cpuid; |
b47ef92a MZ |
188 | } |
189 | ||
190 | static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) | |
191 | { | |
c1bfb577 MZ |
192 | return x->shared; |
193 | } | |
194 | ||
195 | static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) | |
196 | { | |
197 | int size; | |
198 | ||
199 | size = nr_cpus * VGIC_NR_PRIVATE_IRQS; | |
200 | size += nr_irqs - VGIC_NR_PRIVATE_IRQS; | |
201 | ||
202 | x->private = kzalloc(size, GFP_KERNEL); | |
203 | if (!x->private) | |
204 | return -ENOMEM; | |
205 | ||
206 | x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static void vgic_free_bytemap(struct vgic_bytemap *b) | |
211 | { | |
212 | kfree(b->private); | |
213 | b->private = NULL; | |
214 | b->shared = NULL; | |
b47ef92a MZ |
215 | } |
216 | ||
217 | static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) | |
218 | { | |
c1bfb577 MZ |
219 | u32 *reg; |
220 | ||
221 | if (offset < VGIC_NR_PRIVATE_IRQS) { | |
222 | reg = x->private; | |
223 | offset += cpuid * VGIC_NR_PRIVATE_IRQS; | |
224 | } else { | |
225 | reg = x->shared; | |
226 | offset -= VGIC_NR_PRIVATE_IRQS; | |
227 | } | |
228 | ||
229 | return reg + (offset / sizeof(u32)); | |
b47ef92a MZ |
230 | } |
231 | ||
232 | #define VGIC_CFG_LEVEL 0 | |
233 | #define VGIC_CFG_EDGE 1 | |
234 | ||
235 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
236 | { | |
237 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
238 | int irq_val; | |
239 | ||
240 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
241 | return irq_val == VGIC_CFG_EDGE; | |
242 | } | |
243 | ||
244 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
245 | { | |
246 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
247 | ||
248 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
249 | } | |
250 | ||
dbf20f9d | 251 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
252 | { |
253 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
254 | ||
dbf20f9d | 255 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
256 | } |
257 | ||
dbf20f9d | 258 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
259 | { |
260 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
261 | ||
dbf20f9d | 262 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
263 | } |
264 | ||
dbf20f9d | 265 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
266 | { |
267 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
268 | ||
dbf20f9d | 269 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
270 | } |
271 | ||
faa1b46c CD |
272 | static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq) |
273 | { | |
274 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
275 | ||
276 | return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq); | |
277 | } | |
278 | ||
279 | static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq) | |
280 | { | |
281 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
282 | ||
283 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1); | |
284 | } | |
285 | ||
286 | static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq) | |
287 | { | |
288 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
289 | ||
290 | vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0); | |
291 | } | |
292 | ||
293 | static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
294 | { | |
295 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
296 | ||
297 | return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq); | |
298 | } | |
299 | ||
300 | static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq) | |
301 | { | |
302 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
303 | ||
304 | vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0); | |
305 | } | |
306 | ||
9d949dce MZ |
307 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) |
308 | { | |
309 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
310 | ||
227844f5 | 311 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
312 | } |
313 | ||
227844f5 | 314 | static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
315 | { |
316 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
317 | ||
227844f5 | 318 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
319 | } |
320 | ||
227844f5 | 321 | static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
322 | { |
323 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
324 | ||
227844f5 | 325 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
326 | } |
327 | ||
328 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
329 | { | |
330 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
331 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
332 | else | |
333 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
334 | vcpu->arch.vgic_cpu.pending_shared); | |
335 | } | |
336 | ||
337 | static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
338 | { | |
339 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
340 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
341 | else | |
342 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
343 | vcpu->arch.vgic_cpu.pending_shared); | |
344 | } | |
345 | ||
dbf20f9d CD |
346 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
347 | { | |
348 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
349 | } | |
350 | ||
1a89dd91 MZ |
351 | static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) |
352 | { | |
1c9f0471 | 353 | return le32_to_cpu(*((u32 *)mmio->data)) & mask; |
1a89dd91 MZ |
354 | } |
355 | ||
356 | static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) | |
357 | { | |
1c9f0471 | 358 | *((u32 *)mmio->data) = cpu_to_le32(value) & mask; |
1a89dd91 MZ |
359 | } |
360 | ||
361 | /** | |
362 | * vgic_reg_access - access vgic register | |
363 | * @mmio: pointer to the data describing the mmio access | |
364 | * @reg: pointer to the virtual backing of vgic distributor data | |
365 | * @offset: least significant 2 bits used for word offset | |
366 | * @mode: ACCESS_ mode (see defines above) | |
367 | * | |
368 | * Helper to make vgic register access easier using one of the access | |
369 | * modes defined for vgic register access | |
370 | * (read,raz,write-ignored,setbit,clearbit,write) | |
371 | */ | |
372 | static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, | |
373 | phys_addr_t offset, int mode) | |
374 | { | |
375 | int word_offset = (offset & 3) * 8; | |
376 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
377 | u32 regval; | |
378 | ||
379 | /* | |
380 | * Any alignment fault should have been delivered to the guest | |
381 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
382 | */ | |
383 | ||
384 | if (reg) { | |
385 | regval = *reg; | |
386 | } else { | |
387 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
388 | regval = 0; | |
389 | } | |
390 | ||
391 | if (mmio->is_write) { | |
392 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
393 | switch (ACCESS_WRITE_MASK(mode)) { | |
394 | case ACCESS_WRITE_IGNORED: | |
395 | return; | |
396 | ||
397 | case ACCESS_WRITE_SETBIT: | |
398 | regval |= data; | |
399 | break; | |
400 | ||
401 | case ACCESS_WRITE_CLEARBIT: | |
402 | regval &= ~data; | |
403 | break; | |
404 | ||
405 | case ACCESS_WRITE_VALUE: | |
406 | regval = (regval & ~(mask << word_offset)) | data; | |
407 | break; | |
408 | } | |
409 | *reg = regval; | |
410 | } else { | |
411 | switch (ACCESS_READ_MASK(mode)) { | |
412 | case ACCESS_READ_RAZ: | |
413 | regval = 0; | |
414 | /* fall through */ | |
415 | ||
416 | case ACCESS_READ_VALUE: | |
417 | mmio_data_write(mmio, mask, regval >> word_offset); | |
418 | } | |
419 | } | |
420 | } | |
421 | ||
b47ef92a MZ |
422 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
423 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
424 | { | |
425 | u32 reg; | |
426 | u32 word_offset = offset & 3; | |
427 | ||
428 | switch (offset & ~3) { | |
fa20f5ae | 429 | case 0: /* GICD_CTLR */ |
b47ef92a MZ |
430 | reg = vcpu->kvm->arch.vgic.enabled; |
431 | vgic_reg_access(mmio, ®, word_offset, | |
432 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
433 | if (mmio->is_write) { | |
434 | vcpu->kvm->arch.vgic.enabled = reg & 1; | |
435 | vgic_update_state(vcpu->kvm); | |
436 | return true; | |
437 | } | |
438 | break; | |
439 | ||
fa20f5ae | 440 | case 4: /* GICD_TYPER */ |
b47ef92a MZ |
441 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
442 | reg |= (VGIC_NR_IRQS >> 5) - 1; | |
443 | vgic_reg_access(mmio, ®, word_offset, | |
444 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
445 | break; | |
446 | ||
fa20f5ae CD |
447 | case 8: /* GICD_IIDR */ |
448 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
b47ef92a MZ |
449 | vgic_reg_access(mmio, ®, word_offset, |
450 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
451 | break; | |
452 | } | |
453 | ||
454 | return false; | |
455 | } | |
456 | ||
457 | static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, | |
458 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
459 | { | |
460 | vgic_reg_access(mmio, NULL, offset, | |
461 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
462 | return false; | |
463 | } | |
464 | ||
465 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, | |
466 | struct kvm_exit_mmio *mmio, | |
467 | phys_addr_t offset) | |
468 | { | |
469 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
470 | vcpu->vcpu_id, offset); | |
471 | vgic_reg_access(mmio, reg, offset, | |
472 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
473 | if (mmio->is_write) { | |
474 | vgic_update_state(vcpu->kvm); | |
475 | return true; | |
476 | } | |
477 | ||
478 | return false; | |
479 | } | |
480 | ||
481 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, | |
482 | struct kvm_exit_mmio *mmio, | |
483 | phys_addr_t offset) | |
484 | { | |
485 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
486 | vcpu->vcpu_id, offset); | |
487 | vgic_reg_access(mmio, reg, offset, | |
488 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
489 | if (mmio->is_write) { | |
490 | if (offset < 4) /* Force SGI enabled */ | |
491 | *reg |= 0xffff; | |
a1fcb44e | 492 | vgic_retire_disabled_irqs(vcpu); |
b47ef92a MZ |
493 | vgic_update_state(vcpu->kvm); |
494 | return true; | |
495 | } | |
496 | ||
497 | return false; | |
498 | } | |
499 | ||
500 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, | |
501 | struct kvm_exit_mmio *mmio, | |
502 | phys_addr_t offset) | |
503 | { | |
9da48b55 | 504 | u32 *reg, orig; |
faa1b46c CD |
505 | u32 level_mask; |
506 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
507 | ||
508 | reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset); | |
509 | level_mask = (~(*reg)); | |
510 | ||
511 | /* Mark both level and edge triggered irqs as pending */ | |
512 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 513 | orig = *reg; |
b47ef92a MZ |
514 | vgic_reg_access(mmio, reg, offset, |
515 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
faa1b46c | 516 | |
b47ef92a | 517 | if (mmio->is_write) { |
faa1b46c CD |
518 | /* Set the soft-pending flag only for level-triggered irqs */ |
519 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
520 | vcpu->vcpu_id, offset); | |
521 | vgic_reg_access(mmio, reg, offset, | |
522 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
523 | *reg &= level_mask; | |
524 | ||
9da48b55 CD |
525 | /* Ignore writes to SGIs */ |
526 | if (offset < 2) { | |
527 | *reg &= ~0xffff; | |
528 | *reg |= orig & 0xffff; | |
529 | } | |
530 | ||
b47ef92a MZ |
531 | vgic_update_state(vcpu->kvm); |
532 | return true; | |
533 | } | |
534 | ||
535 | return false; | |
536 | } | |
537 | ||
538 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, | |
539 | struct kvm_exit_mmio *mmio, | |
540 | phys_addr_t offset) | |
541 | { | |
faa1b46c | 542 | u32 *level_active; |
9da48b55 | 543 | u32 *reg, orig; |
faa1b46c CD |
544 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
545 | ||
546 | reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset); | |
9da48b55 | 547 | orig = *reg; |
b47ef92a MZ |
548 | vgic_reg_access(mmio, reg, offset, |
549 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
550 | if (mmio->is_write) { | |
faa1b46c CD |
551 | /* Re-set level triggered level-active interrupts */ |
552 | level_active = vgic_bitmap_get_reg(&dist->irq_level, | |
553 | vcpu->vcpu_id, offset); | |
554 | reg = vgic_bitmap_get_reg(&dist->irq_pending, | |
555 | vcpu->vcpu_id, offset); | |
556 | *reg |= *level_active; | |
557 | ||
9da48b55 CD |
558 | /* Ignore writes to SGIs */ |
559 | if (offset < 2) { | |
560 | *reg &= ~0xffff; | |
561 | *reg |= orig & 0xffff; | |
562 | } | |
563 | ||
faa1b46c CD |
564 | /* Clear soft-pending flags */ |
565 | reg = vgic_bitmap_get_reg(&dist->irq_soft_pend, | |
566 | vcpu->vcpu_id, offset); | |
567 | vgic_reg_access(mmio, reg, offset, | |
568 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
569 | ||
b47ef92a MZ |
570 | vgic_update_state(vcpu->kvm); |
571 | return true; | |
572 | } | |
573 | ||
574 | return false; | |
575 | } | |
576 | ||
577 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, | |
578 | struct kvm_exit_mmio *mmio, | |
579 | phys_addr_t offset) | |
580 | { | |
581 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, | |
582 | vcpu->vcpu_id, offset); | |
583 | vgic_reg_access(mmio, reg, offset, | |
584 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
585 | return false; | |
586 | } | |
587 | ||
588 | #define GICD_ITARGETSR_SIZE 32 | |
589 | #define GICD_CPUTARGETS_BITS 8 | |
590 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) | |
591 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) | |
592 | { | |
593 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986af8e0 | 594 | int i; |
b47ef92a MZ |
595 | u32 val = 0; |
596 | ||
597 | irq -= VGIC_NR_PRIVATE_IRQS; | |
598 | ||
986af8e0 MZ |
599 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
600 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); | |
b47ef92a MZ |
601 | |
602 | return val; | |
603 | } | |
604 | ||
605 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) | |
606 | { | |
607 | struct vgic_dist *dist = &kvm->arch.vgic; | |
608 | struct kvm_vcpu *vcpu; | |
609 | int i, c; | |
610 | unsigned long *bmap; | |
611 | u32 target; | |
612 | ||
613 | irq -= VGIC_NR_PRIVATE_IRQS; | |
614 | ||
615 | /* | |
616 | * Pick the LSB in each byte. This ensures we target exactly | |
617 | * one vcpu per IRQ. If the byte is null, assume we target | |
618 | * CPU0. | |
619 | */ | |
620 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { | |
621 | int shift = i * GICD_CPUTARGETS_BITS; | |
622 | target = ffs((val >> shift) & 0xffU); | |
623 | target = target ? (target - 1) : 0; | |
624 | dist->irq_spi_cpu[irq + i] = target; | |
625 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
626 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); | |
627 | if (c == target) | |
628 | set_bit(irq + i, bmap); | |
629 | else | |
630 | clear_bit(irq + i, bmap); | |
631 | } | |
632 | } | |
633 | } | |
634 | ||
635 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, | |
636 | struct kvm_exit_mmio *mmio, | |
637 | phys_addr_t offset) | |
638 | { | |
639 | u32 reg; | |
640 | ||
641 | /* We treat the banked interrupts targets as read-only */ | |
642 | if (offset < 32) { | |
643 | u32 roreg = 1 << vcpu->vcpu_id; | |
644 | roreg |= roreg << 8; | |
645 | roreg |= roreg << 16; | |
646 | ||
647 | vgic_reg_access(mmio, &roreg, offset, | |
648 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
649 | return false; | |
650 | } | |
651 | ||
652 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); | |
653 | vgic_reg_access(mmio, ®, offset, | |
654 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
655 | if (mmio->is_write) { | |
656 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); | |
657 | vgic_update_state(vcpu->kvm); | |
658 | return true; | |
659 | } | |
660 | ||
661 | return false; | |
662 | } | |
663 | ||
664 | static u32 vgic_cfg_expand(u16 val) | |
665 | { | |
666 | u32 res = 0; | |
667 | int i; | |
668 | ||
669 | /* | |
670 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
671 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
672 | */ | |
673 | for (i = 0; i < 16; i++) | |
674 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
675 | ||
676 | return res; | |
677 | } | |
678 | ||
679 | static u16 vgic_cfg_compress(u32 val) | |
680 | { | |
681 | u16 res = 0; | |
682 | int i; | |
683 | ||
684 | /* | |
685 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
686 | * abcd...mnop which is what we really care about. | |
687 | */ | |
688 | for (i = 0; i < 16; i++) | |
689 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
690 | ||
691 | return res; | |
692 | } | |
693 | ||
694 | /* | |
695 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
696 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
697 | * two above functions to compress/expand the bits | |
698 | */ | |
699 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, | |
700 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
701 | { | |
702 | u32 val; | |
6545eae3 MZ |
703 | u32 *reg; |
704 | ||
6545eae3 | 705 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
f2ae85b2 | 706 | vcpu->vcpu_id, offset >> 1); |
6545eae3 | 707 | |
f2ae85b2 | 708 | if (offset & 4) |
b47ef92a MZ |
709 | val = *reg >> 16; |
710 | else | |
711 | val = *reg & 0xffff; | |
712 | ||
713 | val = vgic_cfg_expand(val); | |
714 | vgic_reg_access(mmio, &val, offset, | |
715 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
716 | if (mmio->is_write) { | |
f2ae85b2 | 717 | if (offset < 8) { |
b47ef92a MZ |
718 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
719 | return false; | |
720 | } | |
721 | ||
722 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 723 | if (offset & 4) { |
b47ef92a MZ |
724 | *reg &= 0xffff; |
725 | *reg |= val << 16; | |
726 | } else { | |
727 | *reg &= 0xffff << 16; | |
728 | *reg |= val; | |
729 | } | |
730 | } | |
731 | ||
732 | return false; | |
733 | } | |
734 | ||
735 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, | |
736 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
737 | { | |
738 | u32 reg; | |
739 | vgic_reg_access(mmio, ®, offset, | |
740 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); | |
741 | if (mmio->is_write) { | |
742 | vgic_dispatch_sgi(vcpu, reg); | |
743 | vgic_update_state(vcpu->kvm); | |
744 | return true; | |
745 | } | |
746 | ||
747 | return false; | |
748 | } | |
749 | ||
cbd333a4 CD |
750 | /** |
751 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
752 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
753 | * | |
754 | * Move any pending IRQs that have already been assigned to LRs back to the | |
755 | * emulated distributor state so that the complete emulated state can be read | |
756 | * from the main emulation structures without investigating the LRs. | |
757 | * | |
758 | * Note that IRQs in the active state in the LRs get their pending state moved | |
759 | * to the distributor but the active state stays in the LRs, because we don't | |
760 | * track the active state on the distributor side. | |
761 | */ | |
762 | static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) | |
763 | { | |
764 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
765 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
766 | int vcpu_id = vcpu->vcpu_id; | |
8d5c6b06 | 767 | int i; |
cbd333a4 CD |
768 | |
769 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 770 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
771 | |
772 | /* | |
773 | * There are three options for the state bits: | |
774 | * | |
775 | * 01: pending | |
776 | * 10: active | |
777 | * 11: pending and active | |
778 | * | |
779 | * If the LR holds only an active interrupt (not pending) then | |
780 | * just leave it alone. | |
781 | */ | |
8d5c6b06 | 782 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
783 | continue; |
784 | ||
785 | /* | |
786 | * Reestablish the pending state on the distributor and the | |
787 | * CPU interface. It may have already been pending, but that | |
788 | * is fine, then we are only setting a few bits that were | |
789 | * already set. | |
790 | */ | |
227844f5 | 791 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
8d5c6b06 | 792 | if (lr.irq < VGIC_NR_SGIS) |
c1bfb577 | 793 | *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source; |
8d5c6b06 MZ |
794 | lr.state &= ~LR_STATE_PENDING; |
795 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
796 | |
797 | /* | |
798 | * If there's no state left on the LR (it could still be | |
799 | * active), then the LR does not hold any useful info and can | |
800 | * be marked as free for other use. | |
801 | */ | |
cced50c9 | 802 | if (!(lr.state & LR_STATE_MASK)) { |
8d5c6b06 | 803 | vgic_retire_lr(i, lr.irq, vcpu); |
cced50c9 CD |
804 | vgic_irq_clear_queued(vcpu, lr.irq); |
805 | } | |
cbd333a4 CD |
806 | |
807 | /* Finally update the VGIC state. */ | |
808 | vgic_update_state(vcpu->kvm); | |
809 | } | |
810 | } | |
811 | ||
90a5355e CD |
812 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
813 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, | |
814 | struct kvm_exit_mmio *mmio, | |
815 | phys_addr_t offset) | |
c07a0191 | 816 | { |
90a5355e CD |
817 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
818 | int sgi; | |
819 | int min_sgi = (offset & ~0x3) * 4; | |
820 | int max_sgi = min_sgi + 3; | |
821 | int vcpu_id = vcpu->vcpu_id; | |
822 | u32 reg = 0; | |
823 | ||
824 | /* Copy source SGIs from distributor side */ | |
825 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
826 | int shift = 8 * (sgi - min_sgi); | |
c1bfb577 | 827 | reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift; |
90a5355e CD |
828 | } |
829 | ||
830 | mmio_data_write(mmio, ~0, reg); | |
c07a0191 CD |
831 | return false; |
832 | } | |
833 | ||
90a5355e CD |
834 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
835 | struct kvm_exit_mmio *mmio, | |
836 | phys_addr_t offset, bool set) | |
837 | { | |
838 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
839 | int sgi; | |
840 | int min_sgi = (offset & ~0x3) * 4; | |
841 | int max_sgi = min_sgi + 3; | |
842 | int vcpu_id = vcpu->vcpu_id; | |
843 | u32 reg; | |
844 | bool updated = false; | |
845 | ||
846 | reg = mmio_data_read(mmio, ~0); | |
847 | ||
848 | /* Clear pending SGIs on the distributor */ | |
849 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
850 | u8 mask = reg >> (8 * (sgi - min_sgi)); | |
c1bfb577 | 851 | u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi); |
90a5355e | 852 | if (set) { |
c1bfb577 | 853 | if ((*src & mask) != mask) |
90a5355e | 854 | updated = true; |
c1bfb577 | 855 | *src |= mask; |
90a5355e | 856 | } else { |
c1bfb577 | 857 | if (*src & mask) |
90a5355e | 858 | updated = true; |
c1bfb577 | 859 | *src &= ~mask; |
90a5355e CD |
860 | } |
861 | } | |
862 | ||
863 | if (updated) | |
864 | vgic_update_state(vcpu->kvm); | |
865 | ||
866 | return updated; | |
867 | } | |
868 | ||
c07a0191 CD |
869 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
870 | struct kvm_exit_mmio *mmio, | |
871 | phys_addr_t offset) | |
872 | { | |
90a5355e CD |
873 | if (!mmio->is_write) |
874 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
875 | else | |
876 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); | |
877 | } | |
878 | ||
879 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, | |
880 | struct kvm_exit_mmio *mmio, | |
881 | phys_addr_t offset) | |
882 | { | |
883 | if (!mmio->is_write) | |
884 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
885 | else | |
886 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); | |
c07a0191 CD |
887 | } |
888 | ||
1a89dd91 MZ |
889 | /* |
890 | * I would have liked to use the kvm_bus_io_*() API instead, but it | |
891 | * cannot cope with banked registers (only the VM pointer is passed | |
892 | * around, and we need the vcpu). One of these days, someone please | |
893 | * fix it! | |
894 | */ | |
895 | struct mmio_range { | |
896 | phys_addr_t base; | |
897 | unsigned long len; | |
898 | bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, | |
899 | phys_addr_t offset); | |
900 | }; | |
901 | ||
1006e8cb | 902 | static const struct mmio_range vgic_dist_ranges[] = { |
b47ef92a MZ |
903 | { |
904 | .base = GIC_DIST_CTRL, | |
905 | .len = 12, | |
906 | .handle_mmio = handle_mmio_misc, | |
907 | }, | |
908 | { | |
909 | .base = GIC_DIST_IGROUP, | |
910 | .len = VGIC_NR_IRQS / 8, | |
911 | .handle_mmio = handle_mmio_raz_wi, | |
912 | }, | |
913 | { | |
914 | .base = GIC_DIST_ENABLE_SET, | |
915 | .len = VGIC_NR_IRQS / 8, | |
916 | .handle_mmio = handle_mmio_set_enable_reg, | |
917 | }, | |
918 | { | |
919 | .base = GIC_DIST_ENABLE_CLEAR, | |
920 | .len = VGIC_NR_IRQS / 8, | |
921 | .handle_mmio = handle_mmio_clear_enable_reg, | |
922 | }, | |
923 | { | |
924 | .base = GIC_DIST_PENDING_SET, | |
925 | .len = VGIC_NR_IRQS / 8, | |
926 | .handle_mmio = handle_mmio_set_pending_reg, | |
927 | }, | |
928 | { | |
929 | .base = GIC_DIST_PENDING_CLEAR, | |
930 | .len = VGIC_NR_IRQS / 8, | |
931 | .handle_mmio = handle_mmio_clear_pending_reg, | |
932 | }, | |
933 | { | |
934 | .base = GIC_DIST_ACTIVE_SET, | |
935 | .len = VGIC_NR_IRQS / 8, | |
936 | .handle_mmio = handle_mmio_raz_wi, | |
937 | }, | |
938 | { | |
939 | .base = GIC_DIST_ACTIVE_CLEAR, | |
940 | .len = VGIC_NR_IRQS / 8, | |
941 | .handle_mmio = handle_mmio_raz_wi, | |
942 | }, | |
943 | { | |
944 | .base = GIC_DIST_PRI, | |
945 | .len = VGIC_NR_IRQS, | |
946 | .handle_mmio = handle_mmio_priority_reg, | |
947 | }, | |
948 | { | |
949 | .base = GIC_DIST_TARGET, | |
950 | .len = VGIC_NR_IRQS, | |
951 | .handle_mmio = handle_mmio_target_reg, | |
952 | }, | |
953 | { | |
954 | .base = GIC_DIST_CONFIG, | |
955 | .len = VGIC_NR_IRQS / 4, | |
956 | .handle_mmio = handle_mmio_cfg_reg, | |
957 | }, | |
958 | { | |
959 | .base = GIC_DIST_SOFTINT, | |
960 | .len = 4, | |
961 | .handle_mmio = handle_mmio_sgi_reg, | |
962 | }, | |
c07a0191 CD |
963 | { |
964 | .base = GIC_DIST_SGI_PENDING_CLEAR, | |
965 | .len = VGIC_NR_SGIS, | |
966 | .handle_mmio = handle_mmio_sgi_clear, | |
967 | }, | |
968 | { | |
969 | .base = GIC_DIST_SGI_PENDING_SET, | |
970 | .len = VGIC_NR_SGIS, | |
971 | .handle_mmio = handle_mmio_sgi_set, | |
972 | }, | |
1a89dd91 MZ |
973 | {} |
974 | }; | |
975 | ||
976 | static const | |
977 | struct mmio_range *find_matching_range(const struct mmio_range *ranges, | |
978 | struct kvm_exit_mmio *mmio, | |
1006e8cb | 979 | phys_addr_t offset) |
1a89dd91 MZ |
980 | { |
981 | const struct mmio_range *r = ranges; | |
1a89dd91 MZ |
982 | |
983 | while (r->len) { | |
1006e8cb CD |
984 | if (offset >= r->base && |
985 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
986 | return r; |
987 | r++; | |
988 | } | |
989 | ||
990 | return NULL; | |
991 | } | |
992 | ||
993 | /** | |
994 | * vgic_handle_mmio - handle an in-kernel MMIO access | |
995 | * @vcpu: pointer to the vcpu performing the access | |
996 | * @run: pointer to the kvm_run structure | |
997 | * @mmio: pointer to the data describing the access | |
998 | * | |
999 | * returns true if the MMIO access has been performed in kernel space, | |
1000 | * and false if it needs to be emulated in user space. | |
1001 | */ | |
1002 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
1003 | struct kvm_exit_mmio *mmio) | |
1004 | { | |
b47ef92a MZ |
1005 | const struct mmio_range *range; |
1006 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1007 | unsigned long base = dist->vgic_dist_base; | |
1008 | bool updated_state; | |
1009 | unsigned long offset; | |
1010 | ||
1011 | if (!irqchip_in_kernel(vcpu->kvm) || | |
1012 | mmio->phys_addr < base || | |
1013 | (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE)) | |
1014 | return false; | |
1015 | ||
1016 | /* We don't support ldrd / strd or ldm / stm to the emulated vgic */ | |
1017 | if (mmio->len > 4) { | |
1018 | kvm_inject_dabt(vcpu, mmio->phys_addr); | |
1019 | return true; | |
1020 | } | |
1021 | ||
1006e8cb CD |
1022 | offset = mmio->phys_addr - base; |
1023 | range = find_matching_range(vgic_dist_ranges, mmio, offset); | |
b47ef92a MZ |
1024 | if (unlikely(!range || !range->handle_mmio)) { |
1025 | pr_warn("Unhandled access %d %08llx %d\n", | |
1026 | mmio->is_write, mmio->phys_addr, mmio->len); | |
1027 | return false; | |
1028 | } | |
1029 | ||
1030 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
1031 | offset = mmio->phys_addr - range->base - base; | |
1032 | updated_state = range->handle_mmio(vcpu, mmio, offset); | |
1033 | spin_unlock(&vcpu->kvm->arch.vgic.lock); | |
1034 | kvm_prepare_mmio(run, mmio); | |
1035 | kvm_handle_mmio_return(vcpu, run); | |
1036 | ||
5863c2ce MZ |
1037 | if (updated_state) |
1038 | vgic_kick_vcpus(vcpu->kvm); | |
1039 | ||
b47ef92a MZ |
1040 | return true; |
1041 | } | |
1042 | ||
c1bfb577 MZ |
1043 | static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi) |
1044 | { | |
1045 | return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi; | |
1046 | } | |
1047 | ||
b47ef92a MZ |
1048 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) |
1049 | { | |
1050 | struct kvm *kvm = vcpu->kvm; | |
1051 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1052 | int nrcpus = atomic_read(&kvm->online_vcpus); | |
1053 | u8 target_cpus; | |
1054 | int sgi, mode, c, vcpu_id; | |
1055 | ||
1056 | vcpu_id = vcpu->vcpu_id; | |
1057 | ||
1058 | sgi = reg & 0xf; | |
1059 | target_cpus = (reg >> 16) & 0xff; | |
1060 | mode = (reg >> 24) & 3; | |
1061 | ||
1062 | switch (mode) { | |
1063 | case 0: | |
1064 | if (!target_cpus) | |
1065 | return; | |
91021a6c | 1066 | break; |
b47ef92a MZ |
1067 | |
1068 | case 1: | |
1069 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; | |
1070 | break; | |
1071 | ||
1072 | case 2: | |
1073 | target_cpus = 1 << vcpu_id; | |
1074 | break; | |
1075 | } | |
1076 | ||
1077 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1078 | if (target_cpus & 1) { | |
1079 | /* Flag the SGI as pending */ | |
227844f5 | 1080 | vgic_dist_irq_set_pending(vcpu, sgi); |
c1bfb577 | 1081 | *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id; |
b47ef92a MZ |
1082 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); |
1083 | } | |
1084 | ||
1085 | target_cpus >>= 1; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) | |
1090 | { | |
9d949dce MZ |
1091 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1092 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
1093 | unsigned long pending_private, pending_shared; | |
1094 | int vcpu_id; | |
1095 | ||
1096 | vcpu_id = vcpu->vcpu_id; | |
1097 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
1098 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
1099 | ||
227844f5 | 1100 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
1101 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
1102 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
1103 | ||
227844f5 | 1104 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce MZ |
1105 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
1106 | bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS); | |
1107 | bitmap_and(pend_shared, pend_shared, | |
1108 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
1109 | VGIC_NR_SHARED_IRQS); | |
1110 | ||
1111 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
1112 | pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS); | |
1113 | return (pending_private < VGIC_NR_PRIVATE_IRQS || | |
1114 | pending_shared < VGIC_NR_SHARED_IRQS); | |
b47ef92a MZ |
1115 | } |
1116 | ||
1117 | /* | |
1118 | * Update the interrupt state and determine which CPUs have pending | |
1119 | * interrupts. Must be called with distributor lock held. | |
1120 | */ | |
1121 | static void vgic_update_state(struct kvm *kvm) | |
1122 | { | |
1123 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1124 | struct kvm_vcpu *vcpu; | |
1125 | int c; | |
1126 | ||
1127 | if (!dist->enabled) { | |
c1bfb577 | 1128 | set_bit(0, dist->irq_pending_on_cpu); |
b47ef92a MZ |
1129 | return; |
1130 | } | |
1131 | ||
1132 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1133 | if (compute_pending_for_cpu(vcpu)) { | |
1134 | pr_debug("CPU%d has pending interrupts\n", c); | |
c1bfb577 | 1135 | set_bit(c, dist->irq_pending_on_cpu); |
b47ef92a MZ |
1136 | } |
1137 | } | |
1a89dd91 | 1138 | } |
330690cd | 1139 | |
8d5c6b06 MZ |
1140 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
1141 | { | |
8f186d52 | 1142 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
1143 | } |
1144 | ||
1145 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
1146 | struct vgic_lr vlr) | |
1147 | { | |
8f186d52 | 1148 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
1149 | } |
1150 | ||
69bb2c9f MZ |
1151 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
1152 | struct vgic_lr vlr) | |
1153 | { | |
8f186d52 | 1154 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
1155 | } |
1156 | ||
1157 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
1158 | { | |
8f186d52 | 1159 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
1160 | } |
1161 | ||
8d6a0313 MZ |
1162 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
1163 | { | |
8f186d52 | 1164 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1165 | } |
1166 | ||
495dd859 MZ |
1167 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1168 | { | |
8f186d52 | 1169 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1170 | } |
1171 | ||
909d9b50 MZ |
1172 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1173 | { | |
8f186d52 | 1174 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1175 | } |
1176 | ||
1177 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1178 | { | |
8f186d52 | 1179 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1180 | } |
1181 | ||
beee38b9 MZ |
1182 | static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
1183 | { | |
8f186d52 | 1184 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1185 | } |
1186 | ||
1187 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) | |
1188 | { | |
8f186d52 | 1189 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1190 | } |
1191 | ||
da8dafd1 MZ |
1192 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1193 | { | |
8f186d52 | 1194 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1195 | } |
1196 | ||
8d5c6b06 MZ |
1197 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1198 | { | |
1199 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1200 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1201 | ||
1202 | vlr.state = 0; | |
1203 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1204 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1205 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1206 | } | |
a1fcb44e MZ |
1207 | |
1208 | /* | |
1209 | * An interrupt may have been disabled after being made pending on the | |
1210 | * CPU interface (the classic case is a timer running while we're | |
1211 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1212 | * interface gets enabled, with deadly consequences). | |
1213 | * | |
1214 | * The solution is to examine already active LRs, and check the | |
1215 | * interrupt is still enabled. If not, just retire it. | |
1216 | */ | |
1217 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1218 | { | |
1219 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1220 | int lr; | |
1221 | ||
8f186d52 | 1222 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1223 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1224 | |
8d5c6b06 MZ |
1225 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1226 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1227 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1228 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1229 | } |
1230 | } | |
1231 | } | |
1232 | ||
9d949dce MZ |
1233 | /* |
1234 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1235 | * or false if it wasn't possible to queue it. | |
1236 | */ | |
1237 | static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |
1238 | { | |
1239 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
8d5c6b06 | 1240 | struct vgic_lr vlr; |
9d949dce MZ |
1241 | int lr; |
1242 | ||
1243 | /* Sanitize the input... */ | |
1244 | BUG_ON(sgi_source_id & ~7); | |
1245 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
1246 | BUG_ON(irq >= VGIC_NR_IRQS); | |
1247 | ||
1248 | kvm_debug("Queue IRQ%d\n", irq); | |
1249 | ||
1250 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1251 | ||
1252 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1253 | if (lr != LR_EMPTY) { |
1254 | vlr = vgic_get_lr(vcpu, lr); | |
1255 | if (vlr.source == sgi_source_id) { | |
1256 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1257 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
1258 | vlr.state |= LR_STATE_PENDING; | |
1259 | vgic_set_lr(vcpu, lr, vlr); | |
1260 | return true; | |
1261 | } | |
9d949dce MZ |
1262 | } |
1263 | ||
1264 | /* Try to use another LR for this interrupt */ | |
1265 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1266 | vgic->nr_lr); |
1267 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1268 | return false; |
1269 | ||
1270 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1271 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1272 | set_bit(lr, vgic_cpu->lr_used); | |
1273 | ||
8d5c6b06 MZ |
1274 | vlr.irq = irq; |
1275 | vlr.source = sgi_source_id; | |
1276 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 1277 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
1278 | vlr.state |= LR_EOI_INT; |
1279 | ||
1280 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1281 | |
1282 | return true; | |
1283 | } | |
1284 | ||
1285 | static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
1286 | { | |
1287 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1288 | unsigned long sources; | |
1289 | int vcpu_id = vcpu->vcpu_id; | |
1290 | int c; | |
1291 | ||
c1bfb577 | 1292 | sources = *vgic_get_sgi_sources(dist, vcpu_id, irq); |
9d949dce MZ |
1293 | |
1294 | for_each_set_bit(c, &sources, VGIC_MAX_CPUS) { | |
1295 | if (vgic_queue_irq(vcpu, c, irq)) | |
1296 | clear_bit(c, &sources); | |
1297 | } | |
1298 | ||
c1bfb577 | 1299 | *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources; |
9d949dce MZ |
1300 | |
1301 | /* | |
1302 | * If the sources bitmap has been cleared it means that we | |
1303 | * could queue all the SGIs onto link registers (see the | |
1304 | * clear_bit above), and therefore we are done with them in | |
1305 | * our emulated gic and can get rid of them. | |
1306 | */ | |
1307 | if (!sources) { | |
227844f5 | 1308 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1309 | vgic_cpu_irq_clear(vcpu, irq); |
1310 | return true; | |
1311 | } | |
1312 | ||
1313 | return false; | |
1314 | } | |
1315 | ||
1316 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) | |
1317 | { | |
dbf20f9d | 1318 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1319 | return true; /* level interrupt, already queued */ |
1320 | ||
1321 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1322 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1323 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1324 | vgic_cpu_irq_clear(vcpu, irq); |
1325 | } else { | |
dbf20f9d | 1326 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1327 | } |
1328 | ||
1329 | return true; | |
1330 | } | |
1331 | ||
1332 | return false; | |
1333 | } | |
1334 | ||
1335 | /* | |
1336 | * Fill the list registers with pending interrupts before running the | |
1337 | * guest. | |
1338 | */ | |
1339 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1340 | { | |
1341 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1342 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1343 | int i, vcpu_id; | |
1344 | int overflow = 0; | |
1345 | ||
1346 | vcpu_id = vcpu->vcpu_id; | |
1347 | ||
1348 | /* | |
1349 | * We may not have any pending interrupt, or the interrupts | |
1350 | * may have been serviced from another vcpu. In all cases, | |
1351 | * move along. | |
1352 | */ | |
1353 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1354 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1355 | goto epilog; | |
1356 | } | |
1357 | ||
1358 | /* SGIs */ | |
1359 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
1360 | if (!vgic_queue_sgi(vcpu, i)) | |
1361 | overflow = 1; | |
1362 | } | |
1363 | ||
1364 | /* PPIs */ | |
1365 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1366 | if (!vgic_queue_hwirq(vcpu, i)) | |
1367 | overflow = 1; | |
1368 | } | |
1369 | ||
1370 | /* SPIs */ | |
1371 | for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) { | |
1372 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) | |
1373 | overflow = 1; | |
1374 | } | |
1375 | ||
1376 | epilog: | |
1377 | if (overflow) { | |
909d9b50 | 1378 | vgic_enable_underflow(vcpu); |
9d949dce | 1379 | } else { |
909d9b50 | 1380 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1381 | /* |
1382 | * We're about to run this VCPU, and we've consumed | |
1383 | * everything the distributor had in store for | |
1384 | * us. Claim we don't have anything pending. We'll | |
1385 | * adjust that if needed while exiting. | |
1386 | */ | |
c1bfb577 | 1387 | clear_bit(vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1388 | } |
1389 | } | |
1390 | ||
1391 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1392 | { | |
495dd859 | 1393 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1394 | bool level_pending = false; |
1395 | ||
495dd859 | 1396 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1397 | |
495dd859 | 1398 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1399 | /* |
1400 | * Some level interrupts have been EOIed. Clear their | |
1401 | * active bit. | |
1402 | */ | |
8d6a0313 MZ |
1403 | u64 eisr = vgic_get_eisr(vcpu); |
1404 | unsigned long *eisr_ptr = (unsigned long *)&eisr; | |
8d5c6b06 | 1405 | int lr; |
9d949dce | 1406 | |
8f186d52 | 1407 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1408 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
faa1b46c | 1409 | WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq)); |
9d949dce | 1410 | |
dbf20f9d | 1411 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1412 | WARN_ON(vlr.state & LR_STATE_MASK); |
1413 | vlr.state = 0; | |
1414 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce | 1415 | |
faa1b46c CD |
1416 | /* |
1417 | * If the IRQ was EOIed it was also ACKed and we we | |
1418 | * therefore assume we can clear the soft pending | |
1419 | * state (should it had been set) for this interrupt. | |
1420 | * | |
1421 | * Note: if the IRQ soft pending state was set after | |
1422 | * the IRQ was acked, it actually shouldn't be | |
1423 | * cleared, but we have no way of knowing that unless | |
1424 | * we start trapping ACKs when the soft-pending state | |
1425 | * is set. | |
1426 | */ | |
1427 | vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq); | |
1428 | ||
9d949dce | 1429 | /* Any additional pending interrupt? */ |
faa1b46c | 1430 | if (vgic_dist_irq_get_level(vcpu, vlr.irq)) { |
8d5c6b06 | 1431 | vgic_cpu_irq_set(vcpu, vlr.irq); |
9d949dce MZ |
1432 | level_pending = true; |
1433 | } else { | |
faa1b46c | 1434 | vgic_dist_irq_clear_pending(vcpu, vlr.irq); |
8d5c6b06 | 1435 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1436 | } |
75da01e1 MZ |
1437 | |
1438 | /* | |
1439 | * Despite being EOIed, the LR may not have | |
1440 | * been marked as empty. | |
1441 | */ | |
69bb2c9f | 1442 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1443 | } |
1444 | } | |
1445 | ||
495dd859 | 1446 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1447 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1448 | |
1449 | return level_pending; | |
1450 | } | |
1451 | ||
1452 | /* | |
33c83cb3 MZ |
1453 | * Sync back the VGIC state after a guest run. The distributor lock is |
1454 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1455 | */ |
1456 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1457 | { | |
1458 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1459 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1460 | u64 elrsr; |
1461 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1462 | int lr, pending; |
1463 | bool level_pending; | |
1464 | ||
1465 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f MZ |
1466 | elrsr = vgic_get_elrsr(vcpu); |
1467 | elrsr_ptr = (unsigned long *)&elrsr; | |
9d949dce MZ |
1468 | |
1469 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1470 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1471 | struct vgic_lr vlr; |
9d949dce MZ |
1472 | |
1473 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1474 | continue; | |
1475 | ||
8d5c6b06 | 1476 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1477 | |
8d5c6b06 MZ |
1478 | BUG_ON(vlr.irq >= VGIC_NR_IRQS); |
1479 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; | |
9d949dce MZ |
1480 | } |
1481 | ||
1482 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1483 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1484 | if (level_pending || pending < vgic->nr_lr) | |
c1bfb577 | 1485 | set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1486 | } |
1487 | ||
1488 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1489 | { | |
1490 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1491 | ||
1492 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1493 | return; | |
1494 | ||
1495 | spin_lock(&dist->lock); | |
1496 | __kvm_vgic_flush_hwstate(vcpu); | |
1497 | spin_unlock(&dist->lock); | |
1498 | } | |
1499 | ||
1500 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1501 | { | |
33c83cb3 MZ |
1502 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1503 | ||
9d949dce MZ |
1504 | if (!irqchip_in_kernel(vcpu->kvm)) |
1505 | return; | |
1506 | ||
33c83cb3 | 1507 | spin_lock(&dist->lock); |
9d949dce | 1508 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1509 | spin_unlock(&dist->lock); |
9d949dce MZ |
1510 | } |
1511 | ||
1512 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1513 | { | |
1514 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1515 | ||
1516 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1517 | return 0; | |
1518 | ||
c1bfb577 | 1519 | return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); |
9d949dce MZ |
1520 | } |
1521 | ||
5863c2ce MZ |
1522 | static void vgic_kick_vcpus(struct kvm *kvm) |
1523 | { | |
1524 | struct kvm_vcpu *vcpu; | |
1525 | int c; | |
1526 | ||
1527 | /* | |
1528 | * We've injected an interrupt, time to find out who deserves | |
1529 | * a good kick... | |
1530 | */ | |
1531 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1532 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1533 | kvm_vcpu_kick(vcpu); | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1538 | { | |
227844f5 | 1539 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1540 | |
1541 | /* | |
1542 | * Only inject an interrupt if: | |
1543 | * - edge triggered and we have a rising edge | |
1544 | * - level triggered and we change level | |
1545 | */ | |
faa1b46c CD |
1546 | if (edge_triggered) { |
1547 | int state = vgic_dist_irq_is_pending(vcpu, irq); | |
5863c2ce | 1548 | return level > state; |
faa1b46c CD |
1549 | } else { |
1550 | int state = vgic_dist_irq_get_level(vcpu, irq); | |
5863c2ce | 1551 | return level != state; |
faa1b46c | 1552 | } |
5863c2ce MZ |
1553 | } |
1554 | ||
227844f5 | 1555 | static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1556 | unsigned int irq_num, bool level) |
1557 | { | |
1558 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1559 | struct kvm_vcpu *vcpu; | |
227844f5 | 1560 | int edge_triggered, level_triggered; |
5863c2ce MZ |
1561 | int enabled; |
1562 | bool ret = true; | |
1563 | ||
1564 | spin_lock(&dist->lock); | |
1565 | ||
1566 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1567 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1568 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1569 | |
1570 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1571 | ret = false; | |
1572 | goto out; | |
1573 | } | |
1574 | ||
1575 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1576 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
1577 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1578 | } | |
1579 | ||
1580 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1581 | ||
faa1b46c CD |
1582 | if (level) { |
1583 | if (level_triggered) | |
1584 | vgic_dist_irq_set_level(vcpu, irq_num); | |
227844f5 | 1585 | vgic_dist_irq_set_pending(vcpu, irq_num); |
faa1b46c CD |
1586 | } else { |
1587 | if (level_triggered) { | |
1588 | vgic_dist_irq_clear_level(vcpu, irq_num); | |
1589 | if (!vgic_dist_irq_soft_pend(vcpu, irq_num)) | |
1590 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
1591 | } else { | |
1592 | vgic_dist_irq_clear_pending(vcpu, irq_num); | |
1593 | } | |
1594 | } | |
5863c2ce MZ |
1595 | |
1596 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1597 | ||
1598 | if (!enabled) { | |
1599 | ret = false; | |
1600 | goto out; | |
1601 | } | |
1602 | ||
dbf20f9d | 1603 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1604 | /* |
1605 | * Level interrupt in progress, will be picked up | |
1606 | * when EOId. | |
1607 | */ | |
1608 | ret = false; | |
1609 | goto out; | |
1610 | } | |
1611 | ||
1612 | if (level) { | |
1613 | vgic_cpu_irq_set(vcpu, irq_num); | |
c1bfb577 | 1614 | set_bit(cpuid, dist->irq_pending_on_cpu); |
5863c2ce MZ |
1615 | } |
1616 | ||
1617 | out: | |
1618 | spin_unlock(&dist->lock); | |
1619 | ||
1620 | return ret; | |
1621 | } | |
1622 | ||
1623 | /** | |
1624 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1625 | * @kvm: The VM structure pointer | |
1626 | * @cpuid: The CPU for PPIs | |
1627 | * @irq_num: The IRQ number that is assigned to the device | |
1628 | * @level: Edge-triggered: true: to trigger the interrupt | |
1629 | * false: to ignore the call | |
1630 | * Level-sensitive true: activates an interrupt | |
1631 | * false: deactivates an interrupt | |
1632 | * | |
1633 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1634 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1635 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1636 | */ | |
1637 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1638 | bool level) | |
1639 | { | |
71afaba4 MZ |
1640 | if (likely(vgic_initialized(kvm)) && |
1641 | vgic_update_irq_pending(kvm, cpuid, irq_num, level)) | |
5863c2ce MZ |
1642 | vgic_kick_vcpus(kvm); |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | ||
01ac5e34 MZ |
1647 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1648 | { | |
1649 | /* | |
1650 | * We cannot rely on the vgic maintenance interrupt to be | |
1651 | * delivered synchronously. This means we can only use it to | |
1652 | * exit the VM, and we perform the handling of EOIed | |
1653 | * interrupts on the exit path (see vgic_process_maintenance). | |
1654 | */ | |
1655 | return IRQ_HANDLED; | |
1656 | } | |
1657 | ||
c1bfb577 MZ |
1658 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) |
1659 | { | |
1660 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1661 | ||
1662 | kfree(vgic_cpu->pending_shared); | |
1663 | kfree(vgic_cpu->vgic_irq_lr_map); | |
1664 | vgic_cpu->pending_shared = NULL; | |
1665 | vgic_cpu->vgic_irq_lr_map = NULL; | |
1666 | } | |
1667 | ||
1668 | static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) | |
1669 | { | |
1670 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1671 | ||
1672 | int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8; | |
1673 | vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); | |
1674 | vgic_cpu->vgic_irq_lr_map = kzalloc(nr_irqs, GFP_KERNEL); | |
1675 | ||
1676 | if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) { | |
1677 | kvm_vgic_vcpu_destroy(vcpu); | |
1678 | return -ENOMEM; | |
1679 | } | |
1680 | ||
1681 | return 0; | |
1682 | } | |
1683 | ||
e1ba0207 CD |
1684 | /** |
1685 | * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state | |
1686 | * @vcpu: pointer to the vcpu struct | |
1687 | * | |
1688 | * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to | |
1689 | * this vcpu and enable the VGIC for this VCPU | |
1690 | */ | |
01ac5e34 MZ |
1691 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) |
1692 | { | |
1693 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1694 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1695 | int i; | |
1696 | ||
01ac5e34 MZ |
1697 | if (vcpu->vcpu_id >= VGIC_MAX_CPUS) |
1698 | return -EBUSY; | |
1699 | ||
1700 | for (i = 0; i < VGIC_NR_IRQS; i++) { | |
1701 | if (i < VGIC_NR_PPIS) | |
1702 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1703 | vcpu->vcpu_id, i, 1); | |
1704 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1705 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1706 | vcpu->vcpu_id, i, VGIC_CFG_EDGE); | |
1707 | ||
1708 | vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY; | |
1709 | } | |
1710 | ||
1711 | /* | |
ca85f623 MZ |
1712 | * Store the number of LRs per vcpu, so we don't have to go |
1713 | * all the way to the distributor structure to find out. Only | |
1714 | * assembly code should use this one. | |
01ac5e34 | 1715 | */ |
8f186d52 | 1716 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1717 | |
da8dafd1 | 1718 | vgic_enable(vcpu); |
01ac5e34 MZ |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | ||
c1bfb577 MZ |
1723 | void kvm_vgic_destroy(struct kvm *kvm) |
1724 | { | |
1725 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1726 | struct kvm_vcpu *vcpu; | |
1727 | int i; | |
1728 | ||
1729 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1730 | kvm_vgic_vcpu_destroy(vcpu); | |
1731 | ||
1732 | vgic_free_bitmap(&dist->irq_enabled); | |
1733 | vgic_free_bitmap(&dist->irq_level); | |
1734 | vgic_free_bitmap(&dist->irq_pending); | |
1735 | vgic_free_bitmap(&dist->irq_soft_pend); | |
1736 | vgic_free_bitmap(&dist->irq_queued); | |
1737 | vgic_free_bitmap(&dist->irq_cfg); | |
1738 | vgic_free_bytemap(&dist->irq_priority); | |
1739 | if (dist->irq_spi_target) { | |
1740 | for (i = 0; i < dist->nr_cpus; i++) | |
1741 | vgic_free_bitmap(&dist->irq_spi_target[i]); | |
1742 | } | |
1743 | kfree(dist->irq_sgi_sources); | |
1744 | kfree(dist->irq_spi_cpu); | |
1745 | kfree(dist->irq_spi_target); | |
1746 | kfree(dist->irq_pending_on_cpu); | |
1747 | dist->irq_sgi_sources = NULL; | |
1748 | dist->irq_spi_cpu = NULL; | |
1749 | dist->irq_spi_target = NULL; | |
1750 | dist->irq_pending_on_cpu = NULL; | |
1751 | } | |
1752 | ||
1753 | /* | |
1754 | * Allocate and initialize the various data structures. Must be called | |
1755 | * with kvm->lock held! | |
1756 | */ | |
1757 | static int vgic_init_maps(struct kvm *kvm) | |
1758 | { | |
1759 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1760 | struct kvm_vcpu *vcpu; | |
1761 | int nr_cpus, nr_irqs; | |
1762 | int ret, i; | |
1763 | ||
1764 | nr_cpus = dist->nr_cpus = VGIC_MAX_CPUS; | |
1765 | nr_irqs = dist->nr_irqs = VGIC_NR_IRQS; | |
1766 | ||
1767 | ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs); | |
1768 | ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs); | |
1769 | ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs); | |
1770 | ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs); | |
1771 | ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs); | |
1772 | ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs); | |
1773 | ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs); | |
1774 | ||
1775 | if (ret) | |
1776 | goto out; | |
1777 | ||
1778 | dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL); | |
1779 | dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL); | |
1780 | dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus, | |
1781 | GFP_KERNEL); | |
1782 | dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long), | |
1783 | GFP_KERNEL); | |
1784 | if (!dist->irq_sgi_sources || | |
1785 | !dist->irq_spi_cpu || | |
1786 | !dist->irq_spi_target || | |
1787 | !dist->irq_pending_on_cpu) { | |
1788 | ret = -ENOMEM; | |
1789 | goto out; | |
1790 | } | |
1791 | ||
1792 | for (i = 0; i < nr_cpus; i++) | |
1793 | ret |= vgic_init_bitmap(&dist->irq_spi_target[i], | |
1794 | nr_cpus, nr_irqs); | |
1795 | ||
1796 | if (ret) | |
1797 | goto out; | |
1798 | ||
1799 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1800 | ret = vgic_vcpu_init_maps(vcpu, nr_irqs); | |
1801 | if (ret) { | |
1802 | kvm_err("VGIC: Failed to allocate vcpu memory\n"); | |
1803 | break; | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | out: | |
1808 | if (ret) | |
1809 | kvm_vgic_destroy(kvm); | |
1810 | ||
1811 | return ret; | |
1812 | } | |
1813 | ||
e1ba0207 CD |
1814 | /** |
1815 | * kvm_vgic_init - Initialize global VGIC state before running any VCPUs | |
1816 | * @kvm: pointer to the kvm struct | |
1817 | * | |
1818 | * Map the virtual CPU interface into the VM before running any VCPUs. We | |
1819 | * can't do this at creation time, because user space must first set the | |
1820 | * virtual CPU interface address in the guest physical address space. Also | |
1821 | * initialize the ITARGETSRn regs to 0 on the emulated distributor. | |
1822 | */ | |
01ac5e34 MZ |
1823 | int kvm_vgic_init(struct kvm *kvm) |
1824 | { | |
1825 | int ret = 0, i; | |
1826 | ||
e1ba0207 CD |
1827 | if (!irqchip_in_kernel(kvm)) |
1828 | return 0; | |
1829 | ||
01ac5e34 MZ |
1830 | mutex_lock(&kvm->lock); |
1831 | ||
1832 | if (vgic_initialized(kvm)) | |
1833 | goto out; | |
1834 | ||
1835 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || | |
1836 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { | |
1837 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
1838 | ret = -ENXIO; | |
1839 | goto out; | |
1840 | } | |
1841 | ||
1842 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, | |
8f186d52 | 1843 | vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE); |
01ac5e34 MZ |
1844 | if (ret) { |
1845 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
1846 | goto out; | |
1847 | } | |
1848 | ||
1849 | for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4) | |
1850 | vgic_set_target_reg(kvm, 0, i); | |
1851 | ||
1852 | kvm->arch.vgic.ready = true; | |
1853 | out: | |
1854 | mutex_unlock(&kvm->lock); | |
1855 | return ret; | |
1856 | } | |
1857 | ||
1858 | int kvm_vgic_create(struct kvm *kvm) | |
1859 | { | |
7330672b CD |
1860 | int i, vcpu_lock_idx = -1, ret = 0; |
1861 | struct kvm_vcpu *vcpu; | |
01ac5e34 MZ |
1862 | |
1863 | mutex_lock(&kvm->lock); | |
1864 | ||
7330672b | 1865 | if (kvm->arch.vgic.vctrl_base) { |
01ac5e34 MZ |
1866 | ret = -EEXIST; |
1867 | goto out; | |
1868 | } | |
1869 | ||
7330672b CD |
1870 | /* |
1871 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1872 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1873 | * that no other VCPUs are run while we create the vgic. | |
1874 | */ | |
1875 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1876 | if (!mutex_trylock(&vcpu->mutex)) | |
1877 | goto out_unlock; | |
1878 | vcpu_lock_idx = i; | |
1879 | } | |
1880 | ||
1881 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1882 | if (vcpu->arch.has_run_once) { | |
1883 | ret = -EBUSY; | |
1884 | goto out_unlock; | |
1885 | } | |
1886 | } | |
1887 | ||
01ac5e34 | 1888 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1889 | kvm->arch.vgic.in_kernel = true; |
8f186d52 | 1890 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1891 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1892 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
1893 | ||
c1bfb577 MZ |
1894 | ret = vgic_init_maps(kvm); |
1895 | if (ret) | |
1896 | kvm_err("Unable to allocate maps\n"); | |
1897 | ||
7330672b CD |
1898 | out_unlock: |
1899 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1900 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1901 | mutex_unlock(&vcpu->mutex); | |
1902 | } | |
1903 | ||
01ac5e34 MZ |
1904 | out: |
1905 | mutex_unlock(&kvm->lock); | |
1906 | return ret; | |
1907 | } | |
1908 | ||
1fa451bc | 1909 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
1910 | { |
1911 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1912 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1913 | ||
1914 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1915 | return 0; | |
1916 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1917 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1918 | return -EBUSY; | |
1919 | return 0; | |
1920 | } | |
1921 | ||
1922 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1923 | phys_addr_t addr, phys_addr_t size) | |
1924 | { | |
1925 | int ret; | |
1926 | ||
ce01e4e8 CD |
1927 | if (addr & ~KVM_PHYS_MASK) |
1928 | return -E2BIG; | |
1929 | ||
1930 | if (addr & (SZ_4K - 1)) | |
1931 | return -EINVAL; | |
1932 | ||
330690cd CD |
1933 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1934 | return -EEXIST; | |
1935 | if (addr + size < addr) | |
1936 | return -EINVAL; | |
1937 | ||
30c21170 | 1938 | *ioaddr = addr; |
330690cd CD |
1939 | ret = vgic_ioaddr_overlap(kvm); |
1940 | if (ret) | |
30c21170 HW |
1941 | *ioaddr = VGIC_ADDR_UNDEF; |
1942 | ||
330690cd CD |
1943 | return ret; |
1944 | } | |
1945 | ||
ce01e4e8 CD |
1946 | /** |
1947 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1948 | * @kvm: pointer to the vm struct | |
1949 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX | |
1950 | * @addr: pointer to address value | |
1951 | * @write: if true set the address in the VM address space, if false read the | |
1952 | * address | |
1953 | * | |
1954 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1955 | * interface in the VM physical address space. These addresses are properties | |
1956 | * of the emulated core/SoC and therefore user space initially knows this | |
1957 | * information. | |
1958 | */ | |
1959 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1960 | { |
1961 | int r = 0; | |
1962 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
1963 | ||
330690cd CD |
1964 | mutex_lock(&kvm->lock); |
1965 | switch (type) { | |
1966 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ce01e4e8 CD |
1967 | if (write) { |
1968 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, | |
1969 | *addr, KVM_VGIC_V2_DIST_SIZE); | |
1970 | } else { | |
1971 | *addr = vgic->vgic_dist_base; | |
1972 | } | |
330690cd CD |
1973 | break; |
1974 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ce01e4e8 CD |
1975 | if (write) { |
1976 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, | |
1977 | *addr, KVM_VGIC_V2_CPU_SIZE); | |
1978 | } else { | |
1979 | *addr = vgic->vgic_cpu_base; | |
1980 | } | |
330690cd CD |
1981 | break; |
1982 | default: | |
1983 | r = -ENODEV; | |
1984 | } | |
1985 | ||
1986 | mutex_unlock(&kvm->lock); | |
1987 | return r; | |
1988 | } | |
7330672b | 1989 | |
c07a0191 CD |
1990 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
1991 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1992 | { | |
fa20f5ae | 1993 | bool updated = false; |
beee38b9 MZ |
1994 | struct vgic_vmcr vmcr; |
1995 | u32 *vmcr_field; | |
1996 | u32 reg; | |
1997 | ||
1998 | vgic_get_vmcr(vcpu, &vmcr); | |
fa20f5ae CD |
1999 | |
2000 | switch (offset & ~0x3) { | |
2001 | case GIC_CPU_CTRL: | |
beee38b9 | 2002 | vmcr_field = &vmcr.ctlr; |
fa20f5ae CD |
2003 | break; |
2004 | case GIC_CPU_PRIMASK: | |
beee38b9 | 2005 | vmcr_field = &vmcr.pmr; |
fa20f5ae CD |
2006 | break; |
2007 | case GIC_CPU_BINPOINT: | |
beee38b9 | 2008 | vmcr_field = &vmcr.bpr; |
fa20f5ae CD |
2009 | break; |
2010 | case GIC_CPU_ALIAS_BINPOINT: | |
beee38b9 | 2011 | vmcr_field = &vmcr.abpr; |
fa20f5ae | 2012 | break; |
beee38b9 MZ |
2013 | default: |
2014 | BUG(); | |
fa20f5ae CD |
2015 | } |
2016 | ||
2017 | if (!mmio->is_write) { | |
beee38b9 | 2018 | reg = *vmcr_field; |
fa20f5ae CD |
2019 | mmio_data_write(mmio, ~0, reg); |
2020 | } else { | |
2021 | reg = mmio_data_read(mmio, ~0); | |
beee38b9 MZ |
2022 | if (reg != *vmcr_field) { |
2023 | *vmcr_field = reg; | |
2024 | vgic_set_vmcr(vcpu, &vmcr); | |
fa20f5ae | 2025 | updated = true; |
beee38b9 | 2026 | } |
fa20f5ae CD |
2027 | } |
2028 | return updated; | |
2029 | } | |
2030 | ||
2031 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, | |
2032 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
2033 | { | |
2034 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); | |
c07a0191 CD |
2035 | } |
2036 | ||
fa20f5ae CD |
2037 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
2038 | struct kvm_exit_mmio *mmio, | |
2039 | phys_addr_t offset) | |
2040 | { | |
2041 | u32 reg; | |
2042 | ||
2043 | if (mmio->is_write) | |
2044 | return false; | |
2045 | ||
2046 | /* GICC_IIDR */ | |
2047 | reg = (PRODUCT_ID_KVM << 20) | | |
2048 | (GICC_ARCH_VERSION_V2 << 16) | | |
2049 | (IMPLEMENTER_ARM << 0); | |
2050 | mmio_data_write(mmio, ~0, reg); | |
2051 | return false; | |
2052 | } | |
2053 | ||
2054 | /* | |
2055 | * CPU Interface Register accesses - these are not accessed by the VM, but by | |
2056 | * user space for saving and restoring VGIC state. | |
2057 | */ | |
c07a0191 CD |
2058 | static const struct mmio_range vgic_cpu_ranges[] = { |
2059 | { | |
2060 | .base = GIC_CPU_CTRL, | |
2061 | .len = 12, | |
2062 | .handle_mmio = handle_cpu_mmio_misc, | |
2063 | }, | |
2064 | { | |
2065 | .base = GIC_CPU_ALIAS_BINPOINT, | |
2066 | .len = 4, | |
fa20f5ae | 2067 | .handle_mmio = handle_mmio_abpr, |
c07a0191 CD |
2068 | }, |
2069 | { | |
2070 | .base = GIC_CPU_ACTIVEPRIO, | |
2071 | .len = 16, | |
fa20f5ae | 2072 | .handle_mmio = handle_mmio_raz_wi, |
c07a0191 CD |
2073 | }, |
2074 | { | |
2075 | .base = GIC_CPU_IDENT, | |
2076 | .len = 4, | |
fa20f5ae | 2077 | .handle_mmio = handle_cpu_mmio_ident, |
c07a0191 CD |
2078 | }, |
2079 | }; | |
2080 | ||
2081 | static int vgic_attr_regs_access(struct kvm_device *dev, | |
2082 | struct kvm_device_attr *attr, | |
2083 | u32 *reg, bool is_write) | |
2084 | { | |
2085 | const struct mmio_range *r = NULL, *ranges; | |
2086 | phys_addr_t offset; | |
2087 | int ret, cpuid, c; | |
2088 | struct kvm_vcpu *vcpu, *tmp_vcpu; | |
2089 | struct vgic_dist *vgic; | |
2090 | struct kvm_exit_mmio mmio; | |
2091 | ||
2092 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2093 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> | |
2094 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; | |
2095 | ||
2096 | mutex_lock(&dev->kvm->lock); | |
2097 | ||
2098 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { | |
2099 | ret = -EINVAL; | |
2100 | goto out; | |
2101 | } | |
2102 | ||
2103 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); | |
2104 | vgic = &dev->kvm->arch.vgic; | |
2105 | ||
2106 | mmio.len = 4; | |
2107 | mmio.is_write = is_write; | |
2108 | if (is_write) | |
2109 | mmio_data_write(&mmio, ~0, *reg); | |
2110 | switch (attr->group) { | |
2111 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2112 | mmio.phys_addr = vgic->vgic_dist_base + offset; | |
2113 | ranges = vgic_dist_ranges; | |
2114 | break; | |
2115 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2116 | mmio.phys_addr = vgic->vgic_cpu_base + offset; | |
2117 | ranges = vgic_cpu_ranges; | |
2118 | break; | |
2119 | default: | |
2120 | BUG(); | |
2121 | } | |
2122 | r = find_matching_range(ranges, &mmio, offset); | |
2123 | ||
2124 | if (unlikely(!r || !r->handle_mmio)) { | |
2125 | ret = -ENXIO; | |
2126 | goto out; | |
2127 | } | |
2128 | ||
2129 | ||
2130 | spin_lock(&vgic->lock); | |
2131 | ||
2132 | /* | |
2133 | * Ensure that no other VCPU is running by checking the vcpu->cpu | |
2134 | * field. If no other VPCUs are running we can safely access the VGIC | |
2135 | * state, because even if another VPU is run after this point, that | |
2136 | * VCPU will not touch the vgic state, because it will block on | |
2137 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). | |
2138 | */ | |
2139 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { | |
2140 | if (unlikely(tmp_vcpu->cpu != -1)) { | |
2141 | ret = -EBUSY; | |
2142 | goto out_vgic_unlock; | |
2143 | } | |
2144 | } | |
2145 | ||
cbd333a4 CD |
2146 | /* |
2147 | * Move all pending IRQs from the LRs on all VCPUs so the pending | |
2148 | * state can be properly represented in the register state accessible | |
2149 | * through this API. | |
2150 | */ | |
2151 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) | |
2152 | vgic_unqueue_irqs(tmp_vcpu); | |
2153 | ||
c07a0191 CD |
2154 | offset -= r->base; |
2155 | r->handle_mmio(vcpu, &mmio, offset); | |
2156 | ||
2157 | if (!is_write) | |
2158 | *reg = mmio_data_read(&mmio, ~0); | |
2159 | ||
2160 | ret = 0; | |
2161 | out_vgic_unlock: | |
2162 | spin_unlock(&vgic->lock); | |
2163 | out: | |
2164 | mutex_unlock(&dev->kvm->lock); | |
2165 | return ret; | |
2166 | } | |
2167 | ||
7330672b CD |
2168 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2169 | { | |
ce01e4e8 CD |
2170 | int r; |
2171 | ||
2172 | switch (attr->group) { | |
2173 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2174 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2175 | u64 addr; | |
2176 | unsigned long type = (unsigned long)attr->attr; | |
2177 | ||
2178 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
2179 | return -EFAULT; | |
2180 | ||
2181 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
2182 | return (r == -ENODEV) ? -ENXIO : r; | |
2183 | } | |
c07a0191 CD |
2184 | |
2185 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2186 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2187 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2188 | u32 reg; | |
2189 | ||
2190 | if (get_user(reg, uaddr)) | |
2191 | return -EFAULT; | |
2192 | ||
2193 | return vgic_attr_regs_access(dev, attr, ®, true); | |
2194 | } | |
2195 | ||
ce01e4e8 CD |
2196 | } |
2197 | ||
7330672b CD |
2198 | return -ENXIO; |
2199 | } | |
2200 | ||
2201 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
2202 | { | |
ce01e4e8 CD |
2203 | int r = -ENXIO; |
2204 | ||
2205 | switch (attr->group) { | |
2206 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
2207 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
2208 | u64 addr; | |
2209 | unsigned long type = (unsigned long)attr->attr; | |
2210 | ||
2211 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
2212 | if (r) | |
2213 | return (r == -ENODEV) ? -ENXIO : r; | |
2214 | ||
2215 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
2216 | return -EFAULT; | |
c07a0191 CD |
2217 | break; |
2218 | } | |
2219 | ||
2220 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
2221 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
2222 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
2223 | u32 reg = 0; | |
2224 | ||
2225 | r = vgic_attr_regs_access(dev, attr, ®, false); | |
2226 | if (r) | |
2227 | return r; | |
2228 | r = put_user(reg, uaddr); | |
2229 | break; | |
ce01e4e8 | 2230 | } |
c07a0191 | 2231 | |
ce01e4e8 CD |
2232 | } |
2233 | ||
2234 | return r; | |
7330672b CD |
2235 | } |
2236 | ||
c07a0191 CD |
2237 | static int vgic_has_attr_regs(const struct mmio_range *ranges, |
2238 | phys_addr_t offset) | |
2239 | { | |
2240 | struct kvm_exit_mmio dev_attr_mmio; | |
2241 | ||
2242 | dev_attr_mmio.len = 4; | |
2243 | if (find_matching_range(ranges, &dev_attr_mmio, offset)) | |
2244 | return 0; | |
2245 | else | |
2246 | return -ENXIO; | |
2247 | } | |
2248 | ||
7330672b CD |
2249 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
2250 | { | |
c07a0191 CD |
2251 | phys_addr_t offset; |
2252 | ||
ce01e4e8 CD |
2253 | switch (attr->group) { |
2254 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
2255 | switch (attr->attr) { | |
2256 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
2257 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
2258 | return 0; | |
2259 | } | |
2260 | break; | |
c07a0191 CD |
2261 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
2262 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2263 | return vgic_has_attr_regs(vgic_dist_ranges, offset); | |
2264 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
2265 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
2266 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); | |
ce01e4e8 | 2267 | } |
7330672b CD |
2268 | return -ENXIO; |
2269 | } | |
2270 | ||
2271 | static void vgic_destroy(struct kvm_device *dev) | |
2272 | { | |
2273 | kfree(dev); | |
2274 | } | |
2275 | ||
2276 | static int vgic_create(struct kvm_device *dev, u32 type) | |
2277 | { | |
2278 | return kvm_vgic_create(dev->kvm); | |
2279 | } | |
2280 | ||
c06a841b | 2281 | static struct kvm_device_ops kvm_arm_vgic_v2_ops = { |
7330672b CD |
2282 | .name = "kvm-arm-vgic", |
2283 | .create = vgic_create, | |
2284 | .destroy = vgic_destroy, | |
2285 | .set_attr = vgic_set_attr, | |
2286 | .get_attr = vgic_get_attr, | |
2287 | .has_attr = vgic_has_attr, | |
2288 | }; | |
c06a841b WD |
2289 | |
2290 | static void vgic_init_maintenance_interrupt(void *info) | |
2291 | { | |
2292 | enable_percpu_irq(vgic->maint_irq, 0); | |
2293 | } | |
2294 | ||
2295 | static int vgic_cpu_notify(struct notifier_block *self, | |
2296 | unsigned long action, void *cpu) | |
2297 | { | |
2298 | switch (action) { | |
2299 | case CPU_STARTING: | |
2300 | case CPU_STARTING_FROZEN: | |
2301 | vgic_init_maintenance_interrupt(NULL); | |
2302 | break; | |
2303 | case CPU_DYING: | |
2304 | case CPU_DYING_FROZEN: | |
2305 | disable_percpu_irq(vgic->maint_irq); | |
2306 | break; | |
2307 | } | |
2308 | ||
2309 | return NOTIFY_OK; | |
2310 | } | |
2311 | ||
2312 | static struct notifier_block vgic_cpu_nb = { | |
2313 | .notifier_call = vgic_cpu_notify, | |
2314 | }; | |
2315 | ||
2316 | static const struct of_device_id vgic_ids[] = { | |
2317 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
2318 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
2319 | {}, | |
2320 | }; | |
2321 | ||
2322 | int kvm_vgic_hyp_init(void) | |
2323 | { | |
2324 | const struct of_device_id *matched_id; | |
a875dafc CD |
2325 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2326 | const struct vgic_params **); | |
c06a841b WD |
2327 | struct device_node *vgic_node; |
2328 | int ret; | |
2329 | ||
2330 | vgic_node = of_find_matching_node_and_match(NULL, | |
2331 | vgic_ids, &matched_id); | |
2332 | if (!vgic_node) { | |
2333 | kvm_err("error: no compatible GIC node found\n"); | |
2334 | return -ENODEV; | |
2335 | } | |
2336 | ||
2337 | vgic_probe = matched_id->data; | |
2338 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2339 | if (ret) | |
2340 | return ret; | |
2341 | ||
2342 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2343 | "vgic", kvm_get_running_vcpus()); | |
2344 | if (ret) { | |
2345 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2346 | return ret; | |
2347 | } | |
2348 | ||
2349 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2350 | if (ret) { | |
2351 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2352 | goto out_free_irq; | |
2353 | } | |
2354 | ||
2355 | /* Callback into for arch code for setup */ | |
2356 | vgic_arch_setup(vgic); | |
2357 | ||
2358 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
2359 | ||
2360 | return kvm_register_device_ops(&kvm_arm_vgic_v2_ops, | |
2361 | KVM_DEV_TYPE_ARM_VGIC_V2); | |
2362 | ||
2363 | out_free_irq: | |
2364 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2365 | return ret; | |
2366 | } |