Commit | Line | Data |
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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
01ac5e34 | 19 | #include <linux/cpu.h> |
1a89dd91 MZ |
20 | #include <linux/kvm.h> |
21 | #include <linux/kvm_host.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
01ac5e34 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
2a2f3e26 | 27 | #include <linux/uaccess.h> |
01ac5e34 MZ |
28 | |
29 | #include <linux/irqchip/arm-gic.h> | |
30 | ||
1a89dd91 | 31 | #include <asm/kvm_emulate.h> |
01ac5e34 MZ |
32 | #include <asm/kvm_arm.h> |
33 | #include <asm/kvm_mmu.h> | |
1a89dd91 | 34 | |
b47ef92a MZ |
35 | /* |
36 | * How the whole thing works (courtesy of Christoffer Dall): | |
37 | * | |
38 | * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if | |
39 | * something is pending | |
227844f5 | 40 | * - VGIC pending interrupts are stored on the vgic.irq_pending vgic |
b47ef92a MZ |
41 | * bitmap (this bitmap is updated by both user land ioctls and guest |
42 | * mmio ops, and other in-kernel peripherals such as the | |
43 | * arch. timers) and indicate the 'wire' state. | |
44 | * - Every time the bitmap changes, the irq_pending_on_cpu oracle is | |
45 | * recalculated | |
46 | * - To calculate the oracle, we need info for each cpu from | |
47 | * compute_pending_for_cpu, which considers: | |
227844f5 CD |
48 | * - PPI: dist->irq_pending & dist->irq_enable |
49 | * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target | |
b47ef92a MZ |
50 | * - irq_spi_target is a 'formatted' version of the GICD_ICFGR |
51 | * registers, stored on each vcpu. We only keep one bit of | |
52 | * information per interrupt, making sure that only one vcpu can | |
53 | * accept the interrupt. | |
54 | * - The same is true when injecting an interrupt, except that we only | |
55 | * consider a single interrupt at a time. The irq_spi_cpu array | |
56 | * contains the target CPU for each SPI. | |
57 | * | |
58 | * The handling of level interrupts adds some extra complexity. We | |
59 | * need to track when the interrupt has been EOIed, so we can sample | |
60 | * the 'line' again. This is achieved as such: | |
61 | * | |
62 | * - When a level interrupt is moved onto a vcpu, the corresponding | |
dbf20f9d | 63 | * bit in irq_queued is set. As long as this bit is set, the line |
b47ef92a MZ |
64 | * will be ignored for further interrupts. The interrupt is injected |
65 | * into the vcpu with the GICH_LR_EOI bit set (generate a | |
66 | * maintenance interrupt on EOI). | |
67 | * - When the interrupt is EOIed, the maintenance interrupt fires, | |
dbf20f9d | 68 | * and clears the corresponding bit in irq_queued. This allows the |
b47ef92a MZ |
69 | * interrupt line to be sampled again. |
70 | */ | |
71 | ||
330690cd CD |
72 | #define VGIC_ADDR_UNDEF (-1) |
73 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) | |
74 | ||
fa20f5ae CD |
75 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
76 | #define IMPLEMENTER_ARM 0x43b | |
77 | #define GICC_ARCH_VERSION_V2 0x2 | |
78 | ||
1a89dd91 MZ |
79 | #define ACCESS_READ_VALUE (1 << 0) |
80 | #define ACCESS_READ_RAZ (0 << 0) | |
81 | #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) | |
82 | #define ACCESS_WRITE_IGNORED (0 << 1) | |
83 | #define ACCESS_WRITE_SETBIT (1 << 1) | |
84 | #define ACCESS_WRITE_CLEARBIT (2 << 1) | |
85 | #define ACCESS_WRITE_VALUE (3 << 1) | |
86 | #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) | |
87 | ||
a1fcb44e | 88 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); |
8d5c6b06 | 89 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); |
b47ef92a | 90 | static void vgic_update_state(struct kvm *kvm); |
5863c2ce | 91 | static void vgic_kick_vcpus(struct kvm *kvm); |
b47ef92a | 92 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); |
8d5c6b06 MZ |
93 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); |
94 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); | |
beee38b9 MZ |
95 | static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
96 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
01ac5e34 | 97 | |
8f186d52 MZ |
98 | static const struct vgic_ops *vgic_ops; |
99 | static const struct vgic_params *vgic; | |
b47ef92a | 100 | |
9662fb48 VK |
101 | /* |
102 | * struct vgic_bitmap contains unions that provide two views of | |
103 | * the same data. In one case it is an array of registers of | |
104 | * u32's, and in the other case it is a bitmap of unsigned | |
105 | * longs. | |
106 | * | |
107 | * This does not work on 64-bit BE systems, because the bitmap access | |
108 | * will store two consecutive 32-bit words with the higher-addressed | |
109 | * register's bits at the lower index and the lower-addressed register's | |
110 | * bits at the higher index. | |
111 | * | |
112 | * Therefore, swizzle the register index when accessing the 32-bit word | |
113 | * registers to access the right register's value. | |
114 | */ | |
115 | #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 | |
116 | #define REG_OFFSET_SWIZZLE 1 | |
117 | #else | |
118 | #define REG_OFFSET_SWIZZLE 0 | |
119 | #endif | |
b47ef92a MZ |
120 | |
121 | static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, | |
122 | int cpuid, u32 offset) | |
123 | { | |
124 | offset >>= 2; | |
125 | if (!offset) | |
9662fb48 | 126 | return x->percpu[cpuid].reg + (offset ^ REG_OFFSET_SWIZZLE); |
b47ef92a | 127 | else |
9662fb48 | 128 | return x->shared.reg + ((offset - 1) ^ REG_OFFSET_SWIZZLE); |
b47ef92a MZ |
129 | } |
130 | ||
131 | static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, | |
132 | int cpuid, int irq) | |
133 | { | |
134 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
135 | return test_bit(irq, x->percpu[cpuid].reg_ul); | |
136 | ||
137 | return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul); | |
138 | } | |
139 | ||
140 | static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, | |
141 | int irq, int val) | |
142 | { | |
143 | unsigned long *reg; | |
144 | ||
145 | if (irq < VGIC_NR_PRIVATE_IRQS) { | |
146 | reg = x->percpu[cpuid].reg_ul; | |
147 | } else { | |
148 | reg = x->shared.reg_ul; | |
149 | irq -= VGIC_NR_PRIVATE_IRQS; | |
150 | } | |
151 | ||
152 | if (val) | |
153 | set_bit(irq, reg); | |
154 | else | |
155 | clear_bit(irq, reg); | |
156 | } | |
157 | ||
158 | static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) | |
159 | { | |
160 | if (unlikely(cpuid >= VGIC_MAX_CPUS)) | |
161 | return NULL; | |
162 | return x->percpu[cpuid].reg_ul; | |
163 | } | |
164 | ||
165 | static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) | |
166 | { | |
167 | return x->shared.reg_ul; | |
168 | } | |
169 | ||
170 | static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) | |
171 | { | |
172 | offset >>= 2; | |
173 | BUG_ON(offset > (VGIC_NR_IRQS / 4)); | |
8d98915b | 174 | if (offset < 8) |
b47ef92a MZ |
175 | return x->percpu[cpuid] + offset; |
176 | else | |
177 | return x->shared + offset - 8; | |
178 | } | |
179 | ||
180 | #define VGIC_CFG_LEVEL 0 | |
181 | #define VGIC_CFG_EDGE 1 | |
182 | ||
183 | static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) | |
184 | { | |
185 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
186 | int irq_val; | |
187 | ||
188 | irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq); | |
189 | return irq_val == VGIC_CFG_EDGE; | |
190 | } | |
191 | ||
192 | static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq) | |
193 | { | |
194 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
195 | ||
196 | return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq); | |
197 | } | |
198 | ||
dbf20f9d | 199 | static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
200 | { |
201 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
202 | ||
dbf20f9d | 203 | return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq); |
9d949dce MZ |
204 | } |
205 | ||
dbf20f9d | 206 | static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
207 | { |
208 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
209 | ||
dbf20f9d | 210 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1); |
9d949dce MZ |
211 | } |
212 | ||
dbf20f9d | 213 | static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq) |
9d949dce MZ |
214 | { |
215 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
216 | ||
dbf20f9d | 217 | vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0); |
9d949dce MZ |
218 | } |
219 | ||
220 | static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq) | |
221 | { | |
222 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
223 | ||
227844f5 | 224 | return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq); |
9d949dce MZ |
225 | } |
226 | ||
227844f5 | 227 | static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
228 | { |
229 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
230 | ||
227844f5 | 231 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1); |
b47ef92a MZ |
232 | } |
233 | ||
227844f5 | 234 | static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq) |
b47ef92a MZ |
235 | { |
236 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
237 | ||
227844f5 | 238 | vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0); |
b47ef92a MZ |
239 | } |
240 | ||
241 | static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) | |
242 | { | |
243 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
244 | set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
245 | else | |
246 | set_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
247 | vcpu->arch.vgic_cpu.pending_shared); | |
248 | } | |
249 | ||
250 | static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) | |
251 | { | |
252 | if (irq < VGIC_NR_PRIVATE_IRQS) | |
253 | clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); | |
254 | else | |
255 | clear_bit(irq - VGIC_NR_PRIVATE_IRQS, | |
256 | vcpu->arch.vgic_cpu.pending_shared); | |
257 | } | |
258 | ||
dbf20f9d CD |
259 | static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq) |
260 | { | |
261 | return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq); | |
262 | } | |
263 | ||
1a89dd91 MZ |
264 | static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) |
265 | { | |
1c9f0471 | 266 | return le32_to_cpu(*((u32 *)mmio->data)) & mask; |
1a89dd91 MZ |
267 | } |
268 | ||
269 | static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) | |
270 | { | |
1c9f0471 | 271 | *((u32 *)mmio->data) = cpu_to_le32(value) & mask; |
1a89dd91 MZ |
272 | } |
273 | ||
274 | /** | |
275 | * vgic_reg_access - access vgic register | |
276 | * @mmio: pointer to the data describing the mmio access | |
277 | * @reg: pointer to the virtual backing of vgic distributor data | |
278 | * @offset: least significant 2 bits used for word offset | |
279 | * @mode: ACCESS_ mode (see defines above) | |
280 | * | |
281 | * Helper to make vgic register access easier using one of the access | |
282 | * modes defined for vgic register access | |
283 | * (read,raz,write-ignored,setbit,clearbit,write) | |
284 | */ | |
285 | static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, | |
286 | phys_addr_t offset, int mode) | |
287 | { | |
288 | int word_offset = (offset & 3) * 8; | |
289 | u32 mask = (1UL << (mmio->len * 8)) - 1; | |
290 | u32 regval; | |
291 | ||
292 | /* | |
293 | * Any alignment fault should have been delivered to the guest | |
294 | * directly (ARM ARM B3.12.7 "Prioritization of aborts"). | |
295 | */ | |
296 | ||
297 | if (reg) { | |
298 | regval = *reg; | |
299 | } else { | |
300 | BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED)); | |
301 | regval = 0; | |
302 | } | |
303 | ||
304 | if (mmio->is_write) { | |
305 | u32 data = mmio_data_read(mmio, mask) << word_offset; | |
306 | switch (ACCESS_WRITE_MASK(mode)) { | |
307 | case ACCESS_WRITE_IGNORED: | |
308 | return; | |
309 | ||
310 | case ACCESS_WRITE_SETBIT: | |
311 | regval |= data; | |
312 | break; | |
313 | ||
314 | case ACCESS_WRITE_CLEARBIT: | |
315 | regval &= ~data; | |
316 | break; | |
317 | ||
318 | case ACCESS_WRITE_VALUE: | |
319 | regval = (regval & ~(mask << word_offset)) | data; | |
320 | break; | |
321 | } | |
322 | *reg = regval; | |
323 | } else { | |
324 | switch (ACCESS_READ_MASK(mode)) { | |
325 | case ACCESS_READ_RAZ: | |
326 | regval = 0; | |
327 | /* fall through */ | |
328 | ||
329 | case ACCESS_READ_VALUE: | |
330 | mmio_data_write(mmio, mask, regval >> word_offset); | |
331 | } | |
332 | } | |
333 | } | |
334 | ||
b47ef92a MZ |
335 | static bool handle_mmio_misc(struct kvm_vcpu *vcpu, |
336 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
337 | { | |
338 | u32 reg; | |
339 | u32 word_offset = offset & 3; | |
340 | ||
341 | switch (offset & ~3) { | |
fa20f5ae | 342 | case 0: /* GICD_CTLR */ |
b47ef92a MZ |
343 | reg = vcpu->kvm->arch.vgic.enabled; |
344 | vgic_reg_access(mmio, ®, word_offset, | |
345 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
346 | if (mmio->is_write) { | |
347 | vcpu->kvm->arch.vgic.enabled = reg & 1; | |
348 | vgic_update_state(vcpu->kvm); | |
349 | return true; | |
350 | } | |
351 | break; | |
352 | ||
fa20f5ae | 353 | case 4: /* GICD_TYPER */ |
b47ef92a MZ |
354 | reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5; |
355 | reg |= (VGIC_NR_IRQS >> 5) - 1; | |
356 | vgic_reg_access(mmio, ®, word_offset, | |
357 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
358 | break; | |
359 | ||
fa20f5ae CD |
360 | case 8: /* GICD_IIDR */ |
361 | reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); | |
b47ef92a MZ |
362 | vgic_reg_access(mmio, ®, word_offset, |
363 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
364 | break; | |
365 | } | |
366 | ||
367 | return false; | |
368 | } | |
369 | ||
370 | static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, | |
371 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
372 | { | |
373 | vgic_reg_access(mmio, NULL, offset, | |
374 | ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); | |
375 | return false; | |
376 | } | |
377 | ||
378 | static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu, | |
379 | struct kvm_exit_mmio *mmio, | |
380 | phys_addr_t offset) | |
381 | { | |
382 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
383 | vcpu->vcpu_id, offset); | |
384 | vgic_reg_access(mmio, reg, offset, | |
385 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
386 | if (mmio->is_write) { | |
387 | vgic_update_state(vcpu->kvm); | |
388 | return true; | |
389 | } | |
390 | ||
391 | return false; | |
392 | } | |
393 | ||
394 | static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu, | |
395 | struct kvm_exit_mmio *mmio, | |
396 | phys_addr_t offset) | |
397 | { | |
398 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled, | |
399 | vcpu->vcpu_id, offset); | |
400 | vgic_reg_access(mmio, reg, offset, | |
401 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
402 | if (mmio->is_write) { | |
403 | if (offset < 4) /* Force SGI enabled */ | |
404 | *reg |= 0xffff; | |
a1fcb44e | 405 | vgic_retire_disabled_irqs(vcpu); |
b47ef92a MZ |
406 | vgic_update_state(vcpu->kvm); |
407 | return true; | |
408 | } | |
409 | ||
410 | return false; | |
411 | } | |
412 | ||
413 | static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu, | |
414 | struct kvm_exit_mmio *mmio, | |
415 | phys_addr_t offset) | |
416 | { | |
227844f5 | 417 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_pending, |
b47ef92a MZ |
418 | vcpu->vcpu_id, offset); |
419 | vgic_reg_access(mmio, reg, offset, | |
420 | ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT); | |
421 | if (mmio->is_write) { | |
422 | vgic_update_state(vcpu->kvm); | |
423 | return true; | |
424 | } | |
425 | ||
426 | return false; | |
427 | } | |
428 | ||
429 | static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu, | |
430 | struct kvm_exit_mmio *mmio, | |
431 | phys_addr_t offset) | |
432 | { | |
227844f5 | 433 | u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_pending, |
b47ef92a MZ |
434 | vcpu->vcpu_id, offset); |
435 | vgic_reg_access(mmio, reg, offset, | |
436 | ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); | |
437 | if (mmio->is_write) { | |
438 | vgic_update_state(vcpu->kvm); | |
439 | return true; | |
440 | } | |
441 | ||
442 | return false; | |
443 | } | |
444 | ||
445 | static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu, | |
446 | struct kvm_exit_mmio *mmio, | |
447 | phys_addr_t offset) | |
448 | { | |
449 | u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority, | |
450 | vcpu->vcpu_id, offset); | |
451 | vgic_reg_access(mmio, reg, offset, | |
452 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
453 | return false; | |
454 | } | |
455 | ||
456 | #define GICD_ITARGETSR_SIZE 32 | |
457 | #define GICD_CPUTARGETS_BITS 8 | |
458 | #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS) | |
459 | static u32 vgic_get_target_reg(struct kvm *kvm, int irq) | |
460 | { | |
461 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986af8e0 | 462 | int i; |
b47ef92a MZ |
463 | u32 val = 0; |
464 | ||
465 | irq -= VGIC_NR_PRIVATE_IRQS; | |
466 | ||
986af8e0 MZ |
467 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) |
468 | val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8); | |
b47ef92a MZ |
469 | |
470 | return val; | |
471 | } | |
472 | ||
473 | static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) | |
474 | { | |
475 | struct vgic_dist *dist = &kvm->arch.vgic; | |
476 | struct kvm_vcpu *vcpu; | |
477 | int i, c; | |
478 | unsigned long *bmap; | |
479 | u32 target; | |
480 | ||
481 | irq -= VGIC_NR_PRIVATE_IRQS; | |
482 | ||
483 | /* | |
484 | * Pick the LSB in each byte. This ensures we target exactly | |
485 | * one vcpu per IRQ. If the byte is null, assume we target | |
486 | * CPU0. | |
487 | */ | |
488 | for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) { | |
489 | int shift = i * GICD_CPUTARGETS_BITS; | |
490 | target = ffs((val >> shift) & 0xffU); | |
491 | target = target ? (target - 1) : 0; | |
492 | dist->irq_spi_cpu[irq + i] = target; | |
493 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
494 | bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); | |
495 | if (c == target) | |
496 | set_bit(irq + i, bmap); | |
497 | else | |
498 | clear_bit(irq + i, bmap); | |
499 | } | |
500 | } | |
501 | } | |
502 | ||
503 | static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu, | |
504 | struct kvm_exit_mmio *mmio, | |
505 | phys_addr_t offset) | |
506 | { | |
507 | u32 reg; | |
508 | ||
509 | /* We treat the banked interrupts targets as read-only */ | |
510 | if (offset < 32) { | |
511 | u32 roreg = 1 << vcpu->vcpu_id; | |
512 | roreg |= roreg << 8; | |
513 | roreg |= roreg << 16; | |
514 | ||
515 | vgic_reg_access(mmio, &roreg, offset, | |
516 | ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); | |
517 | return false; | |
518 | } | |
519 | ||
520 | reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U); | |
521 | vgic_reg_access(mmio, ®, offset, | |
522 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
523 | if (mmio->is_write) { | |
524 | vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U); | |
525 | vgic_update_state(vcpu->kvm); | |
526 | return true; | |
527 | } | |
528 | ||
529 | return false; | |
530 | } | |
531 | ||
532 | static u32 vgic_cfg_expand(u16 val) | |
533 | { | |
534 | u32 res = 0; | |
535 | int i; | |
536 | ||
537 | /* | |
538 | * Turn a 16bit value like abcd...mnop into a 32bit word | |
539 | * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is. | |
540 | */ | |
541 | for (i = 0; i < 16; i++) | |
542 | res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1); | |
543 | ||
544 | return res; | |
545 | } | |
546 | ||
547 | static u16 vgic_cfg_compress(u32 val) | |
548 | { | |
549 | u16 res = 0; | |
550 | int i; | |
551 | ||
552 | /* | |
553 | * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like | |
554 | * abcd...mnop which is what we really care about. | |
555 | */ | |
556 | for (i = 0; i < 16; i++) | |
557 | res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i; | |
558 | ||
559 | return res; | |
560 | } | |
561 | ||
562 | /* | |
563 | * The distributor uses 2 bits per IRQ for the CFG register, but the | |
564 | * LSB is always 0. As such, we only keep the upper bit, and use the | |
565 | * two above functions to compress/expand the bits | |
566 | */ | |
567 | static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu, | |
568 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
569 | { | |
570 | u32 val; | |
6545eae3 MZ |
571 | u32 *reg; |
572 | ||
6545eae3 | 573 | reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg, |
f2ae85b2 | 574 | vcpu->vcpu_id, offset >> 1); |
6545eae3 | 575 | |
f2ae85b2 | 576 | if (offset & 4) |
b47ef92a MZ |
577 | val = *reg >> 16; |
578 | else | |
579 | val = *reg & 0xffff; | |
580 | ||
581 | val = vgic_cfg_expand(val); | |
582 | vgic_reg_access(mmio, &val, offset, | |
583 | ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); | |
584 | if (mmio->is_write) { | |
f2ae85b2 | 585 | if (offset < 8) { |
b47ef92a MZ |
586 | *reg = ~0U; /* Force PPIs/SGIs to 1 */ |
587 | return false; | |
588 | } | |
589 | ||
590 | val = vgic_cfg_compress(val); | |
f2ae85b2 | 591 | if (offset & 4) { |
b47ef92a MZ |
592 | *reg &= 0xffff; |
593 | *reg |= val << 16; | |
594 | } else { | |
595 | *reg &= 0xffff << 16; | |
596 | *reg |= val; | |
597 | } | |
598 | } | |
599 | ||
600 | return false; | |
601 | } | |
602 | ||
603 | static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, | |
604 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
605 | { | |
606 | u32 reg; | |
607 | vgic_reg_access(mmio, ®, offset, | |
608 | ACCESS_READ_RAZ | ACCESS_WRITE_VALUE); | |
609 | if (mmio->is_write) { | |
610 | vgic_dispatch_sgi(vcpu, reg); | |
611 | vgic_update_state(vcpu->kvm); | |
612 | return true; | |
613 | } | |
614 | ||
615 | return false; | |
616 | } | |
617 | ||
cbd333a4 CD |
618 | /** |
619 | * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor | |
620 | * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs | |
621 | * | |
622 | * Move any pending IRQs that have already been assigned to LRs back to the | |
623 | * emulated distributor state so that the complete emulated state can be read | |
624 | * from the main emulation structures without investigating the LRs. | |
625 | * | |
626 | * Note that IRQs in the active state in the LRs get their pending state moved | |
627 | * to the distributor but the active state stays in the LRs, because we don't | |
628 | * track the active state on the distributor side. | |
629 | */ | |
630 | static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) | |
631 | { | |
632 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
633 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
634 | int vcpu_id = vcpu->vcpu_id; | |
8d5c6b06 | 635 | int i; |
cbd333a4 CD |
636 | |
637 | for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { | |
8d5c6b06 | 638 | struct vgic_lr lr = vgic_get_lr(vcpu, i); |
cbd333a4 CD |
639 | |
640 | /* | |
641 | * There are three options for the state bits: | |
642 | * | |
643 | * 01: pending | |
644 | * 10: active | |
645 | * 11: pending and active | |
646 | * | |
647 | * If the LR holds only an active interrupt (not pending) then | |
648 | * just leave it alone. | |
649 | */ | |
8d5c6b06 | 650 | if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) |
cbd333a4 CD |
651 | continue; |
652 | ||
653 | /* | |
654 | * Reestablish the pending state on the distributor and the | |
655 | * CPU interface. It may have already been pending, but that | |
656 | * is fine, then we are only setting a few bits that were | |
657 | * already set. | |
658 | */ | |
227844f5 | 659 | vgic_dist_irq_set_pending(vcpu, lr.irq); |
8d5c6b06 MZ |
660 | if (lr.irq < VGIC_NR_SGIS) |
661 | dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source; | |
662 | lr.state &= ~LR_STATE_PENDING; | |
663 | vgic_set_lr(vcpu, i, lr); | |
cbd333a4 CD |
664 | |
665 | /* | |
666 | * If there's no state left on the LR (it could still be | |
667 | * active), then the LR does not hold any useful info and can | |
668 | * be marked as free for other use. | |
669 | */ | |
cced50c9 | 670 | if (!(lr.state & LR_STATE_MASK)) { |
8d5c6b06 | 671 | vgic_retire_lr(i, lr.irq, vcpu); |
cced50c9 CD |
672 | vgic_irq_clear_queued(vcpu, lr.irq); |
673 | } | |
cbd333a4 CD |
674 | |
675 | /* Finally update the VGIC state. */ | |
676 | vgic_update_state(vcpu->kvm); | |
677 | } | |
678 | } | |
679 | ||
90a5355e CD |
680 | /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */ |
681 | static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, | |
682 | struct kvm_exit_mmio *mmio, | |
683 | phys_addr_t offset) | |
c07a0191 | 684 | { |
90a5355e CD |
685 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
686 | int sgi; | |
687 | int min_sgi = (offset & ~0x3) * 4; | |
688 | int max_sgi = min_sgi + 3; | |
689 | int vcpu_id = vcpu->vcpu_id; | |
690 | u32 reg = 0; | |
691 | ||
692 | /* Copy source SGIs from distributor side */ | |
693 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
694 | int shift = 8 * (sgi - min_sgi); | |
695 | reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift; | |
696 | } | |
697 | ||
698 | mmio_data_write(mmio, ~0, reg); | |
c07a0191 CD |
699 | return false; |
700 | } | |
701 | ||
90a5355e CD |
702 | static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu, |
703 | struct kvm_exit_mmio *mmio, | |
704 | phys_addr_t offset, bool set) | |
705 | { | |
706 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
707 | int sgi; | |
708 | int min_sgi = (offset & ~0x3) * 4; | |
709 | int max_sgi = min_sgi + 3; | |
710 | int vcpu_id = vcpu->vcpu_id; | |
711 | u32 reg; | |
712 | bool updated = false; | |
713 | ||
714 | reg = mmio_data_read(mmio, ~0); | |
715 | ||
716 | /* Clear pending SGIs on the distributor */ | |
717 | for (sgi = min_sgi; sgi <= max_sgi; sgi++) { | |
718 | u8 mask = reg >> (8 * (sgi - min_sgi)); | |
719 | if (set) { | |
720 | if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask) | |
721 | updated = true; | |
722 | dist->irq_sgi_sources[vcpu_id][sgi] |= mask; | |
723 | } else { | |
724 | if (dist->irq_sgi_sources[vcpu_id][sgi] & mask) | |
725 | updated = true; | |
726 | dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask; | |
727 | } | |
728 | } | |
729 | ||
730 | if (updated) | |
731 | vgic_update_state(vcpu->kvm); | |
732 | ||
733 | return updated; | |
734 | } | |
735 | ||
c07a0191 CD |
736 | static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu, |
737 | struct kvm_exit_mmio *mmio, | |
738 | phys_addr_t offset) | |
739 | { | |
90a5355e CD |
740 | if (!mmio->is_write) |
741 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
742 | else | |
743 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true); | |
744 | } | |
745 | ||
746 | static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu, | |
747 | struct kvm_exit_mmio *mmio, | |
748 | phys_addr_t offset) | |
749 | { | |
750 | if (!mmio->is_write) | |
751 | return read_set_clear_sgi_pend_reg(vcpu, mmio, offset); | |
752 | else | |
753 | return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false); | |
c07a0191 CD |
754 | } |
755 | ||
1a89dd91 MZ |
756 | /* |
757 | * I would have liked to use the kvm_bus_io_*() API instead, but it | |
758 | * cannot cope with banked registers (only the VM pointer is passed | |
759 | * around, and we need the vcpu). One of these days, someone please | |
760 | * fix it! | |
761 | */ | |
762 | struct mmio_range { | |
763 | phys_addr_t base; | |
764 | unsigned long len; | |
765 | bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, | |
766 | phys_addr_t offset); | |
767 | }; | |
768 | ||
1006e8cb | 769 | static const struct mmio_range vgic_dist_ranges[] = { |
b47ef92a MZ |
770 | { |
771 | .base = GIC_DIST_CTRL, | |
772 | .len = 12, | |
773 | .handle_mmio = handle_mmio_misc, | |
774 | }, | |
775 | { | |
776 | .base = GIC_DIST_IGROUP, | |
777 | .len = VGIC_NR_IRQS / 8, | |
778 | .handle_mmio = handle_mmio_raz_wi, | |
779 | }, | |
780 | { | |
781 | .base = GIC_DIST_ENABLE_SET, | |
782 | .len = VGIC_NR_IRQS / 8, | |
783 | .handle_mmio = handle_mmio_set_enable_reg, | |
784 | }, | |
785 | { | |
786 | .base = GIC_DIST_ENABLE_CLEAR, | |
787 | .len = VGIC_NR_IRQS / 8, | |
788 | .handle_mmio = handle_mmio_clear_enable_reg, | |
789 | }, | |
790 | { | |
791 | .base = GIC_DIST_PENDING_SET, | |
792 | .len = VGIC_NR_IRQS / 8, | |
793 | .handle_mmio = handle_mmio_set_pending_reg, | |
794 | }, | |
795 | { | |
796 | .base = GIC_DIST_PENDING_CLEAR, | |
797 | .len = VGIC_NR_IRQS / 8, | |
798 | .handle_mmio = handle_mmio_clear_pending_reg, | |
799 | }, | |
800 | { | |
801 | .base = GIC_DIST_ACTIVE_SET, | |
802 | .len = VGIC_NR_IRQS / 8, | |
803 | .handle_mmio = handle_mmio_raz_wi, | |
804 | }, | |
805 | { | |
806 | .base = GIC_DIST_ACTIVE_CLEAR, | |
807 | .len = VGIC_NR_IRQS / 8, | |
808 | .handle_mmio = handle_mmio_raz_wi, | |
809 | }, | |
810 | { | |
811 | .base = GIC_DIST_PRI, | |
812 | .len = VGIC_NR_IRQS, | |
813 | .handle_mmio = handle_mmio_priority_reg, | |
814 | }, | |
815 | { | |
816 | .base = GIC_DIST_TARGET, | |
817 | .len = VGIC_NR_IRQS, | |
818 | .handle_mmio = handle_mmio_target_reg, | |
819 | }, | |
820 | { | |
821 | .base = GIC_DIST_CONFIG, | |
822 | .len = VGIC_NR_IRQS / 4, | |
823 | .handle_mmio = handle_mmio_cfg_reg, | |
824 | }, | |
825 | { | |
826 | .base = GIC_DIST_SOFTINT, | |
827 | .len = 4, | |
828 | .handle_mmio = handle_mmio_sgi_reg, | |
829 | }, | |
c07a0191 CD |
830 | { |
831 | .base = GIC_DIST_SGI_PENDING_CLEAR, | |
832 | .len = VGIC_NR_SGIS, | |
833 | .handle_mmio = handle_mmio_sgi_clear, | |
834 | }, | |
835 | { | |
836 | .base = GIC_DIST_SGI_PENDING_SET, | |
837 | .len = VGIC_NR_SGIS, | |
838 | .handle_mmio = handle_mmio_sgi_set, | |
839 | }, | |
1a89dd91 MZ |
840 | {} |
841 | }; | |
842 | ||
843 | static const | |
844 | struct mmio_range *find_matching_range(const struct mmio_range *ranges, | |
845 | struct kvm_exit_mmio *mmio, | |
1006e8cb | 846 | phys_addr_t offset) |
1a89dd91 MZ |
847 | { |
848 | const struct mmio_range *r = ranges; | |
1a89dd91 MZ |
849 | |
850 | while (r->len) { | |
1006e8cb CD |
851 | if (offset >= r->base && |
852 | (offset + mmio->len) <= (r->base + r->len)) | |
1a89dd91 MZ |
853 | return r; |
854 | r++; | |
855 | } | |
856 | ||
857 | return NULL; | |
858 | } | |
859 | ||
860 | /** | |
861 | * vgic_handle_mmio - handle an in-kernel MMIO access | |
862 | * @vcpu: pointer to the vcpu performing the access | |
863 | * @run: pointer to the kvm_run structure | |
864 | * @mmio: pointer to the data describing the access | |
865 | * | |
866 | * returns true if the MMIO access has been performed in kernel space, | |
867 | * and false if it needs to be emulated in user space. | |
868 | */ | |
869 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
870 | struct kvm_exit_mmio *mmio) | |
871 | { | |
b47ef92a MZ |
872 | const struct mmio_range *range; |
873 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
874 | unsigned long base = dist->vgic_dist_base; | |
875 | bool updated_state; | |
876 | unsigned long offset; | |
877 | ||
878 | if (!irqchip_in_kernel(vcpu->kvm) || | |
879 | mmio->phys_addr < base || | |
880 | (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE)) | |
881 | return false; | |
882 | ||
883 | /* We don't support ldrd / strd or ldm / stm to the emulated vgic */ | |
884 | if (mmio->len > 4) { | |
885 | kvm_inject_dabt(vcpu, mmio->phys_addr); | |
886 | return true; | |
887 | } | |
888 | ||
1006e8cb CD |
889 | offset = mmio->phys_addr - base; |
890 | range = find_matching_range(vgic_dist_ranges, mmio, offset); | |
b47ef92a MZ |
891 | if (unlikely(!range || !range->handle_mmio)) { |
892 | pr_warn("Unhandled access %d %08llx %d\n", | |
893 | mmio->is_write, mmio->phys_addr, mmio->len); | |
894 | return false; | |
895 | } | |
896 | ||
897 | spin_lock(&vcpu->kvm->arch.vgic.lock); | |
898 | offset = mmio->phys_addr - range->base - base; | |
899 | updated_state = range->handle_mmio(vcpu, mmio, offset); | |
900 | spin_unlock(&vcpu->kvm->arch.vgic.lock); | |
901 | kvm_prepare_mmio(run, mmio); | |
902 | kvm_handle_mmio_return(vcpu, run); | |
903 | ||
5863c2ce MZ |
904 | if (updated_state) |
905 | vgic_kick_vcpus(vcpu->kvm); | |
906 | ||
b47ef92a MZ |
907 | return true; |
908 | } | |
909 | ||
910 | static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg) | |
911 | { | |
912 | struct kvm *kvm = vcpu->kvm; | |
913 | struct vgic_dist *dist = &kvm->arch.vgic; | |
914 | int nrcpus = atomic_read(&kvm->online_vcpus); | |
915 | u8 target_cpus; | |
916 | int sgi, mode, c, vcpu_id; | |
917 | ||
918 | vcpu_id = vcpu->vcpu_id; | |
919 | ||
920 | sgi = reg & 0xf; | |
921 | target_cpus = (reg >> 16) & 0xff; | |
922 | mode = (reg >> 24) & 3; | |
923 | ||
924 | switch (mode) { | |
925 | case 0: | |
926 | if (!target_cpus) | |
927 | return; | |
91021a6c | 928 | break; |
b47ef92a MZ |
929 | |
930 | case 1: | |
931 | target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff; | |
932 | break; | |
933 | ||
934 | case 2: | |
935 | target_cpus = 1 << vcpu_id; | |
936 | break; | |
937 | } | |
938 | ||
939 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
940 | if (target_cpus & 1) { | |
941 | /* Flag the SGI as pending */ | |
227844f5 | 942 | vgic_dist_irq_set_pending(vcpu, sgi); |
b47ef92a MZ |
943 | dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id; |
944 | kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c); | |
945 | } | |
946 | ||
947 | target_cpus >>= 1; | |
948 | } | |
949 | } | |
950 | ||
951 | static int compute_pending_for_cpu(struct kvm_vcpu *vcpu) | |
952 | { | |
9d949dce MZ |
953 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
954 | unsigned long *pending, *enabled, *pend_percpu, *pend_shared; | |
955 | unsigned long pending_private, pending_shared; | |
956 | int vcpu_id; | |
957 | ||
958 | vcpu_id = vcpu->vcpu_id; | |
959 | pend_percpu = vcpu->arch.vgic_cpu.pending_percpu; | |
960 | pend_shared = vcpu->arch.vgic_cpu.pending_shared; | |
961 | ||
227844f5 | 962 | pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id); |
9d949dce MZ |
963 | enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id); |
964 | bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS); | |
965 | ||
227844f5 | 966 | pending = vgic_bitmap_get_shared_map(&dist->irq_pending); |
9d949dce MZ |
967 | enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled); |
968 | bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS); | |
969 | bitmap_and(pend_shared, pend_shared, | |
970 | vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]), | |
971 | VGIC_NR_SHARED_IRQS); | |
972 | ||
973 | pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS); | |
974 | pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS); | |
975 | return (pending_private < VGIC_NR_PRIVATE_IRQS || | |
976 | pending_shared < VGIC_NR_SHARED_IRQS); | |
b47ef92a MZ |
977 | } |
978 | ||
979 | /* | |
980 | * Update the interrupt state and determine which CPUs have pending | |
981 | * interrupts. Must be called with distributor lock held. | |
982 | */ | |
983 | static void vgic_update_state(struct kvm *kvm) | |
984 | { | |
985 | struct vgic_dist *dist = &kvm->arch.vgic; | |
986 | struct kvm_vcpu *vcpu; | |
987 | int c; | |
988 | ||
989 | if (!dist->enabled) { | |
990 | set_bit(0, &dist->irq_pending_on_cpu); | |
991 | return; | |
992 | } | |
993 | ||
994 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
995 | if (compute_pending_for_cpu(vcpu)) { | |
996 | pr_debug("CPU%d has pending interrupts\n", c); | |
997 | set_bit(c, &dist->irq_pending_on_cpu); | |
998 | } | |
999 | } | |
1a89dd91 | 1000 | } |
330690cd | 1001 | |
8d5c6b06 MZ |
1002 | static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) |
1003 | { | |
8f186d52 | 1004 | return vgic_ops->get_lr(vcpu, lr); |
8d5c6b06 MZ |
1005 | } |
1006 | ||
1007 | static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, | |
1008 | struct vgic_lr vlr) | |
1009 | { | |
8f186d52 | 1010 | vgic_ops->set_lr(vcpu, lr, vlr); |
8d5c6b06 MZ |
1011 | } |
1012 | ||
69bb2c9f MZ |
1013 | static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, |
1014 | struct vgic_lr vlr) | |
1015 | { | |
8f186d52 | 1016 | vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); |
69bb2c9f MZ |
1017 | } |
1018 | ||
1019 | static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) | |
1020 | { | |
8f186d52 | 1021 | return vgic_ops->get_elrsr(vcpu); |
69bb2c9f MZ |
1022 | } |
1023 | ||
8d6a0313 MZ |
1024 | static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) |
1025 | { | |
8f186d52 | 1026 | return vgic_ops->get_eisr(vcpu); |
8d6a0313 MZ |
1027 | } |
1028 | ||
495dd859 MZ |
1029 | static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) |
1030 | { | |
8f186d52 | 1031 | return vgic_ops->get_interrupt_status(vcpu); |
495dd859 MZ |
1032 | } |
1033 | ||
909d9b50 MZ |
1034 | static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) |
1035 | { | |
8f186d52 | 1036 | vgic_ops->enable_underflow(vcpu); |
909d9b50 MZ |
1037 | } |
1038 | ||
1039 | static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) | |
1040 | { | |
8f186d52 | 1041 | vgic_ops->disable_underflow(vcpu); |
909d9b50 MZ |
1042 | } |
1043 | ||
beee38b9 MZ |
1044 | static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) |
1045 | { | |
8f186d52 | 1046 | vgic_ops->get_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1047 | } |
1048 | ||
1049 | static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) | |
1050 | { | |
8f186d52 | 1051 | vgic_ops->set_vmcr(vcpu, vmcr); |
beee38b9 MZ |
1052 | } |
1053 | ||
da8dafd1 MZ |
1054 | static inline void vgic_enable(struct kvm_vcpu *vcpu) |
1055 | { | |
8f186d52 | 1056 | vgic_ops->enable(vcpu); |
da8dafd1 MZ |
1057 | } |
1058 | ||
8d5c6b06 MZ |
1059 | static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) |
1060 | { | |
1061 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1062 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); | |
1063 | ||
1064 | vlr.state = 0; | |
1065 | vgic_set_lr(vcpu, lr_nr, vlr); | |
1066 | clear_bit(lr_nr, vgic_cpu->lr_used); | |
1067 | vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; | |
1068 | } | |
a1fcb44e MZ |
1069 | |
1070 | /* | |
1071 | * An interrupt may have been disabled after being made pending on the | |
1072 | * CPU interface (the classic case is a timer running while we're | |
1073 | * rebooting the guest - the interrupt would kick as soon as the CPU | |
1074 | * interface gets enabled, with deadly consequences). | |
1075 | * | |
1076 | * The solution is to examine already active LRs, and check the | |
1077 | * interrupt is still enabled. If not, just retire it. | |
1078 | */ | |
1079 | static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) | |
1080 | { | |
1081 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1082 | int lr; | |
1083 | ||
8f186d52 | 1084 | for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { |
8d5c6b06 | 1085 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
a1fcb44e | 1086 | |
8d5c6b06 MZ |
1087 | if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { |
1088 | vgic_retire_lr(lr, vlr.irq, vcpu); | |
dbf20f9d CD |
1089 | if (vgic_irq_is_queued(vcpu, vlr.irq)) |
1090 | vgic_irq_clear_queued(vcpu, vlr.irq); | |
a1fcb44e MZ |
1091 | } |
1092 | } | |
1093 | } | |
1094 | ||
9d949dce MZ |
1095 | /* |
1096 | * Queue an interrupt to a CPU virtual interface. Return true on success, | |
1097 | * or false if it wasn't possible to queue it. | |
1098 | */ | |
1099 | static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) | |
1100 | { | |
1101 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
8d5c6b06 | 1102 | struct vgic_lr vlr; |
9d949dce MZ |
1103 | int lr; |
1104 | ||
1105 | /* Sanitize the input... */ | |
1106 | BUG_ON(sgi_source_id & ~7); | |
1107 | BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); | |
1108 | BUG_ON(irq >= VGIC_NR_IRQS); | |
1109 | ||
1110 | kvm_debug("Queue IRQ%d\n", irq); | |
1111 | ||
1112 | lr = vgic_cpu->vgic_irq_lr_map[irq]; | |
1113 | ||
1114 | /* Do we have an active interrupt for the same CPUID? */ | |
8d5c6b06 MZ |
1115 | if (lr != LR_EMPTY) { |
1116 | vlr = vgic_get_lr(vcpu, lr); | |
1117 | if (vlr.source == sgi_source_id) { | |
1118 | kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); | |
1119 | BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); | |
1120 | vlr.state |= LR_STATE_PENDING; | |
1121 | vgic_set_lr(vcpu, lr, vlr); | |
1122 | return true; | |
1123 | } | |
9d949dce MZ |
1124 | } |
1125 | ||
1126 | /* Try to use another LR for this interrupt */ | |
1127 | lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, | |
8f186d52 MZ |
1128 | vgic->nr_lr); |
1129 | if (lr >= vgic->nr_lr) | |
9d949dce MZ |
1130 | return false; |
1131 | ||
1132 | kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); | |
9d949dce MZ |
1133 | vgic_cpu->vgic_irq_lr_map[irq] = lr; |
1134 | set_bit(lr, vgic_cpu->lr_used); | |
1135 | ||
8d5c6b06 MZ |
1136 | vlr.irq = irq; |
1137 | vlr.source = sgi_source_id; | |
1138 | vlr.state = LR_STATE_PENDING; | |
9d949dce | 1139 | if (!vgic_irq_is_edge(vcpu, irq)) |
8d5c6b06 MZ |
1140 | vlr.state |= LR_EOI_INT; |
1141 | ||
1142 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1143 | |
1144 | return true; | |
1145 | } | |
1146 | ||
1147 | static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) | |
1148 | { | |
1149 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1150 | unsigned long sources; | |
1151 | int vcpu_id = vcpu->vcpu_id; | |
1152 | int c; | |
1153 | ||
1154 | sources = dist->irq_sgi_sources[vcpu_id][irq]; | |
1155 | ||
1156 | for_each_set_bit(c, &sources, VGIC_MAX_CPUS) { | |
1157 | if (vgic_queue_irq(vcpu, c, irq)) | |
1158 | clear_bit(c, &sources); | |
1159 | } | |
1160 | ||
1161 | dist->irq_sgi_sources[vcpu_id][irq] = sources; | |
1162 | ||
1163 | /* | |
1164 | * If the sources bitmap has been cleared it means that we | |
1165 | * could queue all the SGIs onto link registers (see the | |
1166 | * clear_bit above), and therefore we are done with them in | |
1167 | * our emulated gic and can get rid of them. | |
1168 | */ | |
1169 | if (!sources) { | |
227844f5 | 1170 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1171 | vgic_cpu_irq_clear(vcpu, irq); |
1172 | return true; | |
1173 | } | |
1174 | ||
1175 | return false; | |
1176 | } | |
1177 | ||
1178 | static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) | |
1179 | { | |
dbf20f9d | 1180 | if (!vgic_can_sample_irq(vcpu, irq)) |
9d949dce MZ |
1181 | return true; /* level interrupt, already queued */ |
1182 | ||
1183 | if (vgic_queue_irq(vcpu, 0, irq)) { | |
1184 | if (vgic_irq_is_edge(vcpu, irq)) { | |
227844f5 | 1185 | vgic_dist_irq_clear_pending(vcpu, irq); |
9d949dce MZ |
1186 | vgic_cpu_irq_clear(vcpu, irq); |
1187 | } else { | |
dbf20f9d | 1188 | vgic_irq_set_queued(vcpu, irq); |
9d949dce MZ |
1189 | } |
1190 | ||
1191 | return true; | |
1192 | } | |
1193 | ||
1194 | return false; | |
1195 | } | |
1196 | ||
1197 | /* | |
1198 | * Fill the list registers with pending interrupts before running the | |
1199 | * guest. | |
1200 | */ | |
1201 | static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1202 | { | |
1203 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1204 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1205 | int i, vcpu_id; | |
1206 | int overflow = 0; | |
1207 | ||
1208 | vcpu_id = vcpu->vcpu_id; | |
1209 | ||
1210 | /* | |
1211 | * We may not have any pending interrupt, or the interrupts | |
1212 | * may have been serviced from another vcpu. In all cases, | |
1213 | * move along. | |
1214 | */ | |
1215 | if (!kvm_vgic_vcpu_pending_irq(vcpu)) { | |
1216 | pr_debug("CPU%d has no pending interrupt\n", vcpu_id); | |
1217 | goto epilog; | |
1218 | } | |
1219 | ||
1220 | /* SGIs */ | |
1221 | for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) { | |
1222 | if (!vgic_queue_sgi(vcpu, i)) | |
1223 | overflow = 1; | |
1224 | } | |
1225 | ||
1226 | /* PPIs */ | |
1227 | for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) { | |
1228 | if (!vgic_queue_hwirq(vcpu, i)) | |
1229 | overflow = 1; | |
1230 | } | |
1231 | ||
1232 | /* SPIs */ | |
1233 | for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) { | |
1234 | if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS)) | |
1235 | overflow = 1; | |
1236 | } | |
1237 | ||
1238 | epilog: | |
1239 | if (overflow) { | |
909d9b50 | 1240 | vgic_enable_underflow(vcpu); |
9d949dce | 1241 | } else { |
909d9b50 | 1242 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1243 | /* |
1244 | * We're about to run this VCPU, and we've consumed | |
1245 | * everything the distributor had in store for | |
1246 | * us. Claim we don't have anything pending. We'll | |
1247 | * adjust that if needed while exiting. | |
1248 | */ | |
1249 | clear_bit(vcpu_id, &dist->irq_pending_on_cpu); | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) | |
1254 | { | |
495dd859 | 1255 | u32 status = vgic_get_interrupt_status(vcpu); |
9d949dce MZ |
1256 | bool level_pending = false; |
1257 | ||
495dd859 | 1258 | kvm_debug("STATUS = %08x\n", status); |
9d949dce | 1259 | |
495dd859 | 1260 | if (status & INT_STATUS_EOI) { |
9d949dce MZ |
1261 | /* |
1262 | * Some level interrupts have been EOIed. Clear their | |
1263 | * active bit. | |
1264 | */ | |
8d6a0313 MZ |
1265 | u64 eisr = vgic_get_eisr(vcpu); |
1266 | unsigned long *eisr_ptr = (unsigned long *)&eisr; | |
8d5c6b06 | 1267 | int lr; |
9d949dce | 1268 | |
8f186d52 | 1269 | for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1270 | struct vgic_lr vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1271 | |
dbf20f9d | 1272 | vgic_irq_clear_queued(vcpu, vlr.irq); |
8d5c6b06 MZ |
1273 | WARN_ON(vlr.state & LR_STATE_MASK); |
1274 | vlr.state = 0; | |
1275 | vgic_set_lr(vcpu, lr, vlr); | |
9d949dce MZ |
1276 | |
1277 | /* Any additional pending interrupt? */ | |
8d5c6b06 MZ |
1278 | if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) { |
1279 | vgic_cpu_irq_set(vcpu, vlr.irq); | |
9d949dce MZ |
1280 | level_pending = true; |
1281 | } else { | |
8d5c6b06 | 1282 | vgic_cpu_irq_clear(vcpu, vlr.irq); |
9d949dce | 1283 | } |
75da01e1 MZ |
1284 | |
1285 | /* | |
1286 | * Despite being EOIed, the LR may not have | |
1287 | * been marked as empty. | |
1288 | */ | |
69bb2c9f | 1289 | vgic_sync_lr_elrsr(vcpu, lr, vlr); |
9d949dce MZ |
1290 | } |
1291 | } | |
1292 | ||
495dd859 | 1293 | if (status & INT_STATUS_UNDERFLOW) |
909d9b50 | 1294 | vgic_disable_underflow(vcpu); |
9d949dce MZ |
1295 | |
1296 | return level_pending; | |
1297 | } | |
1298 | ||
1299 | /* | |
33c83cb3 MZ |
1300 | * Sync back the VGIC state after a guest run. The distributor lock is |
1301 | * needed so we don't get preempted in the middle of the state processing. | |
9d949dce MZ |
1302 | */ |
1303 | static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1304 | { | |
1305 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1306 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
69bb2c9f MZ |
1307 | u64 elrsr; |
1308 | unsigned long *elrsr_ptr; | |
9d949dce MZ |
1309 | int lr, pending; |
1310 | bool level_pending; | |
1311 | ||
1312 | level_pending = vgic_process_maintenance(vcpu); | |
69bb2c9f MZ |
1313 | elrsr = vgic_get_elrsr(vcpu); |
1314 | elrsr_ptr = (unsigned long *)&elrsr; | |
9d949dce MZ |
1315 | |
1316 | /* Clear mappings for empty LRs */ | |
8f186d52 | 1317 | for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { |
8d5c6b06 | 1318 | struct vgic_lr vlr; |
9d949dce MZ |
1319 | |
1320 | if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) | |
1321 | continue; | |
1322 | ||
8d5c6b06 | 1323 | vlr = vgic_get_lr(vcpu, lr); |
9d949dce | 1324 | |
8d5c6b06 MZ |
1325 | BUG_ON(vlr.irq >= VGIC_NR_IRQS); |
1326 | vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; | |
9d949dce MZ |
1327 | } |
1328 | ||
1329 | /* Check if we still have something up our sleeve... */ | |
8f186d52 MZ |
1330 | pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); |
1331 | if (level_pending || pending < vgic->nr_lr) | |
9d949dce MZ |
1332 | set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); |
1333 | } | |
1334 | ||
1335 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) | |
1336 | { | |
1337 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1338 | ||
1339 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1340 | return; | |
1341 | ||
1342 | spin_lock(&dist->lock); | |
1343 | __kvm_vgic_flush_hwstate(vcpu); | |
1344 | spin_unlock(&dist->lock); | |
1345 | } | |
1346 | ||
1347 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) | |
1348 | { | |
33c83cb3 MZ |
1349 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; |
1350 | ||
9d949dce MZ |
1351 | if (!irqchip_in_kernel(vcpu->kvm)) |
1352 | return; | |
1353 | ||
33c83cb3 | 1354 | spin_lock(&dist->lock); |
9d949dce | 1355 | __kvm_vgic_sync_hwstate(vcpu); |
33c83cb3 | 1356 | spin_unlock(&dist->lock); |
9d949dce MZ |
1357 | } |
1358 | ||
1359 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) | |
1360 | { | |
1361 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1362 | ||
1363 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1364 | return 0; | |
1365 | ||
1366 | return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); | |
1367 | } | |
1368 | ||
5863c2ce MZ |
1369 | static void vgic_kick_vcpus(struct kvm *kvm) |
1370 | { | |
1371 | struct kvm_vcpu *vcpu; | |
1372 | int c; | |
1373 | ||
1374 | /* | |
1375 | * We've injected an interrupt, time to find out who deserves | |
1376 | * a good kick... | |
1377 | */ | |
1378 | kvm_for_each_vcpu(c, vcpu, kvm) { | |
1379 | if (kvm_vgic_vcpu_pending_irq(vcpu)) | |
1380 | kvm_vcpu_kick(vcpu); | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level) | |
1385 | { | |
227844f5 | 1386 | int edge_triggered = vgic_irq_is_edge(vcpu, irq); |
5863c2ce MZ |
1387 | int state = vgic_dist_irq_is_pending(vcpu, irq); |
1388 | ||
1389 | /* | |
1390 | * Only inject an interrupt if: | |
1391 | * - edge triggered and we have a rising edge | |
1392 | * - level triggered and we change level | |
1393 | */ | |
227844f5 | 1394 | if (edge_triggered) |
5863c2ce MZ |
1395 | return level > state; |
1396 | else | |
1397 | return level != state; | |
1398 | } | |
1399 | ||
227844f5 | 1400 | static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid, |
5863c2ce MZ |
1401 | unsigned int irq_num, bool level) |
1402 | { | |
1403 | struct vgic_dist *dist = &kvm->arch.vgic; | |
1404 | struct kvm_vcpu *vcpu; | |
227844f5 | 1405 | int edge_triggered, level_triggered; |
5863c2ce MZ |
1406 | int enabled; |
1407 | bool ret = true; | |
1408 | ||
1409 | spin_lock(&dist->lock); | |
1410 | ||
1411 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
227844f5 CD |
1412 | edge_triggered = vgic_irq_is_edge(vcpu, irq_num); |
1413 | level_triggered = !edge_triggered; | |
5863c2ce MZ |
1414 | |
1415 | if (!vgic_validate_injection(vcpu, irq_num, level)) { | |
1416 | ret = false; | |
1417 | goto out; | |
1418 | } | |
1419 | ||
1420 | if (irq_num >= VGIC_NR_PRIVATE_IRQS) { | |
1421 | cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS]; | |
1422 | vcpu = kvm_get_vcpu(kvm, cpuid); | |
1423 | } | |
1424 | ||
1425 | kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid); | |
1426 | ||
1427 | if (level) | |
227844f5 | 1428 | vgic_dist_irq_set_pending(vcpu, irq_num); |
5863c2ce | 1429 | else |
227844f5 | 1430 | vgic_dist_irq_clear_pending(vcpu, irq_num); |
5863c2ce MZ |
1431 | |
1432 | enabled = vgic_irq_is_enabled(vcpu, irq_num); | |
1433 | ||
1434 | if (!enabled) { | |
1435 | ret = false; | |
1436 | goto out; | |
1437 | } | |
1438 | ||
dbf20f9d | 1439 | if (!vgic_can_sample_irq(vcpu, irq_num)) { |
5863c2ce MZ |
1440 | /* |
1441 | * Level interrupt in progress, will be picked up | |
1442 | * when EOId. | |
1443 | */ | |
1444 | ret = false; | |
1445 | goto out; | |
1446 | } | |
1447 | ||
1448 | if (level) { | |
1449 | vgic_cpu_irq_set(vcpu, irq_num); | |
1450 | set_bit(cpuid, &dist->irq_pending_on_cpu); | |
1451 | } | |
1452 | ||
1453 | out: | |
1454 | spin_unlock(&dist->lock); | |
1455 | ||
1456 | return ret; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic | |
1461 | * @kvm: The VM structure pointer | |
1462 | * @cpuid: The CPU for PPIs | |
1463 | * @irq_num: The IRQ number that is assigned to the device | |
1464 | * @level: Edge-triggered: true: to trigger the interrupt | |
1465 | * false: to ignore the call | |
1466 | * Level-sensitive true: activates an interrupt | |
1467 | * false: deactivates an interrupt | |
1468 | * | |
1469 | * The GIC is not concerned with devices being active-LOW or active-HIGH for | |
1470 | * level-sensitive interrupts. You can think of the level parameter as 1 | |
1471 | * being HIGH and 0 being LOW and all devices being active-HIGH. | |
1472 | */ | |
1473 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, | |
1474 | bool level) | |
1475 | { | |
227844f5 | 1476 | if (vgic_update_irq_pending(kvm, cpuid, irq_num, level)) |
5863c2ce MZ |
1477 | vgic_kick_vcpus(kvm); |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
01ac5e34 MZ |
1482 | static irqreturn_t vgic_maintenance_handler(int irq, void *data) |
1483 | { | |
1484 | /* | |
1485 | * We cannot rely on the vgic maintenance interrupt to be | |
1486 | * delivered synchronously. This means we can only use it to | |
1487 | * exit the VM, and we perform the handling of EOIed | |
1488 | * interrupts on the exit path (see vgic_process_maintenance). | |
1489 | */ | |
1490 | return IRQ_HANDLED; | |
1491 | } | |
1492 | ||
e1ba0207 CD |
1493 | /** |
1494 | * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state | |
1495 | * @vcpu: pointer to the vcpu struct | |
1496 | * | |
1497 | * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to | |
1498 | * this vcpu and enable the VGIC for this VCPU | |
1499 | */ | |
01ac5e34 MZ |
1500 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) |
1501 | { | |
1502 | struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; | |
1503 | struct vgic_dist *dist = &vcpu->kvm->arch.vgic; | |
1504 | int i; | |
1505 | ||
01ac5e34 MZ |
1506 | if (vcpu->vcpu_id >= VGIC_MAX_CPUS) |
1507 | return -EBUSY; | |
1508 | ||
1509 | for (i = 0; i < VGIC_NR_IRQS; i++) { | |
1510 | if (i < VGIC_NR_PPIS) | |
1511 | vgic_bitmap_set_irq_val(&dist->irq_enabled, | |
1512 | vcpu->vcpu_id, i, 1); | |
1513 | if (i < VGIC_NR_PRIVATE_IRQS) | |
1514 | vgic_bitmap_set_irq_val(&dist->irq_cfg, | |
1515 | vcpu->vcpu_id, i, VGIC_CFG_EDGE); | |
1516 | ||
1517 | vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY; | |
1518 | } | |
1519 | ||
1520 | /* | |
ca85f623 MZ |
1521 | * Store the number of LRs per vcpu, so we don't have to go |
1522 | * all the way to the distributor structure to find out. Only | |
1523 | * assembly code should use this one. | |
01ac5e34 | 1524 | */ |
8f186d52 | 1525 | vgic_cpu->nr_lr = vgic->nr_lr; |
01ac5e34 | 1526 | |
da8dafd1 | 1527 | vgic_enable(vcpu); |
01ac5e34 MZ |
1528 | |
1529 | return 0; | |
1530 | } | |
1531 | ||
e1ba0207 CD |
1532 | /** |
1533 | * kvm_vgic_init - Initialize global VGIC state before running any VCPUs | |
1534 | * @kvm: pointer to the kvm struct | |
1535 | * | |
1536 | * Map the virtual CPU interface into the VM before running any VCPUs. We | |
1537 | * can't do this at creation time, because user space must first set the | |
1538 | * virtual CPU interface address in the guest physical address space. Also | |
1539 | * initialize the ITARGETSRn regs to 0 on the emulated distributor. | |
1540 | */ | |
01ac5e34 MZ |
1541 | int kvm_vgic_init(struct kvm *kvm) |
1542 | { | |
1543 | int ret = 0, i; | |
1544 | ||
e1ba0207 CD |
1545 | if (!irqchip_in_kernel(kvm)) |
1546 | return 0; | |
1547 | ||
01ac5e34 MZ |
1548 | mutex_lock(&kvm->lock); |
1549 | ||
1550 | if (vgic_initialized(kvm)) | |
1551 | goto out; | |
1552 | ||
1553 | if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) || | |
1554 | IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) { | |
1555 | kvm_err("Need to set vgic cpu and dist addresses first\n"); | |
1556 | ret = -ENXIO; | |
1557 | goto out; | |
1558 | } | |
1559 | ||
1560 | ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, | |
8f186d52 | 1561 | vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE); |
01ac5e34 MZ |
1562 | if (ret) { |
1563 | kvm_err("Unable to remap VGIC CPU to VCPU\n"); | |
1564 | goto out; | |
1565 | } | |
1566 | ||
1567 | for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4) | |
1568 | vgic_set_target_reg(kvm, 0, i); | |
1569 | ||
1570 | kvm->arch.vgic.ready = true; | |
1571 | out: | |
1572 | mutex_unlock(&kvm->lock); | |
1573 | return ret; | |
1574 | } | |
1575 | ||
1576 | int kvm_vgic_create(struct kvm *kvm) | |
1577 | { | |
7330672b CD |
1578 | int i, vcpu_lock_idx = -1, ret = 0; |
1579 | struct kvm_vcpu *vcpu; | |
01ac5e34 MZ |
1580 | |
1581 | mutex_lock(&kvm->lock); | |
1582 | ||
7330672b | 1583 | if (kvm->arch.vgic.vctrl_base) { |
01ac5e34 MZ |
1584 | ret = -EEXIST; |
1585 | goto out; | |
1586 | } | |
1587 | ||
7330672b CD |
1588 | /* |
1589 | * Any time a vcpu is run, vcpu_load is called which tries to grab the | |
1590 | * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure | |
1591 | * that no other VCPUs are run while we create the vgic. | |
1592 | */ | |
1593 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1594 | if (!mutex_trylock(&vcpu->mutex)) | |
1595 | goto out_unlock; | |
1596 | vcpu_lock_idx = i; | |
1597 | } | |
1598 | ||
1599 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1600 | if (vcpu->arch.has_run_once) { | |
1601 | ret = -EBUSY; | |
1602 | goto out_unlock; | |
1603 | } | |
1604 | } | |
1605 | ||
01ac5e34 | 1606 | spin_lock_init(&kvm->arch.vgic.lock); |
f982cf4e | 1607 | kvm->arch.vgic.in_kernel = true; |
8f186d52 | 1608 | kvm->arch.vgic.vctrl_base = vgic->vctrl_base; |
01ac5e34 MZ |
1609 | kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; |
1610 | kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; | |
1611 | ||
7330672b CD |
1612 | out_unlock: |
1613 | for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { | |
1614 | vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx); | |
1615 | mutex_unlock(&vcpu->mutex); | |
1616 | } | |
1617 | ||
01ac5e34 MZ |
1618 | out: |
1619 | mutex_unlock(&kvm->lock); | |
1620 | return ret; | |
1621 | } | |
1622 | ||
1fa451bc | 1623 | static int vgic_ioaddr_overlap(struct kvm *kvm) |
330690cd CD |
1624 | { |
1625 | phys_addr_t dist = kvm->arch.vgic.vgic_dist_base; | |
1626 | phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base; | |
1627 | ||
1628 | if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu)) | |
1629 | return 0; | |
1630 | if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) || | |
1631 | (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist)) | |
1632 | return -EBUSY; | |
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr, | |
1637 | phys_addr_t addr, phys_addr_t size) | |
1638 | { | |
1639 | int ret; | |
1640 | ||
ce01e4e8 CD |
1641 | if (addr & ~KVM_PHYS_MASK) |
1642 | return -E2BIG; | |
1643 | ||
1644 | if (addr & (SZ_4K - 1)) | |
1645 | return -EINVAL; | |
1646 | ||
330690cd CD |
1647 | if (!IS_VGIC_ADDR_UNDEF(*ioaddr)) |
1648 | return -EEXIST; | |
1649 | if (addr + size < addr) | |
1650 | return -EINVAL; | |
1651 | ||
30c21170 | 1652 | *ioaddr = addr; |
330690cd CD |
1653 | ret = vgic_ioaddr_overlap(kvm); |
1654 | if (ret) | |
30c21170 HW |
1655 | *ioaddr = VGIC_ADDR_UNDEF; |
1656 | ||
330690cd CD |
1657 | return ret; |
1658 | } | |
1659 | ||
ce01e4e8 CD |
1660 | /** |
1661 | * kvm_vgic_addr - set or get vgic VM base addresses | |
1662 | * @kvm: pointer to the vm struct | |
1663 | * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX | |
1664 | * @addr: pointer to address value | |
1665 | * @write: if true set the address in the VM address space, if false read the | |
1666 | * address | |
1667 | * | |
1668 | * Set or get the vgic base addresses for the distributor and the virtual CPU | |
1669 | * interface in the VM physical address space. These addresses are properties | |
1670 | * of the emulated core/SoC and therefore user space initially knows this | |
1671 | * information. | |
1672 | */ | |
1673 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) | |
330690cd CD |
1674 | { |
1675 | int r = 0; | |
1676 | struct vgic_dist *vgic = &kvm->arch.vgic; | |
1677 | ||
330690cd CD |
1678 | mutex_lock(&kvm->lock); |
1679 | switch (type) { | |
1680 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
ce01e4e8 CD |
1681 | if (write) { |
1682 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base, | |
1683 | *addr, KVM_VGIC_V2_DIST_SIZE); | |
1684 | } else { | |
1685 | *addr = vgic->vgic_dist_base; | |
1686 | } | |
330690cd CD |
1687 | break; |
1688 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
ce01e4e8 CD |
1689 | if (write) { |
1690 | r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base, | |
1691 | *addr, KVM_VGIC_V2_CPU_SIZE); | |
1692 | } else { | |
1693 | *addr = vgic->vgic_cpu_base; | |
1694 | } | |
330690cd CD |
1695 | break; |
1696 | default: | |
1697 | r = -ENODEV; | |
1698 | } | |
1699 | ||
1700 | mutex_unlock(&kvm->lock); | |
1701 | return r; | |
1702 | } | |
7330672b | 1703 | |
c07a0191 CD |
1704 | static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, |
1705 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1706 | { | |
fa20f5ae | 1707 | bool updated = false; |
beee38b9 MZ |
1708 | struct vgic_vmcr vmcr; |
1709 | u32 *vmcr_field; | |
1710 | u32 reg; | |
1711 | ||
1712 | vgic_get_vmcr(vcpu, &vmcr); | |
fa20f5ae CD |
1713 | |
1714 | switch (offset & ~0x3) { | |
1715 | case GIC_CPU_CTRL: | |
beee38b9 | 1716 | vmcr_field = &vmcr.ctlr; |
fa20f5ae CD |
1717 | break; |
1718 | case GIC_CPU_PRIMASK: | |
beee38b9 | 1719 | vmcr_field = &vmcr.pmr; |
fa20f5ae CD |
1720 | break; |
1721 | case GIC_CPU_BINPOINT: | |
beee38b9 | 1722 | vmcr_field = &vmcr.bpr; |
fa20f5ae CD |
1723 | break; |
1724 | case GIC_CPU_ALIAS_BINPOINT: | |
beee38b9 | 1725 | vmcr_field = &vmcr.abpr; |
fa20f5ae | 1726 | break; |
beee38b9 MZ |
1727 | default: |
1728 | BUG(); | |
fa20f5ae CD |
1729 | } |
1730 | ||
1731 | if (!mmio->is_write) { | |
beee38b9 | 1732 | reg = *vmcr_field; |
fa20f5ae CD |
1733 | mmio_data_write(mmio, ~0, reg); |
1734 | } else { | |
1735 | reg = mmio_data_read(mmio, ~0); | |
beee38b9 MZ |
1736 | if (reg != *vmcr_field) { |
1737 | *vmcr_field = reg; | |
1738 | vgic_set_vmcr(vcpu, &vmcr); | |
fa20f5ae | 1739 | updated = true; |
beee38b9 | 1740 | } |
fa20f5ae CD |
1741 | } |
1742 | return updated; | |
1743 | } | |
1744 | ||
1745 | static bool handle_mmio_abpr(struct kvm_vcpu *vcpu, | |
1746 | struct kvm_exit_mmio *mmio, phys_addr_t offset) | |
1747 | { | |
1748 | return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT); | |
c07a0191 CD |
1749 | } |
1750 | ||
fa20f5ae CD |
1751 | static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu, |
1752 | struct kvm_exit_mmio *mmio, | |
1753 | phys_addr_t offset) | |
1754 | { | |
1755 | u32 reg; | |
1756 | ||
1757 | if (mmio->is_write) | |
1758 | return false; | |
1759 | ||
1760 | /* GICC_IIDR */ | |
1761 | reg = (PRODUCT_ID_KVM << 20) | | |
1762 | (GICC_ARCH_VERSION_V2 << 16) | | |
1763 | (IMPLEMENTER_ARM << 0); | |
1764 | mmio_data_write(mmio, ~0, reg); | |
1765 | return false; | |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * CPU Interface Register accesses - these are not accessed by the VM, but by | |
1770 | * user space for saving and restoring VGIC state. | |
1771 | */ | |
c07a0191 CD |
1772 | static const struct mmio_range vgic_cpu_ranges[] = { |
1773 | { | |
1774 | .base = GIC_CPU_CTRL, | |
1775 | .len = 12, | |
1776 | .handle_mmio = handle_cpu_mmio_misc, | |
1777 | }, | |
1778 | { | |
1779 | .base = GIC_CPU_ALIAS_BINPOINT, | |
1780 | .len = 4, | |
fa20f5ae | 1781 | .handle_mmio = handle_mmio_abpr, |
c07a0191 CD |
1782 | }, |
1783 | { | |
1784 | .base = GIC_CPU_ACTIVEPRIO, | |
1785 | .len = 16, | |
fa20f5ae | 1786 | .handle_mmio = handle_mmio_raz_wi, |
c07a0191 CD |
1787 | }, |
1788 | { | |
1789 | .base = GIC_CPU_IDENT, | |
1790 | .len = 4, | |
fa20f5ae | 1791 | .handle_mmio = handle_cpu_mmio_ident, |
c07a0191 CD |
1792 | }, |
1793 | }; | |
1794 | ||
1795 | static int vgic_attr_regs_access(struct kvm_device *dev, | |
1796 | struct kvm_device_attr *attr, | |
1797 | u32 *reg, bool is_write) | |
1798 | { | |
1799 | const struct mmio_range *r = NULL, *ranges; | |
1800 | phys_addr_t offset; | |
1801 | int ret, cpuid, c; | |
1802 | struct kvm_vcpu *vcpu, *tmp_vcpu; | |
1803 | struct vgic_dist *vgic; | |
1804 | struct kvm_exit_mmio mmio; | |
1805 | ||
1806 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
1807 | cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> | |
1808 | KVM_DEV_ARM_VGIC_CPUID_SHIFT; | |
1809 | ||
1810 | mutex_lock(&dev->kvm->lock); | |
1811 | ||
1812 | if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) { | |
1813 | ret = -EINVAL; | |
1814 | goto out; | |
1815 | } | |
1816 | ||
1817 | vcpu = kvm_get_vcpu(dev->kvm, cpuid); | |
1818 | vgic = &dev->kvm->arch.vgic; | |
1819 | ||
1820 | mmio.len = 4; | |
1821 | mmio.is_write = is_write; | |
1822 | if (is_write) | |
1823 | mmio_data_write(&mmio, ~0, *reg); | |
1824 | switch (attr->group) { | |
1825 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1826 | mmio.phys_addr = vgic->vgic_dist_base + offset; | |
1827 | ranges = vgic_dist_ranges; | |
1828 | break; | |
1829 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
1830 | mmio.phys_addr = vgic->vgic_cpu_base + offset; | |
1831 | ranges = vgic_cpu_ranges; | |
1832 | break; | |
1833 | default: | |
1834 | BUG(); | |
1835 | } | |
1836 | r = find_matching_range(ranges, &mmio, offset); | |
1837 | ||
1838 | if (unlikely(!r || !r->handle_mmio)) { | |
1839 | ret = -ENXIO; | |
1840 | goto out; | |
1841 | } | |
1842 | ||
1843 | ||
1844 | spin_lock(&vgic->lock); | |
1845 | ||
1846 | /* | |
1847 | * Ensure that no other VCPU is running by checking the vcpu->cpu | |
1848 | * field. If no other VPCUs are running we can safely access the VGIC | |
1849 | * state, because even if another VPU is run after this point, that | |
1850 | * VCPU will not touch the vgic state, because it will block on | |
1851 | * getting the vgic->lock in kvm_vgic_sync_hwstate(). | |
1852 | */ | |
1853 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) { | |
1854 | if (unlikely(tmp_vcpu->cpu != -1)) { | |
1855 | ret = -EBUSY; | |
1856 | goto out_vgic_unlock; | |
1857 | } | |
1858 | } | |
1859 | ||
cbd333a4 CD |
1860 | /* |
1861 | * Move all pending IRQs from the LRs on all VCPUs so the pending | |
1862 | * state can be properly represented in the register state accessible | |
1863 | * through this API. | |
1864 | */ | |
1865 | kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) | |
1866 | vgic_unqueue_irqs(tmp_vcpu); | |
1867 | ||
c07a0191 CD |
1868 | offset -= r->base; |
1869 | r->handle_mmio(vcpu, &mmio, offset); | |
1870 | ||
1871 | if (!is_write) | |
1872 | *reg = mmio_data_read(&mmio, ~0); | |
1873 | ||
1874 | ret = 0; | |
1875 | out_vgic_unlock: | |
1876 | spin_unlock(&vgic->lock); | |
1877 | out: | |
1878 | mutex_unlock(&dev->kvm->lock); | |
1879 | return ret; | |
1880 | } | |
1881 | ||
7330672b CD |
1882 | static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
1883 | { | |
ce01e4e8 CD |
1884 | int r; |
1885 | ||
1886 | switch (attr->group) { | |
1887 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1888 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1889 | u64 addr; | |
1890 | unsigned long type = (unsigned long)attr->attr; | |
1891 | ||
1892 | if (copy_from_user(&addr, uaddr, sizeof(addr))) | |
1893 | return -EFAULT; | |
1894 | ||
1895 | r = kvm_vgic_addr(dev->kvm, type, &addr, true); | |
1896 | return (r == -ENODEV) ? -ENXIO : r; | |
1897 | } | |
c07a0191 CD |
1898 | |
1899 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1900 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
1901 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1902 | u32 reg; | |
1903 | ||
1904 | if (get_user(reg, uaddr)) | |
1905 | return -EFAULT; | |
1906 | ||
1907 | return vgic_attr_regs_access(dev, attr, ®, true); | |
1908 | } | |
1909 | ||
ce01e4e8 CD |
1910 | } |
1911 | ||
7330672b CD |
1912 | return -ENXIO; |
1913 | } | |
1914 | ||
1915 | static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1916 | { | |
ce01e4e8 CD |
1917 | int r = -ENXIO; |
1918 | ||
1919 | switch (attr->group) { | |
1920 | case KVM_DEV_ARM_VGIC_GRP_ADDR: { | |
1921 | u64 __user *uaddr = (u64 __user *)(long)attr->addr; | |
1922 | u64 addr; | |
1923 | unsigned long type = (unsigned long)attr->attr; | |
1924 | ||
1925 | r = kvm_vgic_addr(dev->kvm, type, &addr, false); | |
1926 | if (r) | |
1927 | return (r == -ENODEV) ? -ENXIO : r; | |
1928 | ||
1929 | if (copy_to_user(uaddr, &addr, sizeof(addr))) | |
1930 | return -EFAULT; | |
c07a0191 CD |
1931 | break; |
1932 | } | |
1933 | ||
1934 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: | |
1935 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: { | |
1936 | u32 __user *uaddr = (u32 __user *)(long)attr->addr; | |
1937 | u32 reg = 0; | |
1938 | ||
1939 | r = vgic_attr_regs_access(dev, attr, ®, false); | |
1940 | if (r) | |
1941 | return r; | |
1942 | r = put_user(reg, uaddr); | |
1943 | break; | |
ce01e4e8 | 1944 | } |
c07a0191 | 1945 | |
ce01e4e8 CD |
1946 | } |
1947 | ||
1948 | return r; | |
7330672b CD |
1949 | } |
1950 | ||
c07a0191 CD |
1951 | static int vgic_has_attr_regs(const struct mmio_range *ranges, |
1952 | phys_addr_t offset) | |
1953 | { | |
1954 | struct kvm_exit_mmio dev_attr_mmio; | |
1955 | ||
1956 | dev_attr_mmio.len = 4; | |
1957 | if (find_matching_range(ranges, &dev_attr_mmio, offset)) | |
1958 | return 0; | |
1959 | else | |
1960 | return -ENXIO; | |
1961 | } | |
1962 | ||
7330672b CD |
1963 | static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
1964 | { | |
c07a0191 CD |
1965 | phys_addr_t offset; |
1966 | ||
ce01e4e8 CD |
1967 | switch (attr->group) { |
1968 | case KVM_DEV_ARM_VGIC_GRP_ADDR: | |
1969 | switch (attr->attr) { | |
1970 | case KVM_VGIC_V2_ADDR_TYPE_DIST: | |
1971 | case KVM_VGIC_V2_ADDR_TYPE_CPU: | |
1972 | return 0; | |
1973 | } | |
1974 | break; | |
c07a0191 CD |
1975 | case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: |
1976 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
1977 | return vgic_has_attr_regs(vgic_dist_ranges, offset); | |
1978 | case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: | |
1979 | offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; | |
1980 | return vgic_has_attr_regs(vgic_cpu_ranges, offset); | |
ce01e4e8 | 1981 | } |
7330672b CD |
1982 | return -ENXIO; |
1983 | } | |
1984 | ||
1985 | static void vgic_destroy(struct kvm_device *dev) | |
1986 | { | |
1987 | kfree(dev); | |
1988 | } | |
1989 | ||
1990 | static int vgic_create(struct kvm_device *dev, u32 type) | |
1991 | { | |
1992 | return kvm_vgic_create(dev->kvm); | |
1993 | } | |
1994 | ||
c06a841b | 1995 | static struct kvm_device_ops kvm_arm_vgic_v2_ops = { |
7330672b CD |
1996 | .name = "kvm-arm-vgic", |
1997 | .create = vgic_create, | |
1998 | .destroy = vgic_destroy, | |
1999 | .set_attr = vgic_set_attr, | |
2000 | .get_attr = vgic_get_attr, | |
2001 | .has_attr = vgic_has_attr, | |
2002 | }; | |
c06a841b WD |
2003 | |
2004 | static void vgic_init_maintenance_interrupt(void *info) | |
2005 | { | |
2006 | enable_percpu_irq(vgic->maint_irq, 0); | |
2007 | } | |
2008 | ||
2009 | static int vgic_cpu_notify(struct notifier_block *self, | |
2010 | unsigned long action, void *cpu) | |
2011 | { | |
2012 | switch (action) { | |
2013 | case CPU_STARTING: | |
2014 | case CPU_STARTING_FROZEN: | |
2015 | vgic_init_maintenance_interrupt(NULL); | |
2016 | break; | |
2017 | case CPU_DYING: | |
2018 | case CPU_DYING_FROZEN: | |
2019 | disable_percpu_irq(vgic->maint_irq); | |
2020 | break; | |
2021 | } | |
2022 | ||
2023 | return NOTIFY_OK; | |
2024 | } | |
2025 | ||
2026 | static struct notifier_block vgic_cpu_nb = { | |
2027 | .notifier_call = vgic_cpu_notify, | |
2028 | }; | |
2029 | ||
2030 | static const struct of_device_id vgic_ids[] = { | |
2031 | { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, | |
2032 | { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, | |
2033 | {}, | |
2034 | }; | |
2035 | ||
2036 | int kvm_vgic_hyp_init(void) | |
2037 | { | |
2038 | const struct of_device_id *matched_id; | |
a875dafc CD |
2039 | const int (*vgic_probe)(struct device_node *,const struct vgic_ops **, |
2040 | const struct vgic_params **); | |
c06a841b WD |
2041 | struct device_node *vgic_node; |
2042 | int ret; | |
2043 | ||
2044 | vgic_node = of_find_matching_node_and_match(NULL, | |
2045 | vgic_ids, &matched_id); | |
2046 | if (!vgic_node) { | |
2047 | kvm_err("error: no compatible GIC node found\n"); | |
2048 | return -ENODEV; | |
2049 | } | |
2050 | ||
2051 | vgic_probe = matched_id->data; | |
2052 | ret = vgic_probe(vgic_node, &vgic_ops, &vgic); | |
2053 | if (ret) | |
2054 | return ret; | |
2055 | ||
2056 | ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, | |
2057 | "vgic", kvm_get_running_vcpus()); | |
2058 | if (ret) { | |
2059 | kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); | |
2060 | return ret; | |
2061 | } | |
2062 | ||
2063 | ret = __register_cpu_notifier(&vgic_cpu_nb); | |
2064 | if (ret) { | |
2065 | kvm_err("Cannot register vgic CPU notifier\n"); | |
2066 | goto out_free_irq; | |
2067 | } | |
2068 | ||
2069 | /* Callback into for arch code for setup */ | |
2070 | vgic_arch_setup(vgic); | |
2071 | ||
2072 | on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); | |
2073 | ||
2074 | return kvm_register_device_ops(&kvm_arm_vgic_v2_ops, | |
2075 | KVM_DEV_TYPE_ARM_VGIC_V2); | |
2076 | ||
2077 | out_free_irq: | |
2078 | free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); | |
2079 | return ret; | |
2080 | } |