[deliverable/linux.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>
#include <trace/events/kvm.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			if (redir_index < IOAPIC_NUM_PINS)
				redir_content =
					ioapic->redirtbl[redir_index].bits;
			else
				redir_content = ~0ULL;

			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}

	return injected;
}

static void update_handled_vectors(struct kvm_ioapic *ioapic)
{
	DECLARE_BITMAP(handled_vectors, 256);
	int i;

	memset(handled_vectors, 0, sizeof(handled_vectors));
	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
		__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	memcpy(ioapic->handled_vectors, handled_vectors,
	       sizeof(handled_vectors));
	smp_wmb();
}

void kvm_ioapic_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
					u64 *eoi_exit_bitmap)
{
	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	union kvm_ioapic_redirect_entry *e;
	struct kvm_lapic_irq irqe;
	int index;

	spin_lock(&ioapic->lock);
	/* traverse ioapic entry to set eoi exit bitmap*/
	for (index = 0; index < IOAPIC_NUM_PINS; index++) {
		e = &ioapic->redirtbl[index];
		if (!e->fields.mask &&
			(e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
			 kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
				 index))) {
			irqe.dest_id = e->fields.dest_id;
			irqe.vector = e->fields.vector;
			irqe.dest_mode = e->fields.dest_mode;
			irqe.delivery_mode = e->fields.delivery_mode << 8;
			kvm_calculate_eoi_exitmap(vcpu, &irqe, eoi_exit_bitmap);
		}
	}
	spin_unlock(&ioapic->lock);
}
EXPORT_SYMBOL_GPL(kvm_ioapic_calculate_eoi_exitmap);

void kvm_ioapic_make_eoibitmap_request(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	if (!kvm_apic_vid_enabled(kvm) || !ioapic)
		return;
	kvm_make_update_eoibitmap_request(kvm);
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;
	union kvm_ioapic_redirect_entry *e;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		e = &ioapic->redirtbl[index];
		mask_before = e->fields.mask;
		if (ioapic->ioregsel & 1) {
			e->bits &= 0xffffffff;
			e->bits |= (u64) val << 32;
		} else {
			e->bits &= ~0xffffffffULL;
			e->bits |= (u32) val;
			e->fields.remote_irr = 0;
		}
		update_handled_vectors(ioapic);
		mask_after = e->fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		kvm_ioapic_make_eoibitmap_request(ioapic->kvm);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest_id, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;

	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
		       int level)
{
	u32 old_irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret, irq_level;

	BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);

	spin_lock(&ioapic->lock);
	old_irr = ioapic->irr;
	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
					 irq_source_id, level);
	entry = ioapic->redirtbl[irq];
	irq_level ^= entry.fields.polarity;
	if (!irq_level) {
		ioapic->irr &= ~mask;
		ret = 1;
	} else {
		int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
		ioapic->irr |= mask;
		if ((edge && old_irr != ioapic->irr) ||
		    (!edge && !entry.fields.remote_irr))
			ret = ioapic_service(ioapic, irq);
		else
			ret = 0; /* report coalesced interrupt */
	}
	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	spin_unlock(&ioapic->lock);

	return ret;
}

void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
{
	int i;

	spin_lock(&ioapic->lock);
	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
		__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	spin_unlock(&ioapic->lock);
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
				     int trigger_mode)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];

		if (ent->fields.vector != vector)
			continue;

		/*
		 * We are dropping lock while calling ack notifiers because ack
		 * notifier callbacks for assigned devices call into IOAPIC
		 * recursively. Since remote_irr is cleared only after call
		 * to notifiers if the same vector will be delivered while lock
		 * is dropped it will be put into irr and will be delivered
		 * after ack notifier returns.
		 */
		spin_unlock(&ioapic->lock);
		kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
		spin_lock(&ioapic->lock);

		if (trigger_mode != IOAPIC_LEVEL_TRIG)
			continue;

		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << i)))
			ioapic_service(ioapic, i);
	}
}

bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	smp_rmb();
	return test_bit(vector, ioapic->handled_vectors);
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	spin_lock(&ioapic->lock);
	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
	spin_unlock(&ioapic->lock);
}

static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_ioapic, dev);
}

static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
{
	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			    void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 result;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	spin_unlock(&ioapic->lock);

	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
	return 0;
}

static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			     const void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 data;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */

	switch (len) {
	case 8:
	case 4:
		data = *(u32 *) val;
		break;
	case 2:
		data = *(u16 *) val;
		break;
	case 1:
		data = *(u8  *) val;
		break;
	default:
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return 0;
	}

	addr &= 0xff;
	spin_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data & 0xFF; /* 8-bit register */
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
	spin_unlock(&ioapic->lock);
	return 0;
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
	update_handled_vectors(ioapic);
}

static const struct kvm_io_device_ops ioapic_mmio_ops = {
	.read     = ioapic_mmio_read,
	.write    = ioapic_mmio_write,
};

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;
	int ret;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	spin_lock_init(&ioapic->lock);
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
	ioapic->kvm = kvm;
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
				      IOAPIC_MEM_LENGTH, &ioapic->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kvm->arch.vioapic = NULL;
		kfree(ioapic);
	}

	return ret;
}

void kvm_ioapic_destroy(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	if (ioapic) {
		kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
		kvm->arch.vioapic = NULL;
		kfree(ioapic);
	}
}

int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
	spin_unlock(&ioapic->lock);
	return 0;
}

int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	spin_lock(&ioapic->lock);
	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
	update_handled_vectors(ioapic);
	kvm_ioapic_make_eoibitmap_request(kvm);
	spin_unlock(&ioapic->lock);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
1fd4f2a5 ED	2	* Copyright (C) 2001 MandrakeSoft S.A.
221d059d	3	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
1fd4f2a5 ED	4	*
	5	* MandrakeSoft S.A.
	6	* 43, rue d'Aboukir
	7	* 75002 Paris - France
	8	* http://www.linux-mandrake.com/
	9	* http://www.mandrakesoft.com/
	10	*
	11	* This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU Lesser General Public
	13	* License as published by the Free Software Foundation; either
	14	* version 2 of the License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* Lesser General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU Lesser General Public
	22	* License along with this library; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*
	25	* Yunhong Jiang <yunhong.jiang@intel.com>
	26	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	27	* Based on Xen 3.1 code.
	28	*/
	29
edf88417	30	#include <linux/kvm_host.h>
1fd4f2a5 ED	31	#include <linux/kvm.h>
	32	#include <linux/mm.h>
	33	#include <linux/highmem.h>
	34	#include <linux/smp.h>
	35	#include <linux/hrtimer.h>
	36	#include <linux/io.h>
5a0e3ad6	37	#include <linux/slab.h>
c7c9c56c	38	#include <linux/export.h>
1fd4f2a5	39	#include <asm/processor.h>
1fd4f2a5 ED	40	#include <asm/page.h>
1fd4f2a5 ED	41	#include <asm/current.h>
1000ff8d	42	#include <trace/events/kvm.h>
82470196 ZX	43
	44	#include "ioapic.h"
	45	#include "lapic.h"
f5244726	46	#include "irq.h"
82470196	47
e25e3ed5 LV	48	#if 0
	49	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	50	#else
1fd4f2a5	51	#define ioapic_debug(fmt, arg...)
e25e3ed5	52	#endif
ff4b9df8	53	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	54
	55	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	56	unsigned long addr,
	57	unsigned long length)
	58	{
	59	unsigned long result = 0;
	60
	61	switch (ioapic->ioregsel) {
	62	case IOAPIC_REG_VERSION:
	63	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	64	\| (IOAPIC_VERSION_ID & 0xff));
	65	break;
	66
	67	case IOAPIC_REG_APIC_ID:
	68	case IOAPIC_REG_ARB_ID:
	69	result = ((ioapic->id & 0xf) << 24);
	70	break;
	71
	72	default:
	73	{
	74	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	75	u64 redir_content;
	76
a2c118bf AH	77	if (redir_index < IOAPIC_NUM_PINS)
	78	redir_content =
	79	ioapic->redirtbl[redir_index].bits;
	80	else
	81	redir_content = ~0ULL;
1fd4f2a5	82
1fd4f2a5 ED	83	result = (ioapic->ioregsel & 0x1) ?
	84	(redir_content >> 32) & 0xffffffff :
	85	redir_content & 0xffffffff;
	86	break;
	87	}
	88	}
	89
	90	return result;
	91	}
	92
4925663a	93	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	94	{
cf9e4e15	95	union kvm_ioapic_redirect_entry *pent;
4925663a	96	int injected = -1;
1fd4f2a5 ED	97
	98	pent = &ioapic->redirtbl[idx];
	99
	100	if (!pent->fields.mask) {
4925663a	101	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	102	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	103	pent->fields.remote_irr = 1;
1fd4f2a5 ED	104	}
4925663a GN	105
4925663a GN	106	return injected;
1fd4f2a5 ED	107	}
1fd4f2a5 ED	108
46a929bc AK	109	static void update_handled_vectors(struct kvm_ioapic *ioapic)
	110	{
	111	DECLARE_BITMAP(handled_vectors, 256);
	112	int i;
	113
	114	memset(handled_vectors, 0, sizeof(handled_vectors));
	115	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
	116	__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	117	memcpy(ioapic->handled_vectors, handled_vectors,
	118	sizeof(handled_vectors));
	119	smp_wmb();
	120	}
	121
c7c9c56c YZ	122	void kvm_ioapic_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
	123	u64 *eoi_exit_bitmap)
	124	{
	125	struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
	126	union kvm_ioapic_redirect_entry *e;
	127	struct kvm_lapic_irq irqe;
	128	int index;
	129
	130	spin_lock(&ioapic->lock);
	131	/* traverse ioapic entry to set eoi exit bitmap*/
	132	for (index = 0; index < IOAPIC_NUM_PINS; index++) {
	133	e = &ioapic->redirtbl[index];
	134	if (!e->fields.mask &&
	135	(e->fields.trig_mode == IOAPIC_LEVEL_TRIG \|\|
	136	kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC,
	137	index))) {
	138	irqe.dest_id = e->fields.dest_id;
	139	irqe.vector = e->fields.vector;
	140	irqe.dest_mode = e->fields.dest_mode;
	141	irqe.delivery_mode = e->fields.delivery_mode << 8;
	142	kvm_calculate_eoi_exitmap(vcpu, &irqe, eoi_exit_bitmap);
	143	}
	144	}
	145	spin_unlock(&ioapic->lock);
	146	}
	147	EXPORT_SYMBOL_GPL(kvm_ioapic_calculate_eoi_exitmap);
	148
	149	void kvm_ioapic_make_eoibitmap_request(struct kvm *kvm)
	150	{
	151	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	152
	153	if (!kvm_apic_vid_enabled(kvm) \|\| !ioapic)
	154	return;
	155	kvm_make_update_eoibitmap_request(kvm);
	156	}
	157
1fd4f2a5 ED	158	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	159	{
	160	unsigned index;
75858a84	161	bool mask_before, mask_after;
70f93dae	162	union kvm_ioapic_redirect_entry *e;
1fd4f2a5 ED	163
	164	switch (ioapic->ioregsel) {
	165	case IOAPIC_REG_VERSION:
	166	/* Writes are ignored. */
	167	break;
	168
	169	case IOAPIC_REG_APIC_ID:
	170	ioapic->id = (val >> 24) & 0xf;
	171	break;
	172
	173	case IOAPIC_REG_ARB_ID:
	174	break;
	175
	176	default:
	177	index = (ioapic->ioregsel - 0x10) >> 1;
	178
e25e3ed5	179	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	180	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	181	return;
70f93dae GN	182	e = &ioapic->redirtbl[index];
70f93dae GN	183	mask_before = e->fields.mask;
1fd4f2a5	184	if (ioapic->ioregsel & 1) {
70f93dae GN	185	e->bits &= 0xffffffff;
70f93dae GN	186	e->bits \|= (u64) val << 32;
1fd4f2a5	187	} else {
70f93dae GN	188	e->bits &= ~0xffffffffULL;
	189	e->bits \|= (u32) val;
	190	e->fields.remote_irr = 0;
1fd4f2a5	191	}
46a929bc	192	update_handled_vectors(ioapic);
70f93dae	193	mask_after = e->fields.mask;
75858a84	194	if (mask_before != mask_after)
4a994358	195	kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
70f93dae	196	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7	197	&& ioapic->irr & (1 << index))
1fd4f2a5	198	ioapic_service(ioapic, index);
c7c9c56c	199	kvm_ioapic_make_eoibitmap_request(ioapic->kvm);
1fd4f2a5 ED	200	break;
	201	}
	202	}
	203
a53c17d2 GN	204	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
a53c17d2 GN	205	{
58c2dde1 GN	206	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	207	struct kvm_lapic_irq irqe;
a53c17d2 GN	208
	209	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
	210	"vector=%x trig_mode=%x\n",
a38f84ca	211	entry->fields.dest_id, entry->fields.dest_mode,
58c2dde1 GN	212	entry->fields.delivery_mode, entry->fields.vector,
	213	entry->fields.trig_mode);
	214
	215	irqe.dest_id = entry->fields.dest_id;
	216	irqe.vector = entry->fields.vector;
	217	irqe.dest_mode = entry->fields.dest_mode;
	218	irqe.trig_mode = entry->fields.trig_mode;
	219	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	220	irqe.level = 1;
	221	irqe.shorthand = 0;
a53c17d2	222
58c2dde1	223	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
a53c17d2 GN	224	}
a53c17d2 GN	225
1a577b72 MT	226	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
1a577b72 MT	227	int level)
1fd4f2a5	228	{
07dc7263	229	u32 old_irr;
1fd4f2a5	230	u32 mask = 1 << irq;
cf9e4e15	231	union kvm_ioapic_redirect_entry entry;
28a6fdab MT	232	int ret, irq_level;
	233
	234	BUG_ON(irq < 0 \|\| irq >= IOAPIC_NUM_PINS);
1fd4f2a5	235
46a47b1e	236	spin_lock(&ioapic->lock);
07dc7263	237	old_irr = ioapic->irr;
28a6fdab MT	238	irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
	239	irq_source_id, level);
	240	entry = ioapic->redirtbl[irq];
	241	irq_level ^= entry.fields.polarity;
	242	if (!irq_level) {
	243	ioapic->irr &= ~mask;
	244	ret = 1;
	245	} else {
	246	int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
	247	ioapic->irr \|= mask;
	248	if ((edge && old_irr != ioapic->irr) \|\|
	249	(!edge && !entry.fields.remote_irr))
	250	ret = ioapic_service(ioapic, irq);
	251	else
	252	ret = 0; /* report coalesced interrupt */
1fd4f2a5	253	}
28a6fdab	254	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
46a47b1e	255	spin_unlock(&ioapic->lock);
eba0226b	256
4925663a	257	return ret;
1fd4f2a5 ED	258	}
1fd4f2a5 ED	259
1a577b72 MT	260	void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
	261	{
	262	int i;
	263
	264	spin_lock(&ioapic->lock);
	265	for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
	266	__clear_bit(irq_source_id, &ioapic->irq_states[i]);
	267	spin_unlock(&ioapic->lock);
	268	}
	269
eba0226b GN	270	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
eba0226b GN	271	int trigger_mode)
1fd4f2a5	272	{
eba0226b GN	273	int i;
	274
	275	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	276	union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
1fd4f2a5	277
eba0226b GN	278	if (ent->fields.vector != vector)
eba0226b GN	279	continue;
1fd4f2a5	280
eba0226b GN	281	/*
	282	* We are dropping lock while calling ack notifiers because ack
	283	* notifier callbacks for assigned devices call into IOAPIC
	284	* recursively. Since remote_irr is cleared only after call
	285	* to notifiers if the same vector will be delivered while lock
	286	* is dropped it will be put into irr and will be delivered
	287	* after ack notifier returns.
	288	*/
46a47b1e	289	spin_unlock(&ioapic->lock);
eba0226b	290	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
46a47b1e	291	spin_lock(&ioapic->lock);
eba0226b GN	292
	293	if (trigger_mode != IOAPIC_LEVEL_TRIG)
	294	continue;
f5244726	295
f5244726 MT	296	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
f5244726 MT	297	ent->fields.remote_irr = 0;
eba0226b GN	298	if (!ent->fields.mask && (ioapic->irr & (1 << i)))
eba0226b GN	299	ioapic_service(ioapic, i);
f5244726	300	}
1fd4f2a5 ED	301	}
1fd4f2a5 ED	302
a0c9a822 MT	303	bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
	304	{
	305	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	306	smp_rmb();
	307	return test_bit(vector, ioapic->handled_vectors);
	308	}
	309
f5244726	310	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	311	{
4fa6b9c5 AK	312	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
4fa6b9c5	313
46a47b1e	314	spin_lock(&ioapic->lock);
eba0226b	315	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
46a47b1e	316	spin_unlock(&ioapic->lock);
4fa6b9c5 AK	317	}
4fa6b9c5 AK	318
d76685c4 GH	319	static inline struct kvm_ioapic to_ioapic(struct kvm_io_device dev)
	320	{
	321	return container_of(dev, struct kvm_ioapic, dev);
	322	}
	323
bda9020e	324	static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
1fd4f2a5	325	{
1fd4f2a5 ED	326	return ((addr >= ioapic->base_address &&
	327	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	328	}
	329
bda9020e MT	330	static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	331	void *val)
1fd4f2a5	332	{
d76685c4	333	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	334	u32 result;
bda9020e MT	335	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	336	return -EOPNOTSUPP;
1fd4f2a5	337
e25e3ed5	338	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	339	ASSERT(!(addr & 0xf)); /* check alignment */
	340
	341	addr &= 0xff;
46a47b1e	342	spin_lock(&ioapic->lock);
1fd4f2a5 ED	343	switch (addr) {
	344	case IOAPIC_REG_SELECT:
	345	result = ioapic->ioregsel;
	346	break;
	347
	348	case IOAPIC_REG_WINDOW:
	349	result = ioapic_read_indirect(ioapic, addr, len);
	350	break;
	351
	352	default:
	353	result = 0;
	354	break;
	355	}
46a47b1e	356	spin_unlock(&ioapic->lock);
eba0226b	357
1fd4f2a5 ED	358	switch (len) {
	359	case 8:
	360	(u64 ) val = result;
	361	break;
	362	case 1:
	363	case 2:
	364	case 4:
	365	memcpy(val, (char *)&result, len);
	366	break;
	367	default:
	368	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	369	}
bda9020e	370	return 0;
1fd4f2a5 ED	371	}
1fd4f2a5 ED	372
bda9020e MT	373	static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	374	const void *val)
1fd4f2a5	375	{
d76685c4	376	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	377	u32 data;
bda9020e MT	378	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	379	return -EOPNOTSUPP;
1fd4f2a5	380
e25e3ed5 LV	381	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	382	(void*)addr, len, val);
1fd4f2a5	383	ASSERT(!(addr & 0xf)); /* check alignment */
60eead79	384
d77fe635 JS	385	switch (len) {
	386	case 8:
	387	case 4:
1fd4f2a5	388	data = (u32 ) val;
d77fe635 JS	389	break;
	390	case 2:
	391	data = (u16 ) val;
	392	break;
	393	case 1:
	394	data = (u8 ) val;
	395	break;
	396	default:
1fd4f2a5	397	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
eba0226b	398	return 0;
1fd4f2a5 ED	399	}
	400
	401	addr &= 0xff;
46a47b1e	402	spin_lock(&ioapic->lock);
1fd4f2a5 ED	403	switch (addr) {
1fd4f2a5 ED	404	case IOAPIC_REG_SELECT:
d77fe635	405	ioapic->ioregsel = data & 0xFF; /* 8-bit register */
1fd4f2a5 ED	406	break;
	407
	408	case IOAPIC_REG_WINDOW:
	409	ioapic_write_indirect(ioapic, data);
	410	break;
b1fd3d30 ZX	411	#ifdef CONFIG_IA64
b1fd3d30 ZX	412	case IOAPIC_REG_EOI:
eba0226b	413	__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	414	break;
b1fd3d30 ZX	415	#endif
1fd4f2a5 ED	416
	417	default:
	418	break;
	419	}
46a47b1e	420	spin_unlock(&ioapic->lock);
bda9020e	421	return 0;
1fd4f2a5 ED	422	}
1fd4f2a5 ED	423
8c392696 ED	424	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	425	{
	426	int i;
	427
	428	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	429	ioapic->redirtbl[i].fields.mask = 1;
	430	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	431	ioapic->ioregsel = 0;
	432	ioapic->irr = 0;
	433	ioapic->id = 0;
46a929bc	434	update_handled_vectors(ioapic);
8c392696 ED	435	}
8c392696 ED	436
d76685c4 GH	437	static const struct kvm_io_device_ops ioapic_mmio_ops = {
	438	.read = ioapic_mmio_read,
	439	.write = ioapic_mmio_write,
d76685c4 GH	440	};
d76685c4 GH	441
1fd4f2a5 ED	442	int kvm_ioapic_init(struct kvm *kvm)
	443	{
	444	struct kvm_ioapic *ioapic;
090b7aff	445	int ret;
1fd4f2a5 ED	446
	447	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	448	if (!ioapic)
	449	return -ENOMEM;
46a47b1e	450	spin_lock_init(&ioapic->lock);
d7deeeb0	451	kvm->arch.vioapic = ioapic;
8c392696	452	kvm_ioapic_reset(ioapic);
d76685c4	453	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
1fd4f2a5	454	ioapic->kvm = kvm;
79fac95e	455	mutex_lock(&kvm->slots_lock);
743eeb0b SL	456	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
743eeb0b SL	457	IOAPIC_MEM_LENGTH, &ioapic->dev);
79fac95e	458	mutex_unlock(&kvm->slots_lock);
1ae77bad WY	459	if (ret < 0) {
1ae77bad WY	460	kvm->arch.vioapic = NULL;
090b7aff	461	kfree(ioapic);
1ae77bad	462	}
090b7aff GH	463
090b7aff GH	464	return ret;
1fd4f2a5	465	}
75858a84	466
72bb2fcd WY	467	void kvm_ioapic_destroy(struct kvm *kvm)
	468	{
	469	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	470
	471	if (ioapic) {
	472	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
	473	kvm->arch.vioapic = NULL;
	474	kfree(ioapic);
	475	}
	476	}
	477
eba0226b GN	478	int kvm_get_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	479	{
	480	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	481	if (!ioapic)
	482	return -EINVAL;
	483
46a47b1e	484	spin_lock(&ioapic->lock);
eba0226b	485	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
46a47b1e	486	spin_unlock(&ioapic->lock);
eba0226b GN	487	return 0;
	488	}
	489
	490	int kvm_set_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	491	{
	492	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	493	if (!ioapic)
	494	return -EINVAL;
	495
46a47b1e	496	spin_lock(&ioapic->lock);
eba0226b	497	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
46a929bc	498	update_handled_vectors(ioapic);
c7c9c56c	499	kvm_ioapic_make_eoibitmap_request(kvm);
46a47b1e	500	spin_unlock(&ioapic->lock);
eba0226b GN	501	return 0;
eba0226b GN	502	}