Commit | Line | Data |
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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
29 | ||
edf88417 | 30 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
31 | #include <linux/kvm.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/hrtimer.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c7c9c56c | 38 | #include <linux/export.h> |
1fd4f2a5 | 39 | #include <asm/processor.h> |
1fd4f2a5 ED |
40 | #include <asm/page.h> |
41 | #include <asm/current.h> | |
1000ff8d | 42 | #include <trace/events/kvm.h> |
82470196 ZX |
43 | |
44 | #include "ioapic.h" | |
45 | #include "lapic.h" | |
f5244726 | 46 | #include "irq.h" |
82470196 | 47 | |
e25e3ed5 LV |
48 | #if 0 |
49 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
50 | #else | |
1fd4f2a5 | 51 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 52 | #endif |
0b10a1c8 | 53 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 54 | bool line_status); |
1fd4f2a5 ED |
55 | |
56 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
57 | unsigned long addr, | |
58 | unsigned long length) | |
59 | { | |
60 | unsigned long result = 0; | |
61 | ||
62 | switch (ioapic->ioregsel) { | |
63 | case IOAPIC_REG_VERSION: | |
64 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
65 | | (IOAPIC_VERSION_ID & 0xff)); | |
66 | break; | |
67 | ||
68 | case IOAPIC_REG_APIC_ID: | |
69 | case IOAPIC_REG_ARB_ID: | |
70 | result = ((ioapic->id & 0xf) << 24); | |
71 | break; | |
72 | ||
73 | default: | |
74 | { | |
75 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
76 | u64 redir_content; | |
77 | ||
a2c118bf AH |
78 | if (redir_index < IOAPIC_NUM_PINS) |
79 | redir_content = | |
80 | ioapic->redirtbl[redir_index].bits; | |
81 | else | |
82 | redir_content = ~0ULL; | |
1fd4f2a5 | 83 | |
1fd4f2a5 ED |
84 | result = (ioapic->ioregsel & 0x1) ? |
85 | (redir_content >> 32) & 0xffffffff : | |
86 | redir_content & 0xffffffff; | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | return result; | |
92 | } | |
93 | ||
10606919 YZ |
94 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
95 | { | |
96 | ioapic->rtc_status.pending_eoi = 0; | |
97 | bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS); | |
98 | } | |
99 | ||
100 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
101 | { | |
102 | bool new_val, old_val; | |
103 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
104 | union kvm_ioapic_redirect_entry *e; | |
105 | ||
106 | e = &ioapic->redirtbl[RTC_GSI]; | |
107 | if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id, | |
108 | e->fields.dest_mode)) | |
109 | return; | |
110 | ||
111 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
112 | old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
113 | ||
114 | if (new_val == old_val) | |
115 | return; | |
116 | ||
117 | if (new_val) { | |
118 | __set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
119 | ioapic->rtc_status.pending_eoi++; | |
120 | } else { | |
121 | __clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
122 | ioapic->rtc_status.pending_eoi--; | |
123 | } | |
124 | ||
125 | WARN_ON(ioapic->rtc_status.pending_eoi < 0); | |
126 | } | |
127 | ||
128 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
129 | { | |
130 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
131 | ||
132 | spin_lock(&ioapic->lock); | |
133 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
134 | spin_unlock(&ioapic->lock); | |
135 | } | |
136 | ||
137 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
138 | { | |
139 | struct kvm_vcpu *vcpu; | |
140 | int i; | |
141 | ||
142 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
143 | return; | |
144 | ||
145 | rtc_irq_eoi_tracking_reset(ioapic); | |
146 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
147 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
148 | } | |
149 | ||
2c2bf011 YZ |
150 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu) |
151 | { | |
152 | if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map)) | |
153 | --ioapic->rtc_status.pending_eoi; | |
154 | ||
155 | WARN_ON(ioapic->rtc_status.pending_eoi < 0); | |
156 | } | |
157 | ||
158 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
159 | { | |
160 | if (ioapic->rtc_status.pending_eoi > 0) | |
161 | return true; /* coalesced */ | |
162 | ||
163 | return false; | |
164 | } | |
165 | ||
44847dea PB |
166 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
167 | int irq_level, bool line_status) | |
168 | { | |
169 | union kvm_ioapic_redirect_entry entry; | |
170 | u32 mask = 1 << irq; | |
171 | u32 old_irr; | |
172 | int edge, ret; | |
173 | ||
174 | entry = ioapic->redirtbl[irq]; | |
175 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
176 | ||
177 | if (!irq_level) { | |
178 | ioapic->irr &= ~mask; | |
179 | ret = 1; | |
180 | goto out; | |
181 | } | |
182 | ||
183 | /* | |
184 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
185 | * this only happens if a previous edge has not been delivered due | |
186 | * do masking. For level interrupts, the remote_irr field tells | |
187 | * us if the interrupt is waiting for an EOI. | |
188 | * | |
189 | * RTC is special: it is edge-triggered, but userspace likes to know | |
190 | * if it has been already ack-ed via EOI because coalesced RTC | |
191 | * interrupts lead to time drift in Windows guests. So we track | |
192 | * EOI manually for the RTC interrupt. | |
193 | */ | |
194 | if (irq == RTC_GSI && line_status && | |
195 | rtc_irq_check_coalesced(ioapic)) { | |
196 | ret = 0; | |
197 | goto out; | |
198 | } | |
199 | ||
200 | old_irr = ioapic->irr; | |
201 | ioapic->irr |= mask; | |
202 | if ((edge && old_irr == ioapic->irr) || | |
203 | (!edge && entry.fields.remote_irr)) { | |
204 | ret = 0; | |
205 | goto out; | |
206 | } | |
207 | ||
208 | ret = ioapic_service(ioapic, irq, line_status); | |
209 | ||
210 | out: | |
211 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
212 | return ret; | |
213 | } | |
214 | ||
46a929bc AK |
215 | static void update_handled_vectors(struct kvm_ioapic *ioapic) |
216 | { | |
217 | DECLARE_BITMAP(handled_vectors, 256); | |
218 | int i; | |
219 | ||
220 | memset(handled_vectors, 0, sizeof(handled_vectors)); | |
221 | for (i = 0; i < IOAPIC_NUM_PINS; ++i) | |
222 | __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors); | |
223 | memcpy(ioapic->handled_vectors, handled_vectors, | |
224 | sizeof(handled_vectors)); | |
225 | smp_wmb(); | |
226 | } | |
227 | ||
cf9e65b7 YZ |
228 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap, |
229 | u32 *tmr) | |
c7c9c56c YZ |
230 | { |
231 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
232 | union kvm_ioapic_redirect_entry *e; | |
c7c9c56c YZ |
233 | int index; |
234 | ||
235 | spin_lock(&ioapic->lock); | |
c7c9c56c YZ |
236 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
237 | e = &ioapic->redirtbl[index]; | |
238 | if (!e->fields.mask && | |
239 | (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || | |
240 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, | |
f3bff631 | 241 | index) || index == RTC_GSI)) { |
44944d4d | 242 | if (kvm_apic_match_dest(vcpu, NULL, 0, |
cf9e65b7 YZ |
243 | e->fields.dest_id, e->fields.dest_mode)) { |
244 | __set_bit(e->fields.vector, | |
245 | (unsigned long *)eoi_exit_bitmap); | |
246 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
247 | __set_bit(e->fields.vector, | |
248 | (unsigned long *)tmr); | |
249 | } | |
c7c9c56c YZ |
250 | } |
251 | } | |
252 | spin_unlock(&ioapic->lock); | |
253 | } | |
c7c9c56c | 254 | |
3d81bc7e YZ |
255 | #ifdef CONFIG_X86 |
256 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) | |
c7c9c56c YZ |
257 | { |
258 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
259 | ||
3d81bc7e | 260 | if (!ioapic) |
c7c9c56c | 261 | return; |
3d81bc7e | 262 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c | 263 | } |
3d81bc7e YZ |
264 | #else |
265 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) | |
266 | { | |
267 | return; | |
268 | } | |
269 | #endif | |
c7c9c56c | 270 | |
1fd4f2a5 ED |
271 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
272 | { | |
273 | unsigned index; | |
75858a84 | 274 | bool mask_before, mask_after; |
70f93dae | 275 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
276 | |
277 | switch (ioapic->ioregsel) { | |
278 | case IOAPIC_REG_VERSION: | |
279 | /* Writes are ignored. */ | |
280 | break; | |
281 | ||
282 | case IOAPIC_REG_APIC_ID: | |
283 | ioapic->id = (val >> 24) & 0xf; | |
284 | break; | |
285 | ||
286 | case IOAPIC_REG_ARB_ID: | |
287 | break; | |
288 | ||
289 | default: | |
290 | index = (ioapic->ioregsel - 0x10) >> 1; | |
291 | ||
e25e3ed5 | 292 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
293 | if (index >= IOAPIC_NUM_PINS) |
294 | return; | |
70f93dae GN |
295 | e = &ioapic->redirtbl[index]; |
296 | mask_before = e->fields.mask; | |
1fd4f2a5 | 297 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
298 | e->bits &= 0xffffffff; |
299 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 300 | } else { |
70f93dae GN |
301 | e->bits &= ~0xffffffffULL; |
302 | e->bits |= (u32) val; | |
303 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 304 | } |
46a929bc | 305 | update_handled_vectors(ioapic); |
70f93dae | 306 | mask_after = e->fields.mask; |
75858a84 | 307 | if (mask_before != mask_after) |
4a994358 | 308 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
70f93dae | 309 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 310 | && ioapic->irr & (1 << index)) |
aa2fbe6d | 311 | ioapic_service(ioapic, index, false); |
3d81bc7e | 312 | kvm_vcpu_request_scan_ioapic(ioapic->kvm); |
1fd4f2a5 ED |
313 | break; |
314 | } | |
315 | } | |
316 | ||
0b10a1c8 | 317 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 318 | { |
58c2dde1 GN |
319 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
320 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 321 | int ret; |
a53c17d2 | 322 | |
0b10a1c8 PB |
323 | if (entry->fields.mask) |
324 | return -1; | |
325 | ||
a53c17d2 GN |
326 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " |
327 | "vector=%x trig_mode=%x\n", | |
a38f84ca | 328 | entry->fields.dest_id, entry->fields.dest_mode, |
58c2dde1 GN |
329 | entry->fields.delivery_mode, entry->fields.vector, |
330 | entry->fields.trig_mode); | |
331 | ||
332 | irqe.dest_id = entry->fields.dest_id; | |
333 | irqe.vector = entry->fields.vector; | |
334 | irqe.dest_mode = entry->fields.dest_mode; | |
335 | irqe.trig_mode = entry->fields.trig_mode; | |
336 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
337 | irqe.level = 1; | |
338 | irqe.shorthand = 0; | |
a53c17d2 | 339 | |
0bc830b0 PB |
340 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
341 | ioapic->irr &= ~(1 << irq); | |
342 | ||
2c2bf011 YZ |
343 | if (irq == RTC_GSI && line_status) { |
344 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); | |
345 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
346 | ioapic->rtc_status.dest_map); | |
347 | ioapic->rtc_status.pending_eoi = ret; | |
348 | } else | |
349 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
350 | ||
0b10a1c8 PB |
351 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
352 | entry->fields.remote_irr = 1; | |
353 | ||
2c2bf011 | 354 | return ret; |
a53c17d2 GN |
355 | } |
356 | ||
1a577b72 | 357 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 358 | int level, bool line_status) |
1fd4f2a5 | 359 | { |
28a6fdab MT |
360 | int ret, irq_level; |
361 | ||
362 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 363 | |
46a47b1e | 364 | spin_lock(&ioapic->lock); |
28a6fdab MT |
365 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
366 | irq_source_id, level); | |
44847dea | 367 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 368 | |
46a47b1e | 369 | spin_unlock(&ioapic->lock); |
eba0226b | 370 | |
4925663a | 371 | return ret; |
1fd4f2a5 ED |
372 | } |
373 | ||
1a577b72 MT |
374 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
375 | { | |
376 | int i; | |
377 | ||
378 | spin_lock(&ioapic->lock); | |
379 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
380 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
381 | spin_unlock(&ioapic->lock); | |
382 | } | |
383 | ||
1fcc7890 YZ |
384 | static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, |
385 | struct kvm_ioapic *ioapic, int vector, int trigger_mode) | |
1fd4f2a5 | 386 | { |
eba0226b GN |
387 | int i; |
388 | ||
389 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
390 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 391 | |
eba0226b GN |
392 | if (ent->fields.vector != vector) |
393 | continue; | |
1fd4f2a5 | 394 | |
2c2bf011 YZ |
395 | if (i == RTC_GSI) |
396 | rtc_irq_eoi(ioapic, vcpu); | |
eba0226b GN |
397 | /* |
398 | * We are dropping lock while calling ack notifiers because ack | |
399 | * notifier callbacks for assigned devices call into IOAPIC | |
400 | * recursively. Since remote_irr is cleared only after call | |
401 | * to notifiers if the same vector will be delivered while lock | |
402 | * is dropped it will be put into irr and will be delivered | |
403 | * after ack notifier returns. | |
404 | */ | |
46a47b1e | 405 | spin_unlock(&ioapic->lock); |
eba0226b | 406 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 407 | spin_lock(&ioapic->lock); |
eba0226b GN |
408 | |
409 | if (trigger_mode != IOAPIC_LEVEL_TRIG) | |
410 | continue; | |
f5244726 | 411 | |
f5244726 MT |
412 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
413 | ent->fields.remote_irr = 0; | |
0b10a1c8 | 414 | if (ioapic->irr & (1 << i)) |
aa2fbe6d | 415 | ioapic_service(ioapic, i, false); |
f5244726 | 416 | } |
1fd4f2a5 ED |
417 | } |
418 | ||
a0c9a822 MT |
419 | bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector) |
420 | { | |
421 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
422 | smp_rmb(); | |
423 | return test_bit(vector, ioapic->handled_vectors); | |
424 | } | |
425 | ||
1fcc7890 | 426 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 427 | { |
1fcc7890 | 428 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 429 | |
46a47b1e | 430 | spin_lock(&ioapic->lock); |
1fcc7890 | 431 | __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode); |
46a47b1e | 432 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
433 | } |
434 | ||
d76685c4 GH |
435 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
436 | { | |
437 | return container_of(dev, struct kvm_ioapic, dev); | |
438 | } | |
439 | ||
bda9020e | 440 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 441 | { |
1fd4f2a5 ED |
442 | return ((addr >= ioapic->base_address && |
443 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
444 | } | |
445 | ||
bda9020e MT |
446 | static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, |
447 | void *val) | |
1fd4f2a5 | 448 | { |
d76685c4 | 449 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 450 | u32 result; |
bda9020e MT |
451 | if (!ioapic_in_range(ioapic, addr)) |
452 | return -EOPNOTSUPP; | |
1fd4f2a5 | 453 | |
e25e3ed5 | 454 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
455 | ASSERT(!(addr & 0xf)); /* check alignment */ |
456 | ||
457 | addr &= 0xff; | |
46a47b1e | 458 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
459 | switch (addr) { |
460 | case IOAPIC_REG_SELECT: | |
461 | result = ioapic->ioregsel; | |
462 | break; | |
463 | ||
464 | case IOAPIC_REG_WINDOW: | |
465 | result = ioapic_read_indirect(ioapic, addr, len); | |
466 | break; | |
467 | ||
468 | default: | |
469 | result = 0; | |
470 | break; | |
471 | } | |
46a47b1e | 472 | spin_unlock(&ioapic->lock); |
eba0226b | 473 | |
1fd4f2a5 ED |
474 | switch (len) { |
475 | case 8: | |
476 | *(u64 *) val = result; | |
477 | break; | |
478 | case 1: | |
479 | case 2: | |
480 | case 4: | |
481 | memcpy(val, (char *)&result, len); | |
482 | break; | |
483 | default: | |
484 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
485 | } | |
bda9020e | 486 | return 0; |
1fd4f2a5 ED |
487 | } |
488 | ||
bda9020e MT |
489 | static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, |
490 | const void *val) | |
1fd4f2a5 | 491 | { |
d76685c4 | 492 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 493 | u32 data; |
bda9020e MT |
494 | if (!ioapic_in_range(ioapic, addr)) |
495 | return -EOPNOTSUPP; | |
1fd4f2a5 | 496 | |
e25e3ed5 LV |
497 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
498 | (void*)addr, len, val); | |
1fd4f2a5 | 499 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 500 | |
d77fe635 JS |
501 | switch (len) { |
502 | case 8: | |
503 | case 4: | |
1fd4f2a5 | 504 | data = *(u32 *) val; |
d77fe635 JS |
505 | break; |
506 | case 2: | |
507 | data = *(u16 *) val; | |
508 | break; | |
509 | case 1: | |
510 | data = *(u8 *) val; | |
511 | break; | |
512 | default: | |
1fd4f2a5 | 513 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 514 | return 0; |
1fd4f2a5 ED |
515 | } |
516 | ||
517 | addr &= 0xff; | |
46a47b1e | 518 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
519 | switch (addr) { |
520 | case IOAPIC_REG_SELECT: | |
d77fe635 | 521 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
522 | break; |
523 | ||
524 | case IOAPIC_REG_WINDOW: | |
525 | ioapic_write_indirect(ioapic, data); | |
526 | break; | |
b1fd3d30 ZX |
527 | #ifdef CONFIG_IA64 |
528 | case IOAPIC_REG_EOI: | |
1fcc7890 | 529 | __kvm_ioapic_update_eoi(NULL, ioapic, data, IOAPIC_LEVEL_TRIG); |
b1fd3d30 ZX |
530 | break; |
531 | #endif | |
1fd4f2a5 ED |
532 | |
533 | default: | |
534 | break; | |
535 | } | |
46a47b1e | 536 | spin_unlock(&ioapic->lock); |
bda9020e | 537 | return 0; |
1fd4f2a5 ED |
538 | } |
539 | ||
7940876e | 540 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
541 | { |
542 | int i; | |
543 | ||
544 | for (i = 0; i < IOAPIC_NUM_PINS; i++) | |
545 | ioapic->redirtbl[i].fields.mask = 1; | |
546 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
547 | ioapic->ioregsel = 0; | |
548 | ioapic->irr = 0; | |
549 | ioapic->id = 0; | |
10606919 | 550 | rtc_irq_eoi_tracking_reset(ioapic); |
46a929bc | 551 | update_handled_vectors(ioapic); |
8c392696 ED |
552 | } |
553 | ||
d76685c4 GH |
554 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
555 | .read = ioapic_mmio_read, | |
556 | .write = ioapic_mmio_write, | |
d76685c4 GH |
557 | }; |
558 | ||
1fd4f2a5 ED |
559 | int kvm_ioapic_init(struct kvm *kvm) |
560 | { | |
561 | struct kvm_ioapic *ioapic; | |
090b7aff | 562 | int ret; |
1fd4f2a5 ED |
563 | |
564 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
565 | if (!ioapic) | |
566 | return -ENOMEM; | |
46a47b1e | 567 | spin_lock_init(&ioapic->lock); |
d7deeeb0 | 568 | kvm->arch.vioapic = ioapic; |
8c392696 | 569 | kvm_ioapic_reset(ioapic); |
d76685c4 | 570 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 571 | ioapic->kvm = kvm; |
79fac95e | 572 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
573 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
574 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 575 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
576 | if (ret < 0) { |
577 | kvm->arch.vioapic = NULL; | |
090b7aff | 578 | kfree(ioapic); |
1ae77bad | 579 | } |
090b7aff GH |
580 | |
581 | return ret; | |
1fd4f2a5 | 582 | } |
75858a84 | 583 | |
72bb2fcd WY |
584 | void kvm_ioapic_destroy(struct kvm *kvm) |
585 | { | |
586 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
587 | ||
588 | if (ioapic) { | |
589 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); | |
590 | kvm->arch.vioapic = NULL; | |
591 | kfree(ioapic); | |
592 | } | |
593 | } | |
594 | ||
eba0226b GN |
595 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
596 | { | |
597 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
598 | if (!ioapic) | |
599 | return -EINVAL; | |
600 | ||
46a47b1e | 601 | spin_lock(&ioapic->lock); |
eba0226b | 602 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
46a47b1e | 603 | spin_unlock(&ioapic->lock); |
eba0226b GN |
604 | return 0; |
605 | } | |
606 | ||
607 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
608 | { | |
609 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
610 | if (!ioapic) | |
611 | return -EINVAL; | |
612 | ||
46a47b1e | 613 | spin_lock(&ioapic->lock); |
eba0226b | 614 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
46a929bc | 615 | update_handled_vectors(ioapic); |
3d81bc7e | 616 | kvm_vcpu_request_scan_ioapic(kvm); |
10606919 | 617 | kvm_rtc_eoi_tracking_restore_all(ioapic); |
46a47b1e | 618 | spin_unlock(&ioapic->lock); |
eba0226b GN |
619 | return 0; |
620 | } |