[deliverable/linux.git] / virt / kvm / ioapic.c

/*
 *  Copyright (C) 2001  MandrakeSoft S.A.
 *
 *    MandrakeSoft S.A.
 *    43, rue d'Aboukir
 *    75002 Paris - France
 *    http://www.linux-mandrake.com/
 *    http://www.mandrakesoft.com/
 *
 *  This library is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU Lesser General Public
 *  License as published by the Free Software Foundation; either
 *  version 2 of the License, or (at your option) any later version.
 *
 *  This library is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  Lesser General Public License for more details.
 *
 *  You should have received a copy of the GNU Lesser General Public
 *  License along with this library; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Yunhong Jiang <yunhong.jiang@intel.com>
 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
 *  Based on Xen 3.1 code.
 */

#include <linux/kvm_host.h>
#include <linux/kvm.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/smp.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/current.h>
#include <trace/events/kvm.h>

#include "ioapic.h"
#include "lapic.h"
#include "irq.h"

#if 0
#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
#else
#define ioapic_debug(fmt, arg...)
#endif
static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);

static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
					  unsigned long addr,
					  unsigned long length)
{
	unsigned long result = 0;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
			  | (IOAPIC_VERSION_ID & 0xff));
		break;

	case IOAPIC_REG_APIC_ID:
	case IOAPIC_REG_ARB_ID:
		result = ((ioapic->id & 0xf) << 24);
		break;

	default:
		{
			u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
			u64 redir_content;

			ASSERT(redir_index < IOAPIC_NUM_PINS);

			redir_content = ioapic->redirtbl[redir_index].bits;
			result = (ioapic->ioregsel & 0x1) ?
			    (redir_content >> 32) & 0xffffffff :
			    redir_content & 0xffffffff;
			break;
		}
	}

	return result;
}

static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
{
	union kvm_ioapic_redirect_entry *pent;
	int injected = -1;

	pent = &ioapic->redirtbl[idx];

	if (!pent->fields.mask) {
		injected = ioapic_deliver(ioapic, idx);
		if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
			pent->fields.remote_irr = 1;
	}

	return injected;
}

static void update_handled_vectors(struct kvm_ioapic *ioapic)
{
	DECLARE_BITMAP(handled_vectors, 256);
	int i;

	memset(handled_vectors, 0, sizeof(handled_vectors));
	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
		__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	memcpy(ioapic->handled_vectors, handled_vectors,
	       sizeof(handled_vectors));
	smp_wmb();
}

static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
{
	unsigned index;
	bool mask_before, mask_after;
	union kvm_ioapic_redirect_entry *e;

	switch (ioapic->ioregsel) {
	case IOAPIC_REG_VERSION:
		/* Writes are ignored. */
		break;

	case IOAPIC_REG_APIC_ID:
		ioapic->id = (val >> 24) & 0xf;
		break;

	case IOAPIC_REG_ARB_ID:
		break;

	default:
		index = (ioapic->ioregsel - 0x10) >> 1;

		ioapic_debug("change redir index %x val %x\n", index, val);
		if (index >= IOAPIC_NUM_PINS)
			return;
		e = &ioapic->redirtbl[index];
		mask_before = e->fields.mask;
		if (ioapic->ioregsel & 1) {
			e->bits &= 0xffffffff;
			e->bits |= (u64) val << 32;
		} else {
			e->bits &= ~0xffffffffULL;
			e->bits |= (u32) val;
			e->fields.remote_irr = 0;
		}
		update_handled_vectors(ioapic);
		mask_after = e->fields.mask;
		if (mask_before != mask_after)
			kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
		if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
		    && ioapic->irr & (1 << index))
			ioapic_service(ioapic, index);
		break;
	}
}

static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
{
	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
	struct kvm_lapic_irq irqe;

	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
		     "vector=%x trig_mode=%x\n",
		     entry->fields.dest, entry->fields.dest_mode,
		     entry->fields.delivery_mode, entry->fields.vector,
		     entry->fields.trig_mode);

	irqe.dest_id = entry->fields.dest_id;
	irqe.vector = entry->fields.vector;
	irqe.dest_mode = entry->fields.dest_mode;
	irqe.trig_mode = entry->fields.trig_mode;
	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	irqe.level = 1;
	irqe.shorthand = 0;

#ifdef CONFIG_X86
	/* Always delivery PIT interrupt to vcpu 0 */
	if (irq == 0) {
		irqe.dest_mode = 0; /* Physical mode. */
		/* need to read apic_id from apic regiest since
		 * it can be rewritten */
		irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
	}
#endif
	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
}

int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
{
	u32 old_irr = ioapic->irr;
	u32 mask = 1 << irq;
	union kvm_ioapic_redirect_entry entry;
	int ret = 1;

	mutex_lock(&ioapic->lock);
	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
		entry = ioapic->redirtbl[irq];
		level ^= entry.fields.polarity;
		if (!level)
			ioapic->irr &= ~mask;
		else {
			int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
			ioapic->irr |= mask;
			if ((edge && old_irr != ioapic->irr) ||
			    (!edge && !entry.fields.remote_irr))
				ret = ioapic_service(ioapic, irq);
			else
				ret = 0; /* report coalesced interrupt */
		}
		trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
	}
	mutex_unlock(&ioapic->lock);

	return ret;
}

static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
				     int trigger_mode)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
		union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];

		if (ent->fields.vector != vector)
			continue;

		/*
		 * We are dropping lock while calling ack notifiers because ack
		 * notifier callbacks for assigned devices call into IOAPIC
		 * recursively. Since remote_irr is cleared only after call
		 * to notifiers if the same vector will be delivered while lock
		 * is dropped it will be put into irr and will be delivered
		 * after ack notifier returns.
		 */
		mutex_unlock(&ioapic->lock);
		kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
		mutex_lock(&ioapic->lock);

		if (trigger_mode != IOAPIC_LEVEL_TRIG)
			continue;

		ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
		ent->fields.remote_irr = 0;
		if (!ent->fields.mask && (ioapic->irr & (1 << i)))
			ioapic_service(ioapic, i);
	}
}

void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;

	smp_rmb();
	if (!test_bit(vector, ioapic->handled_vectors))
		return;
	mutex_lock(&ioapic->lock);
	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
	mutex_unlock(&ioapic->lock);
}

static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_ioapic, dev);
}

static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
{
	return ((addr >= ioapic->base_address &&
		 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
}

static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
			    void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 result;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("addr %lx\n", (unsigned long)addr);
	ASSERT(!(addr & 0xf));	/* check alignment */

	addr &= 0xff;
	mutex_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		result = ioapic->ioregsel;
		break;

	case IOAPIC_REG_WINDOW:
		result = ioapic_read_indirect(ioapic, addr, len);
		break;

	default:
		result = 0;
		break;
	}
	mutex_unlock(&ioapic->lock);

	switch (len) {
	case 8:
		*(u64 *) val = result;
		break;
	case 1:
	case 2:
	case 4:
		memcpy(val, (char *)&result, len);
		break;
	default:
		printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	}
	return 0;
}

static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
			     const void *val)
{
	struct kvm_ioapic *ioapic = to_ioapic(this);
	u32 data;
	if (!ioapic_in_range(ioapic, addr))
		return -EOPNOTSUPP;

	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
		     (void*)addr, len, val);
	ASSERT(!(addr & 0xf));	/* check alignment */

	if (len == 4 || len == 8)
		data = *(u32 *) val;
	else {
		printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
		return 0;
	}

	addr &= 0xff;
	mutex_lock(&ioapic->lock);
	switch (addr) {
	case IOAPIC_REG_SELECT:
		ioapic->ioregsel = data;
		break;

	case IOAPIC_REG_WINDOW:
		ioapic_write_indirect(ioapic, data);
		break;
#ifdef	CONFIG_IA64
	case IOAPIC_REG_EOI:
		__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
		break;
#endif

	default:
		break;
	}
	mutex_unlock(&ioapic->lock);
	return 0;
}

void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
{
	int i;

	for (i = 0; i < IOAPIC_NUM_PINS; i++)
		ioapic->redirtbl[i].fields.mask = 1;
	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	ioapic->ioregsel = 0;
	ioapic->irr = 0;
	ioapic->id = 0;
	update_handled_vectors(ioapic);
}

static const struct kvm_io_device_ops ioapic_mmio_ops = {
	.read     = ioapic_mmio_read,
	.write    = ioapic_mmio_write,
};

int kvm_ioapic_init(struct kvm *kvm)
{
	struct kvm_ioapic *ioapic;
	int ret;

	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	if (!ioapic)
		return -ENOMEM;
	mutex_init(&ioapic->lock);
	kvm->arch.vioapic = ioapic;
	kvm_ioapic_reset(ioapic);
	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
	ioapic->kvm = kvm;
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0)
		kfree(ioapic);

	return ret;
}

int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	mutex_lock(&ioapic->lock);
	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
	mutex_unlock(&ioapic->lock);
	return 0;
}

int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
{
	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	if (!ioapic)
		return -EINVAL;

	mutex_lock(&ioapic->lock);
	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
	update_handled_vectors(ioapic);
	mutex_unlock(&ioapic->lock);
	return 0;
}
Commit	Line	Data
1fd4f2a5 ED	1	/*
	2	* Copyright (C) 2001 MandrakeSoft S.A.
	3	*
	4	* MandrakeSoft S.A.
	5	* 43, rue d'Aboukir
	6	* 75002 Paris - France
	7	* http://www.linux-mandrake.com/
	8	* http://www.mandrakesoft.com/
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Yunhong Jiang <yunhong.jiang@intel.com>
	25	* Yaozu (Eddie) Dong <eddie.dong@intel.com>
	26	* Based on Xen 3.1 code.
	27	*/
	28
edf88417	29	#include <linux/kvm_host.h>
1fd4f2a5 ED	30	#include <linux/kvm.h>
	31	#include <linux/mm.h>
	32	#include <linux/highmem.h>
	33	#include <linux/smp.h>
	34	#include <linux/hrtimer.h>
	35	#include <linux/io.h>
	36	#include <asm/processor.h>
1fd4f2a5 ED	37	#include <asm/page.h>
1fd4f2a5 ED	38	#include <asm/current.h>
1000ff8d	39	#include <trace/events/kvm.h>
82470196 ZX	40
	41	#include "ioapic.h"
	42	#include "lapic.h"
f5244726	43	#include "irq.h"
82470196	44
e25e3ed5 LV	45	#if 0
	46	#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
	47	#else
1fd4f2a5	48	#define ioapic_debug(fmt, arg...)
e25e3ed5	49	#endif
ff4b9df8	50	static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
1fd4f2a5 ED	51
	52	static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
	53	unsigned long addr,
	54	unsigned long length)
	55	{
	56	unsigned long result = 0;
	57
	58	switch (ioapic->ioregsel) {
	59	case IOAPIC_REG_VERSION:
	60	result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
	61	\| (IOAPIC_VERSION_ID & 0xff));
	62	break;
	63
	64	case IOAPIC_REG_APIC_ID:
	65	case IOAPIC_REG_ARB_ID:
	66	result = ((ioapic->id & 0xf) << 24);
	67	break;
	68
	69	default:
	70	{
	71	u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
	72	u64 redir_content;
	73
	74	ASSERT(redir_index < IOAPIC_NUM_PINS);
	75
	76	redir_content = ioapic->redirtbl[redir_index].bits;
	77	result = (ioapic->ioregsel & 0x1) ?
	78	(redir_content >> 32) & 0xffffffff :
	79	redir_content & 0xffffffff;
	80	break;
	81	}
	82	}
	83
	84	return result;
	85	}
	86
4925663a	87	static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
1fd4f2a5	88	{
cf9e4e15	89	union kvm_ioapic_redirect_entry *pent;
4925663a	90	int injected = -1;
1fd4f2a5 ED	91
	92	pent = &ioapic->redirtbl[idx];
	93
	94	if (!pent->fields.mask) {
4925663a	95	injected = ioapic_deliver(ioapic, idx);
ff4b9df8	96	if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
1fd4f2a5 ED	97	pent->fields.remote_irr = 1;
1fd4f2a5 ED	98	}
4925663a GN	99
4925663a GN	100	return injected;
1fd4f2a5 ED	101	}
1fd4f2a5 ED	102
46a929bc AK	103	static void update_handled_vectors(struct kvm_ioapic *ioapic)
	104	{
	105	DECLARE_BITMAP(handled_vectors, 256);
	106	int i;
	107
	108	memset(handled_vectors, 0, sizeof(handled_vectors));
	109	for (i = 0; i < IOAPIC_NUM_PINS; ++i)
	110	__set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
	111	memcpy(ioapic->handled_vectors, handled_vectors,
	112	sizeof(handled_vectors));
	113	smp_wmb();
	114	}
	115
1fd4f2a5 ED	116	static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
	117	{
	118	unsigned index;
75858a84	119	bool mask_before, mask_after;
70f93dae	120	union kvm_ioapic_redirect_entry *e;
1fd4f2a5 ED	121
	122	switch (ioapic->ioregsel) {
	123	case IOAPIC_REG_VERSION:
	124	/* Writes are ignored. */
	125	break;
	126
	127	case IOAPIC_REG_APIC_ID:
	128	ioapic->id = (val >> 24) & 0xf;
	129	break;
	130
	131	case IOAPIC_REG_ARB_ID:
	132	break;
	133
	134	default:
	135	index = (ioapic->ioregsel - 0x10) >> 1;
	136
e25e3ed5	137	ioapic_debug("change redir index %x val %x\n", index, val);
1fd4f2a5 ED	138	if (index >= IOAPIC_NUM_PINS)
1fd4f2a5 ED	139	return;
70f93dae GN	140	e = &ioapic->redirtbl[index];
70f93dae GN	141	mask_before = e->fields.mask;
1fd4f2a5	142	if (ioapic->ioregsel & 1) {
70f93dae GN	143	e->bits &= 0xffffffff;
70f93dae GN	144	e->bits \|= (u64) val << 32;
1fd4f2a5	145	} else {
70f93dae GN	146	e->bits &= ~0xffffffffULL;
	147	e->bits \|= (u32) val;
	148	e->fields.remote_irr = 0;
1fd4f2a5	149	}
46a929bc	150	update_handled_vectors(ioapic);
70f93dae	151	mask_after = e->fields.mask;
75858a84 AK	152	if (mask_before != mask_after)
75858a84 AK	153	kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
70f93dae	154	if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
b4a2f5e7	155	&& ioapic->irr & (1 << index))
1fd4f2a5 ED	156	ioapic_service(ioapic, index);
	157	break;
	158	}
	159	}
	160
a53c17d2 GN	161	static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
a53c17d2 GN	162	{
58c2dde1 GN	163	union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
58c2dde1 GN	164	struct kvm_lapic_irq irqe;
a53c17d2 GN	165
	166	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
	167	"vector=%x trig_mode=%x\n",
58c2dde1 GN	168	entry->fields.dest, entry->fields.dest_mode,
	169	entry->fields.delivery_mode, entry->fields.vector,
	170	entry->fields.trig_mode);
	171
	172	irqe.dest_id = entry->fields.dest_id;
	173	irqe.vector = entry->fields.vector;
	174	irqe.dest_mode = entry->fields.dest_mode;
	175	irqe.trig_mode = entry->fields.trig_mode;
	176	irqe.delivery_mode = entry->fields.delivery_mode << 8;
	177	irqe.level = 1;
	178	irqe.shorthand = 0;
a53c17d2 GN	179
	180	#ifdef CONFIG_X86
	181	/* Always delivery PIT interrupt to vcpu 0 */
	182	if (irq == 0) {
58c2dde1	183	irqe.dest_mode = 0; /* Physical mode. */
c5af89b6 GN	184	/* need to read apic_id from apic regiest since
	185	* it can be rewritten */
	186	irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
a53c17d2 GN	187	}
a53c17d2 GN	188	#endif
58c2dde1	189	return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
a53c17d2 GN	190	}
a53c17d2 GN	191
4925663a	192	int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
1fd4f2a5 ED	193	{
	194	u32 old_irr = ioapic->irr;
	195	u32 mask = 1 << irq;
cf9e4e15	196	union kvm_ioapic_redirect_entry entry;
4925663a	197	int ret = 1;
1fd4f2a5	198
eba0226b	199	mutex_lock(&ioapic->lock);
1fd4f2a5 ED	200	if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
	201	entry = ioapic->redirtbl[irq];
	202	level ^= entry.fields.polarity;
	203	if (!level)
	204	ioapic->irr &= ~mask;
	205	else {
b4a2f5e7	206	int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
1fd4f2a5	207	ioapic->irr \|= mask;
b4a2f5e7 GN	208	if ((edge && old_irr != ioapic->irr) \|\|
b4a2f5e7 GN	209	(!edge && !entry.fields.remote_irr))
4925663a	210	ret = ioapic_service(ioapic, irq);
65a82211 GN	211	else
65a82211 GN	212	ret = 0; /* report coalesced interrupt */
1fd4f2a5	213	}
1000ff8d	214	trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
1fd4f2a5	215	}
eba0226b GN	216	mutex_unlock(&ioapic->lock);
eba0226b GN	217
4925663a	218	return ret;
1fd4f2a5 ED	219	}
1fd4f2a5 ED	220
eba0226b GN	221	static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
eba0226b GN	222	int trigger_mode)
1fd4f2a5	223	{
eba0226b GN	224	int i;
	225
	226	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
	227	union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
1fd4f2a5	228
eba0226b GN	229	if (ent->fields.vector != vector)
eba0226b GN	230	continue;
1fd4f2a5	231
eba0226b GN	232	/*
	233	* We are dropping lock while calling ack notifiers because ack
	234	* notifier callbacks for assigned devices call into IOAPIC
	235	* recursively. Since remote_irr is cleared only after call
	236	* to notifiers if the same vector will be delivered while lock
	237	* is dropped it will be put into irr and will be delivered
	238	* after ack notifier returns.
	239	*/
	240	mutex_unlock(&ioapic->lock);
	241	kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
	242	mutex_lock(&ioapic->lock);
	243
	244	if (trigger_mode != IOAPIC_LEVEL_TRIG)
	245	continue;
f5244726	246
f5244726 MT	247	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
f5244726 MT	248	ent->fields.remote_irr = 0;
eba0226b GN	249	if (!ent->fields.mask && (ioapic->irr & (1 << i)))
eba0226b GN	250	ioapic_service(ioapic, i);
f5244726	251	}
1fd4f2a5 ED	252	}
1fd4f2a5 ED	253
f5244726	254	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
4fa6b9c5 AK	255	{
4fa6b9c5 AK	256	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
4fa6b9c5	257
46a929bc AK	258	smp_rmb();
	259	if (!test_bit(vector, ioapic->handled_vectors))
	260	return;
eba0226b GN	261	mutex_lock(&ioapic->lock);
	262	__kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
	263	mutex_unlock(&ioapic->lock);
4fa6b9c5 AK	264	}
4fa6b9c5 AK	265
d76685c4 GH	266	static inline struct kvm_ioapic to_ioapic(struct kvm_io_device dev)
	267	{
	268	return container_of(dev, struct kvm_ioapic, dev);
	269	}
	270
bda9020e	271	static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
1fd4f2a5	272	{
1fd4f2a5 ED	273	return ((addr >= ioapic->base_address &&
	274	(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
	275	}
	276
bda9020e MT	277	static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	278	void *val)
1fd4f2a5	279	{
d76685c4	280	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	281	u32 result;
bda9020e MT	282	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	283	return -EOPNOTSUPP;
1fd4f2a5	284
e25e3ed5	285	ioapic_debug("addr %lx\n", (unsigned long)addr);
1fd4f2a5 ED	286	ASSERT(!(addr & 0xf)); /* check alignment */
	287
	288	addr &= 0xff;
eba0226b	289	mutex_lock(&ioapic->lock);
1fd4f2a5 ED	290	switch (addr) {
	291	case IOAPIC_REG_SELECT:
	292	result = ioapic->ioregsel;
	293	break;
	294
	295	case IOAPIC_REG_WINDOW:
	296	result = ioapic_read_indirect(ioapic, addr, len);
	297	break;
	298
	299	default:
	300	result = 0;
	301	break;
	302	}
eba0226b GN	303	mutex_unlock(&ioapic->lock);
eba0226b GN	304
1fd4f2a5 ED	305	switch (len) {
	306	case 8:
	307	(u64 ) val = result;
	308	break;
	309	case 1:
	310	case 2:
	311	case 4:
	312	memcpy(val, (char *)&result, len);
	313	break;
	314	default:
	315	printk(KERN_WARNING "ioapic: wrong length %d\n", len);
	316	}
bda9020e	317	return 0;
1fd4f2a5 ED	318	}
1fd4f2a5 ED	319
bda9020e MT	320	static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
bda9020e MT	321	const void *val)
1fd4f2a5	322	{
d76685c4	323	struct kvm_ioapic *ioapic = to_ioapic(this);
1fd4f2a5	324	u32 data;
bda9020e MT	325	if (!ioapic_in_range(ioapic, addr))
bda9020e MT	326	return -EOPNOTSUPP;
1fd4f2a5	327
e25e3ed5 LV	328	ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
e25e3ed5 LV	329	(void*)addr, len, val);
1fd4f2a5	330	ASSERT(!(addr & 0xf)); /* check alignment */
60eead79	331
1fd4f2a5 ED	332	if (len == 4 \|\| len == 8)
	333	data = (u32 ) val;
	334	else {
	335	printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
eba0226b	336	return 0;
1fd4f2a5 ED	337	}
	338
	339	addr &= 0xff;
eba0226b	340	mutex_lock(&ioapic->lock);
1fd4f2a5 ED	341	switch (addr) {
	342	case IOAPIC_REG_SELECT:
	343	ioapic->ioregsel = data;
	344	break;
	345
	346	case IOAPIC_REG_WINDOW:
	347	ioapic_write_indirect(ioapic, data);
	348	break;
b1fd3d30 ZX	349	#ifdef CONFIG_IA64
b1fd3d30 ZX	350	case IOAPIC_REG_EOI:
eba0226b	351	__kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
b1fd3d30 ZX	352	break;
b1fd3d30 ZX	353	#endif
1fd4f2a5 ED	354
	355	default:
	356	break;
	357	}
eba0226b	358	mutex_unlock(&ioapic->lock);
bda9020e	359	return 0;
1fd4f2a5 ED	360	}
1fd4f2a5 ED	361
8c392696 ED	362	void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
	363	{
	364	int i;
	365
	366	for (i = 0; i < IOAPIC_NUM_PINS; i++)
	367	ioapic->redirtbl[i].fields.mask = 1;
	368	ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
	369	ioapic->ioregsel = 0;
	370	ioapic->irr = 0;
	371	ioapic->id = 0;
46a929bc	372	update_handled_vectors(ioapic);
8c392696 ED	373	}
8c392696 ED	374
d76685c4 GH	375	static const struct kvm_io_device_ops ioapic_mmio_ops = {
	376	.read = ioapic_mmio_read,
	377	.write = ioapic_mmio_write,
d76685c4 GH	378	};
d76685c4 GH	379
1fd4f2a5 ED	380	int kvm_ioapic_init(struct kvm *kvm)
	381	{
	382	struct kvm_ioapic *ioapic;
090b7aff	383	int ret;
1fd4f2a5 ED	384
	385	ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
	386	if (!ioapic)
	387	return -ENOMEM;
eba0226b	388	mutex_init(&ioapic->lock);
d7deeeb0	389	kvm->arch.vioapic = ioapic;
8c392696	390	kvm_ioapic_reset(ioapic);
d76685c4	391	kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
1fd4f2a5	392	ioapic->kvm = kvm;
79fac95e	393	mutex_lock(&kvm->slots_lock);
e93f8a0f	394	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
79fac95e	395	mutex_unlock(&kvm->slots_lock);
090b7aff GH	396	if (ret < 0)
	397	kfree(ioapic);
	398
	399	return ret;
1fd4f2a5	400	}
75858a84	401
eba0226b GN	402	int kvm_get_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	403	{
	404	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	405	if (!ioapic)
	406	return -EINVAL;
	407
	408	mutex_lock(&ioapic->lock);
	409	memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
	410	mutex_unlock(&ioapic->lock);
	411	return 0;
	412	}
	413
	414	int kvm_set_ioapic(struct kvm kvm, struct kvm_ioapic_state state)
	415	{
	416	struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
	417	if (!ioapic)
	418	return -EINVAL;
	419
	420	mutex_lock(&ioapic->lock);
	421	memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
46a929bc	422	update_handled_vectors(ioapic);
eba0226b GN	423	mutex_unlock(&ioapic->lock);
	424	return 0;
	425	}