[deliverable/linux.git] / virt / kvm / irq_comm.c

/*
 * irq_comm.c: Common API for in kernel interrupt controller
 * Copyright (c) 2007, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 */

#include <linux/kvm_host.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <trace/events/kvm.h>

#include <asm/msidef.h>
#ifdef CONFIG_IA64
#include <asm/iosapic.h>
#endif

#include "irq.h"

#include "ioapic.h"

static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
			   struct kvm *kvm, int irq_source_id, int level,
			   bool line_status)
{
#ifdef CONFIG_X86
	struct kvm_pic *pic = pic_irqchip(kvm);
	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
#else
	return -1;
#endif
}

static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level,
			      bool line_status)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
				line_status);
}

inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
{
#ifdef CONFIG_IA64
	return irq->delivery_mode ==
		(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
#else
	return irq->delivery_mode == APIC_DM_LOWEST;
#endif
}

int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, unsigned long *dest_map)
{
	int i, r = -1;
	struct kvm_vcpu *vcpu, *lowest = NULL;

	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
			kvm_is_dm_lowest_prio(irq)) {
		printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
		irq->delivery_mode = APIC_DM_FIXED;
	}

	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
		return r;

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (!kvm_is_dm_lowest_prio(irq)) {
			if (r < 0)
				r = 0;
			r += kvm_apic_set_irq(vcpu, irq, dest_map);
		} else if (kvm_lapic_enabled(vcpu)) {
			if (!lowest)
				lowest = vcpu;
			else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
				lowest = vcpu;
		}
	}

	if (lowest)
		r = kvm_apic_set_irq(lowest, irq, dest_map);

	return r;
}

static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
				   struct kvm_lapic_irq *irq)
{
	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);

	irq->dest_id = (e->msi.address_lo &
			MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	irq->vector = (e->msi.data &
			MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	irq->delivery_mode = e->msi.data & 0x700;
	irq->level = 1;
	irq->shorthand = 0;
	/* TODO Deal with RH bit of MSI message address */
}

int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
		struct kvm *kvm, int irq_source_id, int level, bool line_status)
{
	struct kvm_lapic_irq irq;

	if (!level)
		return -1;

	kvm_set_msi_irq(e, &irq);

	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
}


static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
			 struct kvm *kvm)
{
	struct kvm_lapic_irq irq;
	int r;

	kvm_set_msi_irq(e, &irq);

	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
		return r;
	else
		return -EWOULDBLOCK;
}

/*
 * Deliver an IRQ in an atomic context if we can, or return a failure,
 * user can retry in a process context.
 * Return value:
 *  -EWOULDBLOCK - Can't deliver in atomic context: retry in a process context.
 *  Other values - No need to retry.
 */
int kvm_set_irq_inatomic(struct kvm *kvm, int irq_source_id, u32 irq, int level)
{
	struct kvm_kernel_irq_routing_entry *e;
	int ret = -EINVAL;
	struct kvm_irq_routing_table *irq_rt;
	int idx;

	trace_kvm_set_irq(irq, level, irq_source_id);

	/*
	 * Injection into either PIC or IOAPIC might need to scan all CPUs,
	 * which would need to be retried from thread context;  when same GSI
	 * is connected to both PIC and IOAPIC, we'd have to report a
	 * partial failure here.
	 * Since there's no easy way to do this, we only support injecting MSI
	 * which is limited to 1:1 GSI mapping.
	 */
	idx = srcu_read_lock(&kvm->irq_srcu);
	irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
	if (irq < irq_rt->nr_rt_entries)
		hlist_for_each_entry(e, &irq_rt->map[irq], link) {
			if (likely(e->type == KVM_IRQ_ROUTING_MSI))
				ret = kvm_set_msi_inatomic(e, kvm);
			else
				ret = -EWOULDBLOCK;
			break;
		}
	srcu_read_unlock(&kvm->irq_srcu, idx);
	return ret;
}

int kvm_request_irq_source_id(struct kvm *kvm)
{
	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
	int irq_source_id;

	mutex_lock(&kvm->irq_lock);
	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);

	if (irq_source_id >= BITS_PER_LONG) {
		printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
		irq_source_id = -EFAULT;
		goto unlock;
	}

	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
#ifdef CONFIG_X86
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
#endif
	set_bit(irq_source_id, bitmap);
unlock:
	mutex_unlock(&kvm->irq_lock);

	return irq_source_id;
}

void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
{
	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
#ifdef CONFIG_X86
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
#endif

	mutex_lock(&kvm->irq_lock);
	if (irq_source_id < 0 ||
	    irq_source_id >= BITS_PER_LONG) {
		printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
		goto unlock;
	}
	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
	if (!irqchip_in_kernel(kvm))
		goto unlock;

	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
#ifdef CONFIG_X86
	kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
#endif
unlock:
	mutex_unlock(&kvm->irq_lock);
}

void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
				    struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	kimn->irq = irq;
	hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
				      struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	hlist_del_rcu(&kimn->link);
	mutex_unlock(&kvm->irq_lock);
	synchronize_srcu(&kvm->irq_srcu);
}

void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
			     bool mask)
{
	struct kvm_irq_mask_notifier *kimn;
	int idx, gsi;

	idx = srcu_read_lock(&kvm->irq_srcu);
	gsi = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu)->chip[irqchip][pin];
	if (gsi != -1)
		hlist_for_each_entry_rcu(kimn, &kvm->mask_notifier_list, link)
			if (kimn->irq == gsi)
				kimn->func(kimn, mask);
	srcu_read_unlock(&kvm->irq_srcu, idx);
}

int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
			  struct kvm_kernel_irq_routing_entry *e,
			  const struct kvm_irq_routing_entry *ue)
{
	int r = -EINVAL;
	int delta;
	unsigned max_pin;

	switch (ue->type) {
	case KVM_IRQ_ROUTING_IRQCHIP:
		delta = 0;
		switch (ue->u.irqchip.irqchip) {
		case KVM_IRQCHIP_PIC_MASTER:
			e->set = kvm_set_pic_irq;
			max_pin = PIC_NUM_PINS;
			break;
		case KVM_IRQCHIP_PIC_SLAVE:
			e->set = kvm_set_pic_irq;
			max_pin = PIC_NUM_PINS;
			delta = 8;
			break;
		case KVM_IRQCHIP_IOAPIC:
			max_pin = KVM_IOAPIC_NUM_PINS;
			e->set = kvm_set_ioapic_irq;
			break;
		default:
			goto out;
		}
		e->irqchip.irqchip = ue->u.irqchip.irqchip;
		e->irqchip.pin = ue->u.irqchip.pin + delta;
		if (e->irqchip.pin >= max_pin)
			goto out;
		rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
		break;
	case KVM_IRQ_ROUTING_MSI:
		e->set = kvm_set_msi;
		e->msi.address_lo = ue->u.msi.address_lo;
		e->msi.address_hi = ue->u.msi.address_hi;
		e->msi.data = ue->u.msi.data;
		break;
	default:
		goto out;
	}

	r = 0;
out:
	return r;
}

#define IOAPIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) }
#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)

#ifdef CONFIG_X86
#  define PIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 }
#  define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
#else
#  define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq)
#endif

static const struct kvm_irq_routing_entry default_routing[] = {
	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
#ifdef CONFIG_IA64
	ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
	ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
	ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
	ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
	ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
	ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
	ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
	ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
	ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
	ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
	ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
	ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
#endif
};

int kvm_setup_default_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, default_routing,
				   ARRAY_SIZE(default_routing), 0);
}
Commit	Line	Data
3de42dc0 XZ	1	/*
	2	* irq_comm.c: Common API for in kernel interrupt controller
	3	* Copyright (c) 2007, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	16	* Place - Suite 330, Boston, MA 02111-1307 USA.
	17	* Authors:
	18	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	19	*
9611c187	20	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
3de42dc0 XZ	21	*/
	22
	23	#include <linux/kvm_host.h>
5a0e3ad6	24	#include <linux/slab.h>
c7c9c56c	25	#include <linux/export.h>
229456fc	26	#include <trace/events/kvm.h>
79950e10	27
79950e10	28	#include <asm/msidef.h>
58c2dde1 GN	29	#ifdef CONFIG_IA64
	30	#include <asm/iosapic.h>
	31	#endif
79950e10	32
3de42dc0 XZ	33	#include "irq.h"
	34
	35	#include "ioapic.h"
	36
4925663a	37	static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	38	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	39	bool line_status)
399ec807 AK	40	{
399ec807 AK	41	#ifdef CONFIG_X86
1a6e4a8c	42	struct kvm_pic *pic = pic_irqchip(kvm);
1a577b72	43	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
4925663a GN	44	#else
4925663a GN	45	return -1;
399ec807 AK	46	#endif
	47	}
	48
4925663a	49	static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	50	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	51	bool line_status)
399ec807	52	{
1a6e4a8c	53	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
aa2fbe6d YZ	54	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
aa2fbe6d YZ	55	line_status);
399ec807 AK	56	}
399ec807 AK	57
58c2dde1	58	inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
116191b6	59	{
58c2dde1 GN	60	#ifdef CONFIG_IA64
	61	return irq->delivery_mode ==
	62	(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
	63	#else
	64	return irq->delivery_mode == APIC_DM_LOWEST;
	65	#endif
	66	}
116191b6	67
58c2dde1	68	int kvm_irq_delivery_to_apic(struct kvm kvm, struct kvm_lapic src,
b4f2225c	69	struct kvm_lapic_irq irq, unsigned long dest_map)
58c2dde1 GN	70	{
	71	int i, r = -1;
	72	struct kvm_vcpu vcpu, lowest = NULL;
	73
	74	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
1e08ec4a	75	kvm_is_dm_lowest_prio(irq)) {
343f94fe	76	printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
1e08ec4a GN	77	irq->delivery_mode = APIC_DM_FIXED;
	78	}
	79
b4f2225c	80	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
1e08ec4a	81	return r;
343f94fe	82
988a2cae GN	83	kvm_for_each_vcpu(i, vcpu, kvm) {
988a2cae GN	84	if (!kvm_apic_present(vcpu))
343f94fe GN	85	continue;
343f94fe GN	86
58c2dde1 GN	87	if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
58c2dde1 GN	88	irq->dest_id, irq->dest_mode))
343f94fe GN	89	continue;
343f94fe GN	90
58c2dde1 GN	91	if (!kvm_is_dm_lowest_prio(irq)) {
	92	if (r < 0)
	93	r = 0;
b4f2225c	94	r += kvm_apic_set_irq(vcpu, irq, dest_map);
aefd18f0	95	} else if (kvm_lapic_enabled(vcpu)) {
58c2dde1 GN	96	if (!lowest)
	97	lowest = vcpu;
	98	else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
	99	lowest = vcpu;
e1035715	100	}
343f94fe GN	101	}
343f94fe GN	102
58c2dde1	103	if (lowest)
b4f2225c	104	r = kvm_apic_set_irq(lowest, irq, dest_map);
58c2dde1 GN	105
58c2dde1 GN	106	return r;
116191b6 SY	107	}
116191b6 SY	108
01f21880 MT	109	static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
	110	struct kvm_lapic_irq *irq)
	111	{
	112	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
	113
	114	irq->dest_id = (e->msi.address_lo &
	115	MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	116	irq->vector = (e->msi.data &
	117	MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	118	irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	119	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	120	irq->delivery_mode = e->msi.data & 0x700;
	121	irq->level = 1;
	122	irq->shorthand = 0;
	123	/* TODO Deal with RH bit of MSI message address */
	124	}
	125
bd2b53b2	126	int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d	127	struct kvm *kvm, int irq_source_id, int level, bool line_status)
79950e10	128	{
58c2dde1	129	struct kvm_lapic_irq irq;
79950e10	130
1a6e4a8c GN	131	if (!level)
	132	return -1;
	133
01f21880	134	kvm_set_msi_irq(e, &irq);
116191b6	135
b4f2225c	136	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
79950e10 SY	137	}
79950e10 SY	138
01f21880 MT	139
	140	static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
	141	struct kvm *kvm)
	142	{
	143	struct kvm_lapic_irq irq;
	144	int r;
	145
	146	kvm_set_msi_irq(e, &irq);
	147
b4f2225c	148	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
01f21880 MT	149	return r;
	150	else
	151	return -EWOULDBLOCK;
	152	}
	153
01f21880 MT	154	/*
	155	* Deliver an IRQ in an atomic context if we can, or return a failure,
	156	* user can retry in a process context.
	157	* Return value:
	158	* -EWOULDBLOCK - Can't deliver in atomic context: retry in a process context.
	159	* Other values - No need to retry.
	160	*/
	161	int kvm_set_irq_inatomic(struct kvm *kvm, int irq_source_id, u32 irq, int level)
	162	{
	163	struct kvm_kernel_irq_routing_entry *e;
	164	int ret = -EINVAL;
	165	struct kvm_irq_routing_table *irq_rt;
719d93cd	166	int idx;
01f21880 MT	167
	168	trace_kvm_set_irq(irq, level, irq_source_id);
	169
	170	/*
	171	* Injection into either PIC or IOAPIC might need to scan all CPUs,
	172	* which would need to be retried from thread context; when same GSI
	173	* is connected to both PIC and IOAPIC, we'd have to report a
	174	* partial failure here.
	175	* Since there's no easy way to do this, we only support injecting MSI
	176	* which is limited to 1:1 GSI mapping.
	177	*/
719d93cd CB	178	idx = srcu_read_lock(&kvm->irq_srcu);
719d93cd CB	179	irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
01f21880	180	if (irq < irq_rt->nr_rt_entries)
b67bfe0d	181	hlist_for_each_entry(e, &irq_rt->map[irq], link) {
01f21880 MT	182	if (likely(e->type == KVM_IRQ_ROUTING_MSI))
	183	ret = kvm_set_msi_inatomic(e, kvm);
	184	else
	185	ret = -EWOULDBLOCK;
	186	break;
	187	}
719d93cd	188	srcu_read_unlock(&kvm->irq_srcu, idx);
01f21880 MT	189	return ret;
	190	}
	191
5550af4d SY	192	int kvm_request_irq_source_id(struct kvm *kvm)
	193	{
	194	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
fa40a821 MT	195	int irq_source_id;
	196
	197	mutex_lock(&kvm->irq_lock);
cd5a2685	198	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
61552367	199
cd5a2685	200	if (irq_source_id >= BITS_PER_LONG) {
5550af4d	201	printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
0c6ddceb JS	202	irq_source_id = -EFAULT;
0c6ddceb JS	203	goto unlock;
61552367 MM	204	}
	205
	206	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a AW	207	#ifdef CONFIG_X86
	208	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
	209	#endif
61552367	210	set_bit(irq_source_id, bitmap);
0c6ddceb	211	unlock:
fa40a821	212	mutex_unlock(&kvm->irq_lock);
61552367	213
5550af4d SY	214	return irq_source_id;
	215	}
	216
	217	void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
	218	{
61552367	219	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a AW	220	#ifdef CONFIG_X86
	221	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
	222	#endif
61552367	223
fa40a821	224	mutex_lock(&kvm->irq_lock);
61552367	225	if (irq_source_id < 0 \|\|
cd5a2685	226	irq_source_id >= BITS_PER_LONG) {
5550af4d	227	printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
0c6ddceb	228	goto unlock;
5550af4d	229	}
e50212bb MT	230	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
	231	if (!irqchip_in_kernel(kvm))
	232	goto unlock;
	233
1a577b72	234	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
1a6e4a8c	235	#ifdef CONFIG_X86
1a577b72	236	kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
1a6e4a8c	237	#endif
0c6ddceb	238	unlock:
fa40a821	239	mutex_unlock(&kvm->irq_lock);
5550af4d	240	}
75858a84 AK	241
	242	void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
	243	struct kvm_irq_mask_notifier *kimn)
	244	{
fa40a821	245	mutex_lock(&kvm->irq_lock);
75858a84	246	kimn->irq = irq;
280aa177	247	hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list);
fa40a821	248	mutex_unlock(&kvm->irq_lock);
75858a84 AK	249	}
	250
	251	void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
	252	struct kvm_irq_mask_notifier *kimn)
	253	{
fa40a821	254	mutex_lock(&kvm->irq_lock);
280aa177	255	hlist_del_rcu(&kimn->link);
fa40a821	256	mutex_unlock(&kvm->irq_lock);
719d93cd	257	synchronize_srcu(&kvm->irq_srcu);
75858a84 AK	258	}
75858a84 AK	259
4a994358 GN	260	void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
4a994358 GN	261	bool mask)
75858a84 AK	262	{
75858a84 AK	263	struct kvm_irq_mask_notifier *kimn;
719d93cd	264	int idx, gsi;
75858a84	265
719d93cd CB	266	idx = srcu_read_lock(&kvm->irq_srcu);
719d93cd CB	267	gsi = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu)->chip[irqchip][pin];
4a994358	268	if (gsi != -1)
b67bfe0d	269	hlist_for_each_entry_rcu(kimn, &kvm->mask_notifier_list, link)
4a994358 GN	270	if (kimn->irq == gsi)
4a994358 GN	271	kimn->func(kimn, mask);
719d93cd	272	srcu_read_unlock(&kvm->irq_srcu, idx);
75858a84 AK	273	}
75858a84 AK	274
e8cde093 AG	275	int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
	276	struct kvm_kernel_irq_routing_entry *e,
	277	const struct kvm_irq_routing_entry *ue)
399ec807 AK	278	{
	279	int r = -EINVAL;
	280	int delta;
d72118ce	281	unsigned max_pin;
46e624b9	282
399ec807 AK	283	switch (ue->type) {
	284	case KVM_IRQ_ROUTING_IRQCHIP:
	285	delta = 0;
	286	switch (ue->u.irqchip.irqchip) {
	287	case KVM_IRQCHIP_PIC_MASTER:
	288	e->set = kvm_set_pic_irq;
93b6547e	289	max_pin = PIC_NUM_PINS;
399ec807 AK	290	break;
399ec807 AK	291	case KVM_IRQCHIP_PIC_SLAVE:
4925663a	292	e->set = kvm_set_pic_irq;
93b6547e	293	max_pin = PIC_NUM_PINS;
399ec807 AK	294	delta = 8;
	295	break;
	296	case KVM_IRQCHIP_IOAPIC:
d72118ce	297	max_pin = KVM_IOAPIC_NUM_PINS;
efbc100c	298	e->set = kvm_set_ioapic_irq;
399ec807 AK	299	break;
	300	default:
	301	goto out;
	302	}
	303	e->irqchip.irqchip = ue->u.irqchip.irqchip;
	304	e->irqchip.pin = ue->u.irqchip.pin + delta;
d72118ce	305	if (e->irqchip.pin >= max_pin)
3e71f88b GN	306	goto out;
3e71f88b GN	307	rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
399ec807	308	break;
79950e10 SY	309	case KVM_IRQ_ROUTING_MSI:
	310	e->set = kvm_set_msi;
	311	e->msi.address_lo = ue->u.msi.address_lo;
	312	e->msi.address_hi = ue->u.msi.address_hi;
	313	e->msi.data = ue->u.msi.data;
	314	break;
399ec807 AK	315	default:
	316	goto out;
	317	}
46e624b9	318
399ec807 AK	319	r = 0;
	320	out:
	321	return r;
	322	}
	323
399ec807 AK	324	#define IOAPIC_ROUTING_ENTRY(irq) \
	325	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
	326	.u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) }
	327	#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
	328
	329	#ifdef CONFIG_X86
399ec807 AK	330	# define PIC_ROUTING_ENTRY(irq) \
	331	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
	332	.u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 }
	333	# define ROUTING_ENTRY2(irq) \
	334	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
	335	#else
	336	# define ROUTING_ENTRY2(irq) \
	337	IOAPIC_ROUTING_ENTRY(irq)
	338	#endif
	339
	340	static const struct kvm_irq_routing_entry default_routing[] = {
	341	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	342	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	343	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	344	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	345	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	346	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	347	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	348	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	349	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	350	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	351	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	352	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
	353	#ifdef CONFIG_IA64
	354	ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
	355	ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
	356	ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
	357	ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
	358	ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
	359	ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
	360	ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
	361	ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
	362	ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
	363	ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
	364	ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
	365	ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
	366	#endif
	367	};
	368
	369	int kvm_setup_default_irq_routing(struct kvm *kvm)
	370	{
	371	return kvm_set_irq_routing(kvm, default_routing,
	372	ARRAY_SIZE(default_routing), 0);
	373	}