| 1 | /dts-v1/; |
| 2 | |
| 3 | /include/ "skeleton.dtsi" |
| 4 | |
| 5 | #include <dt-bindings/interrupt-controller/irq.h> |
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 7 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> |
| 8 | #include <dt-bindings/soc/qcom,gsbi.h> |
| 9 | |
| 10 | / { |
| 11 | model = "Qualcomm MSM8660"; |
| 12 | compatible = "qcom,msm8660"; |
| 13 | interrupt-parent = <&intc>; |
| 14 | |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu@0 { |
| 20 | compatible = "qcom,scorpion"; |
| 21 | enable-method = "qcom,gcc-msm8660"; |
| 22 | device_type = "cpu"; |
| 23 | reg = <0>; |
| 24 | next-level-cache = <&L2>; |
| 25 | }; |
| 26 | |
| 27 | cpu@1 { |
| 28 | compatible = "qcom,scorpion"; |
| 29 | enable-method = "qcom,gcc-msm8660"; |
| 30 | device_type = "cpu"; |
| 31 | reg = <1>; |
| 32 | next-level-cache = <&L2>; |
| 33 | }; |
| 34 | |
| 35 | L2: l2-cache { |
| 36 | compatible = "cache"; |
| 37 | cache-level = <2>; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | cpu-pmu { |
| 42 | compatible = "qcom,scorpion-mp-pmu"; |
| 43 | interrupts = <1 9 0x304>; |
| 44 | }; |
| 45 | |
| 46 | clocks { |
| 47 | cxo_board { |
| 48 | compatible = "fixed-clock"; |
| 49 | #clock-cells = <0>; |
| 50 | clock-frequency = <19200000>; |
| 51 | }; |
| 52 | |
| 53 | pxo_board { |
| 54 | compatible = "fixed-clock"; |
| 55 | #clock-cells = <0>; |
| 56 | clock-frequency = <27000000>; |
| 57 | }; |
| 58 | |
| 59 | sleep_clk { |
| 60 | compatible = "fixed-clock"; |
| 61 | #clock-cells = <0>; |
| 62 | clock-frequency = <32768>; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | soc: soc { |
| 67 | #address-cells = <1>; |
| 68 | #size-cells = <1>; |
| 69 | ranges; |
| 70 | compatible = "simple-bus"; |
| 71 | |
| 72 | intc: interrupt-controller@2080000 { |
| 73 | compatible = "qcom,msm-8660-qgic"; |
| 74 | interrupt-controller; |
| 75 | #interrupt-cells = <3>; |
| 76 | reg = < 0x02080000 0x1000 >, |
| 77 | < 0x02081000 0x1000 >; |
| 78 | }; |
| 79 | |
| 80 | timer@2000000 { |
| 81 | compatible = "qcom,scss-timer", "qcom,msm-timer"; |
| 82 | interrupts = <1 0 0x301>, |
| 83 | <1 1 0x301>, |
| 84 | <1 2 0x301>; |
| 85 | reg = <0x02000000 0x100>; |
| 86 | clock-frequency = <27000000>, |
| 87 | <32768>; |
| 88 | cpu-offset = <0x40000>; |
| 89 | }; |
| 90 | |
| 91 | tlmm: pinctrl@800000 { |
| 92 | compatible = "qcom,msm8660-pinctrl"; |
| 93 | reg = <0x800000 0x4000>; |
| 94 | |
| 95 | gpio-controller; |
| 96 | #gpio-cells = <2>; |
| 97 | interrupts = <0 16 0x4>; |
| 98 | interrupt-controller; |
| 99 | #interrupt-cells = <2>; |
| 100 | |
| 101 | }; |
| 102 | |
| 103 | gcc: clock-controller@900000 { |
| 104 | compatible = "qcom,gcc-msm8660"; |
| 105 | #clock-cells = <1>; |
| 106 | #reset-cells = <1>; |
| 107 | reg = <0x900000 0x4000>; |
| 108 | }; |
| 109 | |
| 110 | gsbi12: gsbi@19c00000 { |
| 111 | compatible = "qcom,gsbi-v1.0.0"; |
| 112 | cell-index = <12>; |
| 113 | reg = <0x19c00000 0x100>; |
| 114 | clocks = <&gcc GSBI12_H_CLK>; |
| 115 | clock-names = "iface"; |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <1>; |
| 118 | ranges; |
| 119 | |
| 120 | syscon-tcsr = <&tcsr>; |
| 121 | |
| 122 | gsbi12_serial: serial@19c40000 { |
| 123 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| 124 | reg = <0x19c40000 0x1000>, |
| 125 | <0x19c00000 0x1000>; |
| 126 | interrupts = <0 195 IRQ_TYPE_NONE>; |
| 127 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; |
| 128 | clock-names = "core", "iface"; |
| 129 | status = "disabled"; |
| 130 | }; |
| 131 | |
| 132 | gsbi12_i2c: i2c@19c80000 { |
| 133 | compatible = "qcom,i2c-qup-v1.1.1"; |
| 134 | reg = <0x19c80000 0x1000>; |
| 135 | interrupts = <0 196 IRQ_TYPE_NONE>; |
| 136 | clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; |
| 137 | clock-names = "core", "iface"; |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <0>; |
| 140 | status = "disabled"; |
| 141 | }; |
| 142 | }; |
| 143 | |
| 144 | qcom,ssbi@500000 { |
| 145 | compatible = "qcom,ssbi"; |
| 146 | reg = <0x500000 0x1000>; |
| 147 | qcom,controller-type = "pmic-arbiter"; |
| 148 | |
| 149 | pmicintc: pmic@0 { |
| 150 | compatible = "qcom,pm8058"; |
| 151 | interrupt-parent = <&tlmm>; |
| 152 | interrupts = <88 8>; |
| 153 | #interrupt-cells = <2>; |
| 154 | interrupt-controller; |
| 155 | #address-cells = <1>; |
| 156 | #size-cells = <0>; |
| 157 | |
| 158 | pm8058_gpio: gpio@150 { |
| 159 | compatible = "qcom,pm8058-gpio", |
| 160 | "qcom,ssbi-gpio"; |
| 161 | reg = <0x150>; |
| 162 | interrupt-parent = <&pmicintc>; |
| 163 | interrupts = <192 IRQ_TYPE_NONE>, |
| 164 | <193 IRQ_TYPE_NONE>, |
| 165 | <194 IRQ_TYPE_NONE>, |
| 166 | <195 IRQ_TYPE_NONE>, |
| 167 | <196 IRQ_TYPE_NONE>, |
| 168 | <197 IRQ_TYPE_NONE>, |
| 169 | <198 IRQ_TYPE_NONE>, |
| 170 | <199 IRQ_TYPE_NONE>, |
| 171 | <200 IRQ_TYPE_NONE>, |
| 172 | <201 IRQ_TYPE_NONE>, |
| 173 | <202 IRQ_TYPE_NONE>, |
| 174 | <203 IRQ_TYPE_NONE>, |
| 175 | <204 IRQ_TYPE_NONE>, |
| 176 | <205 IRQ_TYPE_NONE>, |
| 177 | <206 IRQ_TYPE_NONE>, |
| 178 | <207 IRQ_TYPE_NONE>, |
| 179 | <208 IRQ_TYPE_NONE>, |
| 180 | <209 IRQ_TYPE_NONE>, |
| 181 | <210 IRQ_TYPE_NONE>, |
| 182 | <211 IRQ_TYPE_NONE>, |
| 183 | <212 IRQ_TYPE_NONE>, |
| 184 | <213 IRQ_TYPE_NONE>, |
| 185 | <214 IRQ_TYPE_NONE>, |
| 186 | <215 IRQ_TYPE_NONE>, |
| 187 | <216 IRQ_TYPE_NONE>, |
| 188 | <217 IRQ_TYPE_NONE>, |
| 189 | <218 IRQ_TYPE_NONE>, |
| 190 | <219 IRQ_TYPE_NONE>, |
| 191 | <220 IRQ_TYPE_NONE>, |
| 192 | <221 IRQ_TYPE_NONE>, |
| 193 | <222 IRQ_TYPE_NONE>, |
| 194 | <223 IRQ_TYPE_NONE>, |
| 195 | <224 IRQ_TYPE_NONE>, |
| 196 | <225 IRQ_TYPE_NONE>, |
| 197 | <226 IRQ_TYPE_NONE>, |
| 198 | <227 IRQ_TYPE_NONE>, |
| 199 | <228 IRQ_TYPE_NONE>, |
| 200 | <229 IRQ_TYPE_NONE>, |
| 201 | <230 IRQ_TYPE_NONE>, |
| 202 | <231 IRQ_TYPE_NONE>, |
| 203 | <232 IRQ_TYPE_NONE>, |
| 204 | <233 IRQ_TYPE_NONE>, |
| 205 | <234 IRQ_TYPE_NONE>, |
| 206 | <235 IRQ_TYPE_NONE>; |
| 207 | gpio-controller; |
| 208 | #gpio-cells = <2>; |
| 209 | |
| 210 | }; |
| 211 | |
| 212 | pm8058_mpps: mpps@50 { |
| 213 | compatible = "qcom,pm8058-mpp", |
| 214 | "qcom,ssbi-mpp"; |
| 215 | reg = <0x50>; |
| 216 | gpio-controller; |
| 217 | #gpio-cells = <2>; |
| 218 | interrupt-parent = <&pmicintc>; |
| 219 | interrupts = |
| 220 | <128 IRQ_TYPE_NONE>, |
| 221 | <129 IRQ_TYPE_NONE>, |
| 222 | <130 IRQ_TYPE_NONE>, |
| 223 | <131 IRQ_TYPE_NONE>, |
| 224 | <132 IRQ_TYPE_NONE>, |
| 225 | <133 IRQ_TYPE_NONE>, |
| 226 | <134 IRQ_TYPE_NONE>, |
| 227 | <135 IRQ_TYPE_NONE>, |
| 228 | <136 IRQ_TYPE_NONE>, |
| 229 | <137 IRQ_TYPE_NONE>, |
| 230 | <138 IRQ_TYPE_NONE>, |
| 231 | <139 IRQ_TYPE_NONE>; |
| 232 | }; |
| 233 | |
| 234 | pwrkey@1c { |
| 235 | compatible = "qcom,pm8058-pwrkey"; |
| 236 | reg = <0x1c>; |
| 237 | interrupt-parent = <&pmicintc>; |
| 238 | interrupts = <50 1>, <51 1>; |
| 239 | debounce = <15625>; |
| 240 | pull-up; |
| 241 | }; |
| 242 | |
| 243 | keypad@148 { |
| 244 | compatible = "qcom,pm8058-keypad"; |
| 245 | reg = <0x148>; |
| 246 | interrupt-parent = <&pmicintc>; |
| 247 | interrupts = <74 1>, <75 1>; |
| 248 | debounce = <15>; |
| 249 | scan-delay = <32>; |
| 250 | row-hold = <91500>; |
| 251 | }; |
| 252 | |
| 253 | rtc@1e8 { |
| 254 | compatible = "qcom,pm8058-rtc"; |
| 255 | reg = <0x1e8>; |
| 256 | interrupt-parent = <&pmicintc>; |
| 257 | interrupts = <39 1>; |
| 258 | allow-set-time; |
| 259 | }; |
| 260 | |
| 261 | vibrator@4a { |
| 262 | compatible = "qcom,pm8058-vib"; |
| 263 | reg = <0x4a>; |
| 264 | }; |
| 265 | }; |
| 266 | }; |
| 267 | |
| 268 | l2cc: clock-controller@2082000 { |
| 269 | compatible = "syscon"; |
| 270 | reg = <0x02082000 0x1000>; |
| 271 | }; |
| 272 | |
| 273 | rpm: rpm@104000 { |
| 274 | compatible = "qcom,rpm-msm8660"; |
| 275 | reg = <0x00104000 0x1000>; |
| 276 | qcom,ipc = <&l2cc 0x8 2>; |
| 277 | |
| 278 | interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, |
| 279 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, |
| 280 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; |
| 281 | interrupt-names = "ack", "err", "wakeup"; |
| 282 | clocks = <&gcc RPM_MSG_RAM_H_CLK>; |
| 283 | clock-names = "ram"; |
| 284 | |
| 285 | rpmcc: clock-controller { |
| 286 | compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc"; |
| 287 | #clock-cells = <1>; |
| 288 | }; |
| 289 | |
| 290 | pm8901-regulators { |
| 291 | compatible = "qcom,rpm-pm8901-regulators"; |
| 292 | |
| 293 | pm8901_l0: l0 {}; |
| 294 | pm8901_l1: l1 {}; |
| 295 | pm8901_l2: l2 {}; |
| 296 | pm8901_l3: l3 {}; |
| 297 | pm8901_l4: l4 {}; |
| 298 | pm8901_l5: l5 {}; |
| 299 | pm8901_l6: l6 {}; |
| 300 | |
| 301 | /* S0 and S1 Handled as SAW regulators by SPM */ |
| 302 | pm8901_s2: s2 {}; |
| 303 | pm8901_s3: s3 {}; |
| 304 | pm8901_s4: s4 {}; |
| 305 | |
| 306 | pm8901_lvs0: lvs0 {}; |
| 307 | pm8901_lvs1: lvs1 {}; |
| 308 | pm8901_lvs2: lvs2 {}; |
| 309 | pm8901_lvs3: lvs3 {}; |
| 310 | |
| 311 | pm8901_mvs: mvs {}; |
| 312 | }; |
| 313 | |
| 314 | pm8058-regulators { |
| 315 | compatible = "qcom,rpm-pm8058-regulators"; |
| 316 | |
| 317 | pm8058_l0: l0 {}; |
| 318 | pm8058_l1: l1 {}; |
| 319 | pm8058_l2: l2 {}; |
| 320 | pm8058_l3: l3 {}; |
| 321 | pm8058_l4: l4 {}; |
| 322 | pm8058_l5: l5 {}; |
| 323 | pm8058_l6: l6 {}; |
| 324 | pm8058_l7: l7 {}; |
| 325 | pm8058_l8: l8 {}; |
| 326 | pm8058_l9: l9 {}; |
| 327 | pm8058_l10: l10 {}; |
| 328 | pm8058_l11: l11 {}; |
| 329 | pm8058_l12: l12 {}; |
| 330 | pm8058_l13: l13 {}; |
| 331 | pm8058_l14: l14 {}; |
| 332 | pm8058_l15: l15 {}; |
| 333 | pm8058_l16: l16 {}; |
| 334 | pm8058_l17: l17 {}; |
| 335 | pm8058_l18: l18 {}; |
| 336 | pm8058_l19: l19 {}; |
| 337 | pm8058_l20: l20 {}; |
| 338 | pm8058_l21: l21 {}; |
| 339 | pm8058_l22: l22 {}; |
| 340 | pm8058_l23: l23 {}; |
| 341 | pm8058_l24: l24 {}; |
| 342 | pm8058_l25: l25 {}; |
| 343 | |
| 344 | pm8058_s0: s0 {}; |
| 345 | pm8058_s1: s1 {}; |
| 346 | pm8058_s2: s2 {}; |
| 347 | pm8058_s3: s3 {}; |
| 348 | pm8058_s4: s4 {}; |
| 349 | |
| 350 | pm8058_lvs0: lvs0 {}; |
| 351 | pm8058_lvs1: lvs1 {}; |
| 352 | |
| 353 | pm8058_ncp: ncp {}; |
| 354 | }; |
| 355 | }; |
| 356 | |
| 357 | amba { |
| 358 | compatible = "simple-bus"; |
| 359 | #address-cells = <1>; |
| 360 | #size-cells = <1>; |
| 361 | ranges; |
| 362 | sdcc1: sdcc@12400000 { |
| 363 | status = "disabled"; |
| 364 | compatible = "arm,pl18x", "arm,primecell"; |
| 365 | arm,primecell-periphid = <0x00051180>; |
| 366 | reg = <0x12400000 0x8000>; |
| 367 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| 368 | interrupt-names = "cmd_irq"; |
| 369 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; |
| 370 | clock-names = "mclk", "apb_pclk"; |
| 371 | bus-width = <8>; |
| 372 | max-frequency = <48000000>; |
| 373 | non-removable; |
| 374 | cap-sd-highspeed; |
| 375 | cap-mmc-highspeed; |
| 376 | }; |
| 377 | |
| 378 | sdcc3: sdcc@12180000 { |
| 379 | compatible = "arm,pl18x", "arm,primecell"; |
| 380 | arm,primecell-periphid = <0x00051180>; |
| 381 | status = "disabled"; |
| 382 | reg = <0x12180000 0x8000>; |
| 383 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 384 | interrupt-names = "cmd_irq"; |
| 385 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; |
| 386 | clock-names = "mclk", "apb_pclk"; |
| 387 | bus-width = <4>; |
| 388 | cap-sd-highspeed; |
| 389 | cap-mmc-highspeed; |
| 390 | max-frequency = <48000000>; |
| 391 | no-1-8-v; |
| 392 | }; |
| 393 | |
| 394 | sdcc5: sdcc@12200000 { |
| 395 | compatible = "arm,pl18x", "arm,primecell"; |
| 396 | arm,primecell-periphid = <0x00051180>; |
| 397 | status = "disabled"; |
| 398 | reg = <0x12200000 0x8000>; |
| 399 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
| 400 | interrupt-names = "cmd_irq"; |
| 401 | clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; |
| 402 | clock-names = "mclk", "apb_pclk"; |
| 403 | bus-width = <4>; |
| 404 | cap-sd-highspeed; |
| 405 | cap-mmc-highspeed; |
| 406 | max-frequency = <48000000>; |
| 407 | }; |
| 408 | }; |
| 409 | |
| 410 | tcsr: syscon@1a400000 { |
| 411 | compatible = "qcom,tcsr-msm8660", "syscon"; |
| 412 | reg = <0x1a400000 0x100>; |
| 413 | }; |
| 414 | }; |
| 415 | |
| 416 | }; |