| 1 | /* |
| 2 | * Device Tree Source for the r8a73a4 SoC |
| 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2013 Magnus Damm |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <dt-bindings/clock/r8a73a4-clock.h> |
| 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
| 16 | / { |
| 17 | compatible = "renesas,r8a73a4"; |
| 18 | interrupt-parent = <&gic>; |
| 19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; |
| 21 | |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | |
| 26 | cpu0: cpu@0 { |
| 27 | device_type = "cpu"; |
| 28 | compatible = "arm,cortex-a15"; |
| 29 | reg = <0>; |
| 30 | clock-frequency = <1500000000>; |
| 31 | power-domains = <&pd_a2sl>; |
| 32 | next-level-cache = <&L2_CA15>; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | ptm { |
| 37 | compatible = "arm,coresight-etm3x"; |
| 38 | power-domains = <&pd_d4>; |
| 39 | }; |
| 40 | |
| 41 | timer { |
| 42 | compatible = "arm,armv7-timer"; |
| 43 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 44 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 45 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 46 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 47 | }; |
| 48 | |
| 49 | L2_CA15: cache-controller@0 { |
| 50 | compatible = "cache"; |
| 51 | clocks = <&cpg_clocks R8A73A4_CLK_Z>; |
| 52 | power-domains = <&pd_a3sm>; |
| 53 | cache-unified; |
| 54 | cache-level = <2>; |
| 55 | }; |
| 56 | |
| 57 | L2_CA7: cache-controller@1 { |
| 58 | compatible = "cache"; |
| 59 | clocks = <&cpg_clocks R8A73A4_CLK_Z2>; |
| 60 | power-domains = <&pd_a3km>; |
| 61 | cache-unified; |
| 62 | cache-level = <2>; |
| 63 | }; |
| 64 | |
| 65 | dbsc1: memory-controller@e6790000 { |
| 66 | compatible = "renesas,dbsc-r8a73a4"; |
| 67 | reg = <0 0xe6790000 0 0x10000>; |
| 68 | power-domains = <&pd_a3bc>; |
| 69 | }; |
| 70 | |
| 71 | dbsc2: memory-controller@e67a0000 { |
| 72 | compatible = "renesas,dbsc-r8a73a4"; |
| 73 | reg = <0 0xe67a0000 0 0x10000>; |
| 74 | power-domains = <&pd_a3bc>; |
| 75 | }; |
| 76 | |
| 77 | dmac: dma-multiplexer { |
| 78 | compatible = "renesas,shdma-mux"; |
| 79 | #dma-cells = <1>; |
| 80 | dma-channels = <20>; |
| 81 | dma-requests = <256>; |
| 82 | #address-cells = <2>; |
| 83 | #size-cells = <2>; |
| 84 | ranges; |
| 85 | |
| 86 | dma0: dma-controller@e6700020 { |
| 87 | compatible = "renesas,shdma-r8a73a4"; |
| 88 | reg = <0 0xe6700020 0 0x89e0>; |
| 89 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| 90 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| 91 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| 92 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| 93 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| 94 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| 95 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| 96 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| 97 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| 98 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| 99 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| 100 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| 101 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| 102 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| 103 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| 104 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| 105 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH |
| 106 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| 107 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| 108 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| 109 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
| 110 | interrupt-names = "error", |
| 111 | "ch0", "ch1", "ch2", "ch3", |
| 112 | "ch4", "ch5", "ch6", "ch7", |
| 113 | "ch8", "ch9", "ch10", "ch11", |
| 114 | "ch12", "ch13", "ch14", "ch15", |
| 115 | "ch16", "ch17", "ch18", "ch19"; |
| 116 | clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; |
| 117 | power-domains = <&pd_a3sp>; |
| 118 | }; |
| 119 | }; |
| 120 | |
| 121 | i2c5: i2c@e60b0000 { |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; |
| 124 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 125 | reg = <0 0xe60b0000 0 0x428>; |
| 126 | interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| 127 | clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; |
| 128 | power-domains = <&pd_a3sp>; |
| 129 | |
| 130 | status = "disabled"; |
| 131 | }; |
| 132 | |
| 133 | cmt1: timer@e6130000 { |
| 134 | compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; |
| 135 | reg = <0 0xe6130000 0 0x1004>; |
| 136 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 137 | clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; |
| 138 | clock-names = "fck"; |
| 139 | power-domains = <&pd_c5>; |
| 140 | |
| 141 | renesas,channels-mask = <0xff>; |
| 142 | |
| 143 | status = "disabled"; |
| 144 | }; |
| 145 | |
| 146 | irqc0: interrupt-controller@e61c0000 { |
| 147 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
| 148 | #interrupt-cells = <2>; |
| 149 | interrupt-controller; |
| 150 | reg = <0 0xe61c0000 0 0x200>; |
| 151 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 152 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 153 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| 154 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 155 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 156 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 158 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 159 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| 168 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| 169 | <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 170 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| 171 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| 172 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 173 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| 174 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
| 175 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
| 176 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, |
| 177 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
| 178 | <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, |
| 179 | <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, |
| 180 | <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
| 181 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
| 182 | <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 183 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
| 184 | power-domains = <&pd_c4>; |
| 185 | }; |
| 186 | |
| 187 | irqc1: interrupt-controller@e61c0200 { |
| 188 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
| 189 | #interrupt-cells = <2>; |
| 190 | interrupt-controller; |
| 191 | reg = <0 0xe61c0200 0 0x200>; |
| 192 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 195 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 196 | <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, |
| 197 | <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
| 198 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, |
| 199 | <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| 200 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 201 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 202 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 203 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| 204 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| 205 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| 206 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| 209 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| 211 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| 212 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| 213 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 214 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 215 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 216 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| 217 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 218 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
| 219 | power-domains = <&pd_c4>; |
| 220 | }; |
| 221 | |
| 222 | pfc: pfc@e6050000 { |
| 223 | compatible = "renesas,pfc-r8a73a4"; |
| 224 | reg = <0 0xe6050000 0 0x9000>; |
| 225 | gpio-controller; |
| 226 | #gpio-cells = <2>; |
| 227 | gpio-ranges = |
| 228 | <&pfc 0 0 31>, <&pfc 32 32 9>, |
| 229 | <&pfc 64 64 22>, <&pfc 96 96 31>, |
| 230 | <&pfc 128 128 7>, <&pfc 160 160 19>, |
| 231 | <&pfc 192 192 31>, <&pfc 224 224 27>, |
| 232 | <&pfc 256 256 28>, <&pfc 288 288 21>, |
| 233 | <&pfc 320 320 10>; |
| 234 | interrupts-extended = |
| 235 | <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, |
| 236 | <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, |
| 237 | <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, |
| 238 | <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, |
| 239 | <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, |
| 240 | <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, |
| 241 | <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, |
| 242 | <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, |
| 243 | <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, |
| 244 | <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, |
| 245 | <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, |
| 246 | <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, |
| 247 | <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, |
| 248 | <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, |
| 249 | <&irqc1 24 0>, <&irqc1 25 0>; |
| 250 | power-domains = <&pd_c5>; |
| 251 | }; |
| 252 | |
| 253 | thermal@e61f0000 { |
| 254 | compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; |
| 255 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
| 256 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; |
| 257 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 258 | clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; |
| 259 | power-domains = <&pd_c5>; |
| 260 | }; |
| 261 | |
| 262 | i2c0: i2c@e6500000 { |
| 263 | #address-cells = <1>; |
| 264 | #size-cells = <0>; |
| 265 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 266 | reg = <0 0xe6500000 0 0x428>; |
| 267 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| 268 | clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; |
| 269 | power-domains = <&pd_a3sp>; |
| 270 | status = "disabled"; |
| 271 | }; |
| 272 | |
| 273 | i2c1: i2c@e6510000 { |
| 274 | #address-cells = <1>; |
| 275 | #size-cells = <0>; |
| 276 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 277 | reg = <0 0xe6510000 0 0x428>; |
| 278 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| 279 | clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; |
| 280 | power-domains = <&pd_a3sp>; |
| 281 | status = "disabled"; |
| 282 | }; |
| 283 | |
| 284 | i2c2: i2c@e6520000 { |
| 285 | #address-cells = <1>; |
| 286 | #size-cells = <0>; |
| 287 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 288 | reg = <0 0xe6520000 0 0x428>; |
| 289 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| 290 | clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; |
| 291 | power-domains = <&pd_a3sp>; |
| 292 | status = "disabled"; |
| 293 | }; |
| 294 | |
| 295 | i2c3: i2c@e6530000 { |
| 296 | #address-cells = <1>; |
| 297 | #size-cells = <0>; |
| 298 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 299 | reg = <0 0xe6530000 0 0x428>; |
| 300 | interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| 301 | clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; |
| 302 | power-domains = <&pd_a3sp>; |
| 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
| 306 | i2c4: i2c@e6540000 { |
| 307 | #address-cells = <1>; |
| 308 | #size-cells = <0>; |
| 309 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 310 | reg = <0 0xe6540000 0 0x428>; |
| 311 | interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| 312 | clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; |
| 313 | power-domains = <&pd_a3sp>; |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | |
| 317 | i2c6: i2c@e6550000 { |
| 318 | #address-cells = <1>; |
| 319 | #size-cells = <0>; |
| 320 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 321 | reg = <0 0xe6550000 0 0x428>; |
| 322 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| 323 | clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; |
| 324 | power-domains = <&pd_a3sp>; |
| 325 | status = "disabled"; |
| 326 | }; |
| 327 | |
| 328 | i2c7: i2c@e6560000 { |
| 329 | #address-cells = <1>; |
| 330 | #size-cells = <0>; |
| 331 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 332 | reg = <0 0xe6560000 0 0x428>; |
| 333 | interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
| 334 | clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; |
| 335 | power-domains = <&pd_a3sp>; |
| 336 | status = "disabled"; |
| 337 | }; |
| 338 | |
| 339 | i2c8: i2c@e6570000 { |
| 340 | #address-cells = <1>; |
| 341 | #size-cells = <0>; |
| 342 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
| 343 | reg = <0 0xe6570000 0 0x428>; |
| 344 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 345 | clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; |
| 346 | power-domains = <&pd_a3sp>; |
| 347 | status = "disabled"; |
| 348 | }; |
| 349 | |
| 350 | scifb0: serial@e6c20000 { |
| 351 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 352 | reg = <0 0xe6c20000 0 0x100>; |
| 353 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| 354 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; |
| 355 | clock-names = "fck"; |
| 356 | power-domains = <&pd_a3sp>; |
| 357 | status = "disabled"; |
| 358 | }; |
| 359 | |
| 360 | scifb1: serial@e6c30000 { |
| 361 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 362 | reg = <0 0xe6c30000 0 0x100>; |
| 363 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
| 364 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; |
| 365 | clock-names = "fck"; |
| 366 | power-domains = <&pd_a3sp>; |
| 367 | status = "disabled"; |
| 368 | }; |
| 369 | |
| 370 | scifa0: serial@e6c40000 { |
| 371 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; |
| 372 | reg = <0 0xe6c40000 0 0x100>; |
| 373 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| 374 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; |
| 375 | clock-names = "fck"; |
| 376 | power-domains = <&pd_a3sp>; |
| 377 | status = "disabled"; |
| 378 | }; |
| 379 | |
| 380 | scifa1: serial@e6c50000 { |
| 381 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; |
| 382 | reg = <0 0xe6c50000 0 0x100>; |
| 383 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| 384 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; |
| 385 | clock-names = "fck"; |
| 386 | power-domains = <&pd_a3sp>; |
| 387 | status = "disabled"; |
| 388 | }; |
| 389 | |
| 390 | scifb2: serial@e6ce0000 { |
| 391 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 392 | reg = <0 0xe6ce0000 0 0x100>; |
| 393 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; |
| 395 | clock-names = "fck"; |
| 396 | power-domains = <&pd_a3sp>; |
| 397 | status = "disabled"; |
| 398 | }; |
| 399 | |
| 400 | scifb3: serial@e6cf0000 { |
| 401 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
| 402 | reg = <0 0xe6cf0000 0 0x100>; |
| 403 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
| 404 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; |
| 405 | clock-names = "fck"; |
| 406 | power-domains = <&pd_c4>; |
| 407 | status = "disabled"; |
| 408 | }; |
| 409 | |
| 410 | sdhi0: sd@ee100000 { |
| 411 | compatible = "renesas,sdhi-r8a73a4"; |
| 412 | reg = <0 0xee100000 0 0x100>; |
| 413 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| 414 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; |
| 415 | power-domains = <&pd_a3sp>; |
| 416 | cap-sd-highspeed; |
| 417 | status = "disabled"; |
| 418 | }; |
| 419 | |
| 420 | sdhi1: sd@ee120000 { |
| 421 | compatible = "renesas,sdhi-r8a73a4"; |
| 422 | reg = <0 0xee120000 0 0x100>; |
| 423 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| 424 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; |
| 425 | power-domains = <&pd_a3sp>; |
| 426 | cap-sd-highspeed; |
| 427 | status = "disabled"; |
| 428 | }; |
| 429 | |
| 430 | sdhi2: sd@ee140000 { |
| 431 | compatible = "renesas,sdhi-r8a73a4"; |
| 432 | reg = <0 0xee140000 0 0x100>; |
| 433 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| 434 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; |
| 435 | power-domains = <&pd_a3sp>; |
| 436 | cap-sd-highspeed; |
| 437 | status = "disabled"; |
| 438 | }; |
| 439 | |
| 440 | mmcif0: mmc@ee200000 { |
| 441 | compatible = "renesas,sh-mmcif"; |
| 442 | reg = <0 0xee200000 0 0x80>; |
| 443 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| 444 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; |
| 445 | power-domains = <&pd_a3sp>; |
| 446 | reg-io-width = <4>; |
| 447 | status = "disabled"; |
| 448 | }; |
| 449 | |
| 450 | mmcif1: mmc@ee220000 { |
| 451 | compatible = "renesas,sh-mmcif"; |
| 452 | reg = <0 0xee220000 0 0x80>; |
| 453 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| 454 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; |
| 455 | power-domains = <&pd_a3sp>; |
| 456 | reg-io-width = <4>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
| 460 | gic: interrupt-controller@f1001000 { |
| 461 | compatible = "arm,gic-400"; |
| 462 | #interrupt-cells = <3>; |
| 463 | #address-cells = <0>; |
| 464 | interrupt-controller; |
| 465 | reg = <0 0xf1001000 0 0x1000>, |
| 466 | <0 0xf1002000 0 0x1000>, |
| 467 | <0 0xf1004000 0 0x2000>, |
| 468 | <0 0xf1006000 0 0x2000>; |
| 469 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 470 | }; |
| 471 | |
| 472 | bsc: bus@fec10000 { |
| 473 | compatible = "renesas,bsc-r8a73a4", "renesas,bsc", |
| 474 | "simple-pm-bus"; |
| 475 | #address-cells = <1>; |
| 476 | #size-cells = <1>; |
| 477 | ranges = <0 0 0 0x20000000>; |
| 478 | reg = <0 0xfec10000 0 0x400>; |
| 479 | clocks = <&zb_clk>; |
| 480 | power-domains = <&pd_c4>; |
| 481 | }; |
| 482 | |
| 483 | clocks { |
| 484 | #address-cells = <2>; |
| 485 | #size-cells = <2>; |
| 486 | ranges; |
| 487 | |
| 488 | /* External root clocks */ |
| 489 | extalr_clk: extalr_clk { |
| 490 | compatible = "fixed-clock"; |
| 491 | #clock-cells = <0>; |
| 492 | clock-frequency = <32768>; |
| 493 | clock-output-names = "extalr"; |
| 494 | }; |
| 495 | extal1_clk: extal1_clk { |
| 496 | compatible = "fixed-clock"; |
| 497 | #clock-cells = <0>; |
| 498 | clock-frequency = <25000000>; |
| 499 | clock-output-names = "extal1"; |
| 500 | }; |
| 501 | extal2_clk: extal2_clk { |
| 502 | compatible = "fixed-clock"; |
| 503 | #clock-cells = <0>; |
| 504 | clock-frequency = <48000000>; |
| 505 | clock-output-names = "extal2"; |
| 506 | }; |
| 507 | fsiack_clk: fsiack_clk { |
| 508 | compatible = "fixed-clock"; |
| 509 | #clock-cells = <0>; |
| 510 | /* This value must be overridden by the board. */ |
| 511 | clock-frequency = <0>; |
| 512 | clock-output-names = "fsiack"; |
| 513 | }; |
| 514 | fsibck_clk: fsibck_clk { |
| 515 | compatible = "fixed-clock"; |
| 516 | #clock-cells = <0>; |
| 517 | /* This value must be overridden by the board. */ |
| 518 | clock-frequency = <0>; |
| 519 | clock-output-names = "fsibck"; |
| 520 | }; |
| 521 | |
| 522 | /* Special CPG clocks */ |
| 523 | cpg_clocks: cpg_clocks@e6150000 { |
| 524 | compatible = "renesas,r8a73a4-cpg-clocks"; |
| 525 | reg = <0 0xe6150000 0 0x10000>; |
| 526 | clocks = <&extal1_clk>, <&extal2_clk>; |
| 527 | #clock-cells = <1>; |
| 528 | clock-output-names = "main", "pll0", "pll1", "pll2", |
| 529 | "pll2s", "pll2h", "z", "z2", |
| 530 | "i", "m3", "b", "m1", "m2", |
| 531 | "zx", "zs", "hp"; |
| 532 | }; |
| 533 | |
| 534 | /* Variable factor clocks (DIV6) */ |
| 535 | zb_clk: zb_clk@e6150010 { |
| 536 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 537 | reg = <0 0xe6150010 0 4>; |
| 538 | clocks = <&pll1_div2_clk>, <0>, |
| 539 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; |
| 540 | #clock-cells = <0>; |
| 541 | clock-output-names = "zb"; |
| 542 | }; |
| 543 | sdhi0_clk: sdhi0_clk@e6150074 { |
| 544 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 545 | reg = <0 0xe6150074 0 4>; |
| 546 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 547 | <0>, <&extal2_clk>; |
| 548 | #clock-cells = <0>; |
| 549 | clock-output-names = "sdhi0ck"; |
| 550 | }; |
| 551 | sdhi1_clk: sdhi1_clk@e6150078 { |
| 552 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 553 | reg = <0 0xe6150078 0 4>; |
| 554 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 555 | <0>, <&extal2_clk>; |
| 556 | #clock-cells = <0>; |
| 557 | clock-output-names = "sdhi1ck"; |
| 558 | }; |
| 559 | sdhi2_clk: sdhi2_clk@e615007c { |
| 560 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 561 | reg = <0 0xe615007c 0 4>; |
| 562 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 563 | <0>, <&extal2_clk>; |
| 564 | #clock-cells = <0>; |
| 565 | clock-output-names = "sdhi2ck"; |
| 566 | }; |
| 567 | mmc0_clk: mmc0_clk@e6150240 { |
| 568 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 569 | reg = <0 0xe6150240 0 4>; |
| 570 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 571 | <0>, <&extal2_clk>; |
| 572 | #clock-cells = <0>; |
| 573 | clock-output-names = "mmc0"; |
| 574 | }; |
| 575 | mmc1_clk: mmc1_clk@e6150244 { |
| 576 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 577 | reg = <0 0xe6150244 0 4>; |
| 578 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 579 | <0>, <&extal2_clk>; |
| 580 | #clock-cells = <0>; |
| 581 | clock-output-names = "mmc1"; |
| 582 | }; |
| 583 | vclk1_clk: vclk1_clk@e6150008 { |
| 584 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 585 | reg = <0 0xe6150008 0 4>; |
| 586 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 587 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 588 | <&extalr_clk>, <0>, <0>; |
| 589 | #clock-cells = <0>; |
| 590 | clock-output-names = "vclk1"; |
| 591 | }; |
| 592 | vclk2_clk: vclk2_clk@e615000c { |
| 593 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 594 | reg = <0 0xe615000c 0 4>; |
| 595 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 596 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 597 | <&extalr_clk>, <0>, <0>; |
| 598 | #clock-cells = <0>; |
| 599 | clock-output-names = "vclk2"; |
| 600 | }; |
| 601 | vclk3_clk: vclk3_clk@e615001c { |
| 602 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 603 | reg = <0 0xe615001c 0 4>; |
| 604 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 605 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 606 | <&extalr_clk>, <0>, <0>; |
| 607 | #clock-cells = <0>; |
| 608 | clock-output-names = "vclk3"; |
| 609 | }; |
| 610 | vclk4_clk: vclk4_clk@e6150014 { |
| 611 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 612 | reg = <0 0xe6150014 0 4>; |
| 613 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 614 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 615 | <&extalr_clk>, <0>, <0>; |
| 616 | #clock-cells = <0>; |
| 617 | clock-output-names = "vclk4"; |
| 618 | }; |
| 619 | vclk5_clk: vclk5_clk@e6150034 { |
| 620 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 621 | reg = <0 0xe6150034 0 4>; |
| 622 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 623 | <0>, <&extal2_clk>, <&main_div2_clk>, |
| 624 | <&extalr_clk>, <0>, <0>; |
| 625 | #clock-cells = <0>; |
| 626 | clock-output-names = "vclk5"; |
| 627 | }; |
| 628 | fsia_clk: fsia_clk@e6150018 { |
| 629 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 630 | reg = <0 0xe6150018 0 4>; |
| 631 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 632 | <&fsiack_clk>, <0>; |
| 633 | #clock-cells = <0>; |
| 634 | clock-output-names = "fsia"; |
| 635 | }; |
| 636 | fsib_clk: fsib_clk@e6150090 { |
| 637 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 638 | reg = <0 0xe6150090 0 4>; |
| 639 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 640 | <&fsibck_clk>, <0>; |
| 641 | #clock-cells = <0>; |
| 642 | clock-output-names = "fsib"; |
| 643 | }; |
| 644 | mp_clk: mp_clk@e6150080 { |
| 645 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 646 | reg = <0 0xe6150080 0 4>; |
| 647 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 648 | <&extal2_clk>, <&extal2_clk>; |
| 649 | #clock-cells = <0>; |
| 650 | clock-output-names = "mp"; |
| 651 | }; |
| 652 | m4_clk: m4_clk@e6150098 { |
| 653 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 654 | reg = <0 0xe6150098 0 4>; |
| 655 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; |
| 656 | #clock-cells = <0>; |
| 657 | clock-output-names = "m4"; |
| 658 | }; |
| 659 | hsi_clk: hsi_clk@e615026c { |
| 660 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 661 | reg = <0 0xe615026c 0 4>; |
| 662 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, |
| 663 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; |
| 664 | #clock-cells = <0>; |
| 665 | clock-output-names = "hsi"; |
| 666 | }; |
| 667 | spuv_clk: spuv_clk@e6150094 { |
| 668 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 669 | reg = <0 0xe6150094 0 4>; |
| 670 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 671 | <&extal2_clk>, <&extal2_clk>; |
| 672 | #clock-cells = <0>; |
| 673 | clock-output-names = "spuv"; |
| 674 | }; |
| 675 | |
| 676 | /* Fixed factor clocks */ |
| 677 | main_div2_clk: main_div2_clk { |
| 678 | compatible = "fixed-factor-clock"; |
| 679 | clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; |
| 680 | #clock-cells = <0>; |
| 681 | clock-div = <2>; |
| 682 | clock-mult = <1>; |
| 683 | clock-output-names = "main_div2"; |
| 684 | }; |
| 685 | pll0_div2_clk: pll0_div2_clk { |
| 686 | compatible = "fixed-factor-clock"; |
| 687 | clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; |
| 688 | #clock-cells = <0>; |
| 689 | clock-div = <2>; |
| 690 | clock-mult = <1>; |
| 691 | clock-output-names = "pll0_div2"; |
| 692 | }; |
| 693 | pll1_div2_clk: pll1_div2_clk { |
| 694 | compatible = "fixed-factor-clock"; |
| 695 | clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; |
| 696 | #clock-cells = <0>; |
| 697 | clock-div = <2>; |
| 698 | clock-mult = <1>; |
| 699 | clock-output-names = "pll1_div2"; |
| 700 | }; |
| 701 | extal1_div2_clk: extal1_div2_clk { |
| 702 | compatible = "fixed-factor-clock"; |
| 703 | clocks = <&extal1_clk>; |
| 704 | #clock-cells = <0>; |
| 705 | clock-div = <2>; |
| 706 | clock-mult = <1>; |
| 707 | clock-output-names = "extal1_div2"; |
| 708 | }; |
| 709 | |
| 710 | /* Gate clocks */ |
| 711 | mstp2_clks: mstp2_clks@e6150138 { |
| 712 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 713 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 714 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 715 | <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; |
| 716 | #clock-cells = <1>; |
| 717 | clock-indices = < |
| 718 | R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 |
| 719 | R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 |
| 720 | R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 |
| 721 | R8A73A4_CLK_DMAC |
| 722 | >; |
| 723 | clock-output-names = |
| 724 | "scifa0", "scifa1", "scifb0", "scifb1", |
| 725 | "scifb2", "scifb3", "dmac"; |
| 726 | }; |
| 727 | mstp3_clks: mstp3_clks@e615013c { |
| 728 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 729 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 730 | clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, |
| 731 | <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, |
| 732 | <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, |
| 733 | <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks |
| 734 | R8A73A4_CLK_HP>, <&cpg_clocks |
| 735 | R8A73A4_CLK_HP>, <&extalr_clk>; |
| 736 | #clock-cells = <1>; |
| 737 | clock-indices = < |
| 738 | R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 |
| 739 | R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 |
| 740 | R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 |
| 741 | R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 |
| 742 | R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 |
| 743 | R8A73A4_CLK_CMT1 |
| 744 | >; |
| 745 | clock-output-names = |
| 746 | "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", |
| 747 | "mmcif0", "iic6", "iic7", "iic0", "iic1", |
| 748 | "cmt1"; |
| 749 | }; |
| 750 | mstp4_clks: mstp4_clks@e6150140 { |
| 751 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 752 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 753 | clocks = <&main_div2_clk>, <&main_div2_clk>, |
| 754 | <&cpg_clocks R8A73A4_CLK_HP>, |
| 755 | <&cpg_clocks R8A73A4_CLK_HP>; |
| 756 | #clock-cells = <1>; |
| 757 | clock-indices = < |
| 758 | R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 |
| 759 | R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 |
| 760 | >; |
| 761 | clock-output-names = |
| 762 | "irqc", "iic5", "iic4", "iic3"; |
| 763 | }; |
| 764 | mstp5_clks: mstp5_clks@e6150144 { |
| 765 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 766 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
| 767 | clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; |
| 768 | #clock-cells = <1>; |
| 769 | clock-indices = < |
| 770 | R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 |
| 771 | >; |
| 772 | clock-output-names = |
| 773 | "thermal", "iic8"; |
| 774 | }; |
| 775 | }; |
| 776 | |
| 777 | sysc: system-controller@e6180000 { |
| 778 | compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; |
| 779 | reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; |
| 780 | |
| 781 | pm-domains { |
| 782 | pd_c5: c5 { |
| 783 | #address-cells = <1>; |
| 784 | #size-cells = <0>; |
| 785 | #power-domain-cells = <0>; |
| 786 | |
| 787 | pd_c4: c4@0 { |
| 788 | reg = <0>; |
| 789 | #address-cells = <1>; |
| 790 | #size-cells = <0>; |
| 791 | #power-domain-cells = <0>; |
| 792 | |
| 793 | pd_a3sg: a3sg@16 { |
| 794 | reg = <16>; |
| 795 | #power-domain-cells = <0>; |
| 796 | }; |
| 797 | |
| 798 | pd_a3ex: a3ex@17 { |
| 799 | reg = <17>; |
| 800 | #power-domain-cells = <0>; |
| 801 | }; |
| 802 | |
| 803 | pd_a3sp: a3sp@18 { |
| 804 | reg = <18>; |
| 805 | #address-cells = <1>; |
| 806 | #size-cells = <0>; |
| 807 | #power-domain-cells = <0>; |
| 808 | |
| 809 | pd_a2us: a2us@19 { |
| 810 | reg = <19>; |
| 811 | #power-domain-cells = <0>; |
| 812 | }; |
| 813 | }; |
| 814 | |
| 815 | pd_a3sm: a3sm@20 { |
| 816 | reg = <20>; |
| 817 | #address-cells = <1>; |
| 818 | #size-cells = <0>; |
| 819 | #power-domain-cells = <0>; |
| 820 | |
| 821 | pd_a2sl: a2sl@21 { |
| 822 | reg = <21>; |
| 823 | #power-domain-cells = <0>; |
| 824 | }; |
| 825 | }; |
| 826 | |
| 827 | pd_a3km: a3km@22 { |
| 828 | reg = <22>; |
| 829 | #address-cells = <1>; |
| 830 | #size-cells = <0>; |
| 831 | #power-domain-cells = <0>; |
| 832 | |
| 833 | pd_a2kl: a2kl@23 { |
| 834 | reg = <23>; |
| 835 | #power-domain-cells = <0>; |
| 836 | }; |
| 837 | }; |
| 838 | }; |
| 839 | |
| 840 | pd_c4ma: c4ma@1 { |
| 841 | reg = <1>; |
| 842 | #power-domain-cells = <0>; |
| 843 | }; |
| 844 | |
| 845 | pd_c4cl: c4cl@2 { |
| 846 | reg = <2>; |
| 847 | #power-domain-cells = <0>; |
| 848 | }; |
| 849 | |
| 850 | pd_d4: d4@3 { |
| 851 | reg = <3>; |
| 852 | #power-domain-cells = <0>; |
| 853 | }; |
| 854 | |
| 855 | pd_a4bc: a4bc@4 { |
| 856 | reg = <4>; |
| 857 | #address-cells = <1>; |
| 858 | #size-cells = <0>; |
| 859 | #power-domain-cells = <0>; |
| 860 | |
| 861 | pd_a3bc: a3bc@5 { |
| 862 | reg = <5>; |
| 863 | #power-domain-cells = <0>; |
| 864 | }; |
| 865 | }; |
| 866 | |
| 867 | pd_a4l: a4l@6 { |
| 868 | reg = <6>; |
| 869 | #power-domain-cells = <0>; |
| 870 | }; |
| 871 | |
| 872 | pd_a4lc: a4lc@7 { |
| 873 | reg = <7>; |
| 874 | #power-domain-cells = <0>; |
| 875 | }; |
| 876 | |
| 877 | pd_a4mp: a4mp@8 { |
| 878 | reg = <8>; |
| 879 | #address-cells = <1>; |
| 880 | #size-cells = <0>; |
| 881 | #power-domain-cells = <0>; |
| 882 | |
| 883 | pd_a3mp: a3mp@9 { |
| 884 | reg = <9>; |
| 885 | #power-domain-cells = <0>; |
| 886 | }; |
| 887 | |
| 888 | pd_a3vc: a3vc@10 { |
| 889 | reg = <10>; |
| 890 | #power-domain-cells = <0>; |
| 891 | }; |
| 892 | }; |
| 893 | |
| 894 | pd_a4sf: a4sf@11 { |
| 895 | reg = <11>; |
| 896 | #power-domain-cells = <0>; |
| 897 | }; |
| 898 | |
| 899 | pd_a3r: a3r@12 { |
| 900 | reg = <12>; |
| 901 | #address-cells = <1>; |
| 902 | #size-cells = <0>; |
| 903 | #power-domain-cells = <0>; |
| 904 | |
| 905 | pd_a2rv: a2rv@13 { |
| 906 | reg = <13>; |
| 907 | #power-domain-cells = <0>; |
| 908 | }; |
| 909 | |
| 910 | pd_a2is: a2is@14 { |
| 911 | reg = <14>; |
| 912 | #power-domain-cells = <0>; |
| 913 | }; |
| 914 | }; |
| 915 | }; |
| 916 | }; |
| 917 | }; |
| 918 | }; |