| 1 | /* |
| 2 | * linux/arch/arm/kernel/bios32.c |
| 3 | * |
| 4 | * PCI bios-type initialisation for PCI machines |
| 5 | * |
| 6 | * Bits taken from various places. |
| 7 | */ |
| 8 | #include <linux/export.h> |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/slab.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/io.h> |
| 14 | |
| 15 | #include <asm/mach-types.h> |
| 16 | #include <asm/mach/map.h> |
| 17 | #include <asm/mach/pci.h> |
| 18 | |
| 19 | static int debug_pci; |
| 20 | |
| 21 | /* |
| 22 | * We can't use pci_get_device() here since we are |
| 23 | * called from interrupt context. |
| 24 | */ |
| 25 | static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) |
| 26 | { |
| 27 | struct pci_dev *dev; |
| 28 | |
| 29 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 30 | u16 status; |
| 31 | |
| 32 | /* |
| 33 | * ignore host bridge - we handle |
| 34 | * that separately |
| 35 | */ |
| 36 | if (dev->bus->number == 0 && dev->devfn == 0) |
| 37 | continue; |
| 38 | |
| 39 | pci_read_config_word(dev, PCI_STATUS, &status); |
| 40 | if (status == 0xffff) |
| 41 | continue; |
| 42 | |
| 43 | if ((status & status_mask) == 0) |
| 44 | continue; |
| 45 | |
| 46 | /* clear the status errors */ |
| 47 | pci_write_config_word(dev, PCI_STATUS, status & status_mask); |
| 48 | |
| 49 | if (warn) |
| 50 | printk("(%s: %04X) ", pci_name(dev), status); |
| 51 | } |
| 52 | |
| 53 | list_for_each_entry(dev, &bus->devices, bus_list) |
| 54 | if (dev->subordinate) |
| 55 | pcibios_bus_report_status(dev->subordinate, status_mask, warn); |
| 56 | } |
| 57 | |
| 58 | void pcibios_report_status(u_int status_mask, int warn) |
| 59 | { |
| 60 | struct pci_bus *bus; |
| 61 | |
| 62 | list_for_each_entry(bus, &pci_root_buses, node) |
| 63 | pcibios_bus_report_status(bus, status_mask, warn); |
| 64 | } |
| 65 | |
| 66 | /* |
| 67 | * We don't use this to fix the device, but initialisation of it. |
| 68 | * It's not the correct use for this, but it works. |
| 69 | * Note that the arbiter/ISA bridge appears to be buggy, specifically in |
| 70 | * the following area: |
| 71 | * 1. park on CPU |
| 72 | * 2. ISA bridge ping-pong |
| 73 | * 3. ISA bridge master handling of target RETRY |
| 74 | * |
| 75 | * Bug 3 is responsible for the sound DMA grinding to a halt. We now |
| 76 | * live with bug 2. |
| 77 | */ |
| 78 | static void pci_fixup_83c553(struct pci_dev *dev) |
| 79 | { |
| 80 | /* |
| 81 | * Set memory region to start at address 0, and enable IO |
| 82 | */ |
| 83 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 84 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); |
| 85 | |
| 86 | dev->resource[0].end -= dev->resource[0].start; |
| 87 | dev->resource[0].start = 0; |
| 88 | |
| 89 | /* |
| 90 | * All memory requests from ISA to be channelled to PCI |
| 91 | */ |
| 92 | pci_write_config_byte(dev, 0x48, 0xff); |
| 93 | |
| 94 | /* |
| 95 | * Enable ping-pong on bus master to ISA bridge transactions. |
| 96 | * This improves the sound DMA substantially. The fixed |
| 97 | * priority arbiter also helps (see below). |
| 98 | */ |
| 99 | pci_write_config_byte(dev, 0x42, 0x01); |
| 100 | |
| 101 | /* |
| 102 | * Enable PCI retry |
| 103 | */ |
| 104 | pci_write_config_byte(dev, 0x40, 0x22); |
| 105 | |
| 106 | /* |
| 107 | * We used to set the arbiter to "park on last master" (bit |
| 108 | * 1 set), but unfortunately the CyberPro does not park the |
| 109 | * bus. We must therefore park on CPU. Unfortunately, this |
| 110 | * may trigger yet another bug in the 553. |
| 111 | */ |
| 112 | pci_write_config_byte(dev, 0x83, 0x02); |
| 113 | |
| 114 | /* |
| 115 | * Make the ISA DMA request lowest priority, and disable |
| 116 | * rotating priorities completely. |
| 117 | */ |
| 118 | pci_write_config_byte(dev, 0x80, 0x11); |
| 119 | pci_write_config_byte(dev, 0x81, 0x00); |
| 120 | |
| 121 | /* |
| 122 | * Route INTA input to IRQ 11, and set IRQ11 to be level |
| 123 | * sensitive. |
| 124 | */ |
| 125 | pci_write_config_word(dev, 0x44, 0xb000); |
| 126 | outb(0x08, 0x4d1); |
| 127 | } |
| 128 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); |
| 129 | |
| 130 | static void pci_fixup_unassign(struct pci_dev *dev) |
| 131 | { |
| 132 | dev->resource[0].end -= dev->resource[0].start; |
| 133 | dev->resource[0].start = 0; |
| 134 | } |
| 135 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); |
| 136 | |
| 137 | /* |
| 138 | * Prevent the PCI layer from seeing the resources allocated to this device |
| 139 | * if it is the host bridge by marking it as such. These resources are of |
| 140 | * no consequence to the PCI layer (they are handled elsewhere). |
| 141 | */ |
| 142 | static void pci_fixup_dec21285(struct pci_dev *dev) |
| 143 | { |
| 144 | int i; |
| 145 | |
| 146 | if (dev->devfn == 0) { |
| 147 | dev->class &= 0xff; |
| 148 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; |
| 149 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 150 | dev->resource[i].start = 0; |
| 151 | dev->resource[i].end = 0; |
| 152 | dev->resource[i].flags = 0; |
| 153 | } |
| 154 | } |
| 155 | } |
| 156 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); |
| 157 | |
| 158 | /* |
| 159 | * PCI IDE controllers use non-standard I/O port decoding, respect it. |
| 160 | */ |
| 161 | static void pci_fixup_ide_bases(struct pci_dev *dev) |
| 162 | { |
| 163 | struct resource *r; |
| 164 | int i; |
| 165 | |
| 166 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) |
| 167 | return; |
| 168 | |
| 169 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 170 | r = dev->resource + i; |
| 171 | if ((r->start & ~0x80) == 0x374) { |
| 172 | r->start |= 2; |
| 173 | r->end = r->start; |
| 174 | } |
| 175 | } |
| 176 | } |
| 177 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); |
| 178 | |
| 179 | /* |
| 180 | * Put the DEC21142 to sleep |
| 181 | */ |
| 182 | static void pci_fixup_dec21142(struct pci_dev *dev) |
| 183 | { |
| 184 | pci_write_config_dword(dev, 0x40, 0x80000000); |
| 185 | } |
| 186 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); |
| 187 | |
| 188 | /* |
| 189 | * The CY82C693 needs some rather major fixups to ensure that it does |
| 190 | * the right thing. Idea from the Alpha people, with a few additions. |
| 191 | * |
| 192 | * We ensure that the IDE base registers are set to 1f0/3f4 for the |
| 193 | * primary bus, and 170/374 for the secondary bus. Also, hide them |
| 194 | * from the PCI subsystem view as well so we won't try to perform |
| 195 | * our own auto-configuration on them. |
| 196 | * |
| 197 | * In addition, we ensure that the PCI IDE interrupts are routed to |
| 198 | * IRQ 14 and IRQ 15 respectively. |
| 199 | * |
| 200 | * The above gets us to a point where the IDE on this device is |
| 201 | * functional. However, The CY82C693U _does not work_ in bus |
| 202 | * master mode without locking the PCI bus solid. |
| 203 | */ |
| 204 | static void pci_fixup_cy82c693(struct pci_dev *dev) |
| 205 | { |
| 206 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { |
| 207 | u32 base0, base1; |
| 208 | |
| 209 | if (dev->class & 0x80) { /* primary */ |
| 210 | base0 = 0x1f0; |
| 211 | base1 = 0x3f4; |
| 212 | } else { /* secondary */ |
| 213 | base0 = 0x170; |
| 214 | base1 = 0x374; |
| 215 | } |
| 216 | |
| 217 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, |
| 218 | base0 | PCI_BASE_ADDRESS_SPACE_IO); |
| 219 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, |
| 220 | base1 | PCI_BASE_ADDRESS_SPACE_IO); |
| 221 | |
| 222 | dev->resource[0].start = 0; |
| 223 | dev->resource[0].end = 0; |
| 224 | dev->resource[0].flags = 0; |
| 225 | |
| 226 | dev->resource[1].start = 0; |
| 227 | dev->resource[1].end = 0; |
| 228 | dev->resource[1].flags = 0; |
| 229 | } else if (PCI_FUNC(dev->devfn) == 0) { |
| 230 | /* |
| 231 | * Setup IDE IRQ routing. |
| 232 | */ |
| 233 | pci_write_config_byte(dev, 0x4b, 14); |
| 234 | pci_write_config_byte(dev, 0x4c, 15); |
| 235 | |
| 236 | /* |
| 237 | * Disable FREQACK handshake, enable USB. |
| 238 | */ |
| 239 | pci_write_config_byte(dev, 0x4d, 0x41); |
| 240 | |
| 241 | /* |
| 242 | * Enable PCI retry, and PCI post-write buffer. |
| 243 | */ |
| 244 | pci_write_config_byte(dev, 0x44, 0x17); |
| 245 | |
| 246 | /* |
| 247 | * Enable ISA master and DMA post write buffering. |
| 248 | */ |
| 249 | pci_write_config_byte(dev, 0x45, 0x03); |
| 250 | } |
| 251 | } |
| 252 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); |
| 253 | |
| 254 | static void pci_fixup_it8152(struct pci_dev *dev) |
| 255 | { |
| 256 | int i; |
| 257 | /* fixup for ITE 8152 devices */ |
| 258 | /* FIXME: add defines for class 0x68000 and 0x80103 */ |
| 259 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || |
| 260 | dev->class == 0x68000 || |
| 261 | dev->class == 0x80103) { |
| 262 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 263 | dev->resource[i].start = 0; |
| 264 | dev->resource[i].end = 0; |
| 265 | dev->resource[i].flags = 0; |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); |
| 270 | |
| 271 | /* |
| 272 | * If the bus contains any of these devices, then we must not turn on |
| 273 | * parity checking of any kind. Currently this is CyberPro 20x0 only. |
| 274 | */ |
| 275 | static inline int pdev_bad_for_parity(struct pci_dev *dev) |
| 276 | { |
| 277 | return ((dev->vendor == PCI_VENDOR_ID_INTERG && |
| 278 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || |
| 279 | dev->device == PCI_DEVICE_ID_INTERG_2010)) || |
| 280 | (dev->vendor == PCI_VENDOR_ID_ITE && |
| 281 | dev->device == PCI_DEVICE_ID_ITE_8152)); |
| 282 | |
| 283 | } |
| 284 | |
| 285 | /* |
| 286 | * pcibios_fixup_bus - Called after each bus is probed, |
| 287 | * but before its children are examined. |
| 288 | */ |
| 289 | void pcibios_fixup_bus(struct pci_bus *bus) |
| 290 | { |
| 291 | struct pci_dev *dev; |
| 292 | u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; |
| 293 | |
| 294 | /* |
| 295 | * Walk the devices on this bus, working out what we can |
| 296 | * and can't support. |
| 297 | */ |
| 298 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 299 | u16 status; |
| 300 | |
| 301 | pci_read_config_word(dev, PCI_STATUS, &status); |
| 302 | |
| 303 | /* |
| 304 | * If any device on this bus does not support fast back |
| 305 | * to back transfers, then the bus as a whole is not able |
| 306 | * to support them. Having fast back to back transfers |
| 307 | * on saves us one PCI cycle per transaction. |
| 308 | */ |
| 309 | if (!(status & PCI_STATUS_FAST_BACK)) |
| 310 | features &= ~PCI_COMMAND_FAST_BACK; |
| 311 | |
| 312 | if (pdev_bad_for_parity(dev)) |
| 313 | features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
| 314 | |
| 315 | switch (dev->class >> 8) { |
| 316 | case PCI_CLASS_BRIDGE_PCI: |
| 317 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); |
| 318 | status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; |
| 319 | status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); |
| 320 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); |
| 321 | break; |
| 322 | |
| 323 | case PCI_CLASS_BRIDGE_CARDBUS: |
| 324 | pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); |
| 325 | status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; |
| 326 | pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); |
| 327 | break; |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * Now walk the devices again, this time setting them up. |
| 333 | */ |
| 334 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 335 | u16 cmd; |
| 336 | |
| 337 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 338 | cmd |= features; |
| 339 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 340 | |
| 341 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, |
| 342 | L1_CACHE_BYTES >> 2); |
| 343 | } |
| 344 | |
| 345 | /* |
| 346 | * Propagate the flags to the PCI bridge. |
| 347 | */ |
| 348 | if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
| 349 | if (features & PCI_COMMAND_FAST_BACK) |
| 350 | bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; |
| 351 | if (features & PCI_COMMAND_PARITY) |
| 352 | bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; |
| 353 | } |
| 354 | |
| 355 | /* |
| 356 | * Report what we did for this bus |
| 357 | */ |
| 358 | pr_info("PCI: bus%d: Fast back to back transfers %sabled\n", |
| 359 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); |
| 360 | } |
| 361 | EXPORT_SYMBOL(pcibios_fixup_bus); |
| 362 | |
| 363 | /* |
| 364 | * Swizzle the device pin each time we cross a bridge. If a platform does |
| 365 | * not provide a swizzle function, we perform the standard PCI swizzling. |
| 366 | * |
| 367 | * The default swizzling walks up the bus tree one level at a time, applying |
| 368 | * the standard swizzle function at each step, stopping when it finds the PCI |
| 369 | * root bus. This will return the slot number of the bridge device on the |
| 370 | * root bus and the interrupt pin on that device which should correspond |
| 371 | * with the downstream device interrupt. |
| 372 | * |
| 373 | * Platforms may override this, in which case the slot and pin returned |
| 374 | * depend entirely on the platform code. However, please note that the |
| 375 | * PCI standard swizzle is implemented on plug-in cards and Cardbus based |
| 376 | * PCI extenders, so it can not be ignored. |
| 377 | */ |
| 378 | static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin) |
| 379 | { |
| 380 | struct pci_sys_data *sys = dev->sysdata; |
| 381 | int slot, oldpin = *pin; |
| 382 | |
| 383 | if (sys->swizzle) |
| 384 | slot = sys->swizzle(dev, pin); |
| 385 | else |
| 386 | slot = pci_common_swizzle(dev, pin); |
| 387 | |
| 388 | if (debug_pci) |
| 389 | printk("PCI: %s swizzling pin %d => pin %d slot %d\n", |
| 390 | pci_name(dev), oldpin, *pin, slot); |
| 391 | |
| 392 | return slot; |
| 393 | } |
| 394 | |
| 395 | /* |
| 396 | * Map a slot/pin to an IRQ. |
| 397 | */ |
| 398 | static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| 399 | { |
| 400 | struct pci_sys_data *sys = dev->sysdata; |
| 401 | int irq = -1; |
| 402 | |
| 403 | if (sys->map_irq) |
| 404 | irq = sys->map_irq(dev, slot, pin); |
| 405 | |
| 406 | if (debug_pci) |
| 407 | printk("PCI: %s mapping slot %d pin %d => irq %d\n", |
| 408 | pci_name(dev), slot, pin, irq); |
| 409 | |
| 410 | return irq; |
| 411 | } |
| 412 | |
| 413 | static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) |
| 414 | { |
| 415 | int ret; |
| 416 | struct resource_entry *window; |
| 417 | |
| 418 | if (list_empty(&sys->resources)) { |
| 419 | pci_add_resource_offset(&sys->resources, |
| 420 | &iomem_resource, sys->mem_offset); |
| 421 | } |
| 422 | |
| 423 | resource_list_for_each_entry(window, &sys->resources) |
| 424 | if (resource_type(window->res) == IORESOURCE_IO) |
| 425 | return 0; |
| 426 | |
| 427 | sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; |
| 428 | sys->io_res.end = (busnr + 1) * SZ_64K - 1; |
| 429 | sys->io_res.flags = IORESOURCE_IO; |
| 430 | sys->io_res.name = sys->io_res_name; |
| 431 | sprintf(sys->io_res_name, "PCI%d I/O", busnr); |
| 432 | |
| 433 | ret = request_resource(&ioport_resource, &sys->io_res); |
| 434 | if (ret) { |
| 435 | pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); |
| 436 | return ret; |
| 437 | } |
| 438 | pci_add_resource_offset(&sys->resources, &sys->io_res, |
| 439 | sys->io_offset); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, |
| 445 | struct list_head *head) |
| 446 | { |
| 447 | struct pci_sys_data *sys = NULL; |
| 448 | int ret; |
| 449 | int nr, busnr; |
| 450 | |
| 451 | for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { |
| 452 | sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); |
| 453 | if (WARN(!sys, "PCI: unable to allocate sys data!")) |
| 454 | break; |
| 455 | |
| 456 | sys->busnr = busnr; |
| 457 | sys->swizzle = hw->swizzle; |
| 458 | sys->map_irq = hw->map_irq; |
| 459 | INIT_LIST_HEAD(&sys->resources); |
| 460 | |
| 461 | if (hw->private_data) |
| 462 | sys->private_data = hw->private_data[nr]; |
| 463 | |
| 464 | ret = hw->setup(nr, sys); |
| 465 | |
| 466 | if (ret > 0) { |
| 467 | struct pci_host_bridge *host_bridge; |
| 468 | |
| 469 | ret = pcibios_init_resources(nr, sys); |
| 470 | if (ret) { |
| 471 | kfree(sys); |
| 472 | break; |
| 473 | } |
| 474 | |
| 475 | if (hw->scan) |
| 476 | sys->bus = hw->scan(nr, sys); |
| 477 | else |
| 478 | sys->bus = pci_scan_root_bus_msi(parent, |
| 479 | sys->busnr, hw->ops, sys, |
| 480 | &sys->resources, hw->msi_ctrl); |
| 481 | |
| 482 | if (WARN(!sys->bus, "PCI: unable to scan bus!")) { |
| 483 | kfree(sys); |
| 484 | break; |
| 485 | } |
| 486 | |
| 487 | busnr = sys->bus->busn_res.end + 1; |
| 488 | |
| 489 | list_add(&sys->node, head); |
| 490 | |
| 491 | host_bridge = pci_find_host_bridge(sys->bus); |
| 492 | host_bridge->align_resource = hw->align_resource; |
| 493 | } else { |
| 494 | kfree(sys); |
| 495 | if (ret < 0) |
| 496 | break; |
| 497 | } |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | void pci_common_init_dev(struct device *parent, struct hw_pci *hw) |
| 502 | { |
| 503 | struct pci_sys_data *sys; |
| 504 | LIST_HEAD(head); |
| 505 | |
| 506 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
| 507 | if (hw->preinit) |
| 508 | hw->preinit(); |
| 509 | pcibios_init_hw(parent, hw, &head); |
| 510 | if (hw->postinit) |
| 511 | hw->postinit(); |
| 512 | |
| 513 | pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); |
| 514 | |
| 515 | list_for_each_entry(sys, &head, node) { |
| 516 | struct pci_bus *bus = sys->bus; |
| 517 | |
| 518 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
| 519 | struct pci_bus *child; |
| 520 | |
| 521 | /* |
| 522 | * Size the bridge windows. |
| 523 | */ |
| 524 | pci_bus_size_bridges(bus); |
| 525 | |
| 526 | /* |
| 527 | * Assign resources. |
| 528 | */ |
| 529 | pci_bus_assign_resources(bus); |
| 530 | |
| 531 | list_for_each_entry(child, &bus->children, node) |
| 532 | pcie_bus_configure_settings(child); |
| 533 | } |
| 534 | /* |
| 535 | * Tell drivers about devices found. |
| 536 | */ |
| 537 | pci_bus_add_devices(bus); |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | #ifndef CONFIG_PCI_HOST_ITE8152 |
| 542 | void pcibios_set_master(struct pci_dev *dev) |
| 543 | { |
| 544 | /* No special bus mastering setup handling */ |
| 545 | } |
| 546 | #endif |
| 547 | |
| 548 | char * __init pcibios_setup(char *str) |
| 549 | { |
| 550 | if (!strcmp(str, "debug")) { |
| 551 | debug_pci = 1; |
| 552 | return NULL; |
| 553 | } |
| 554 | return str; |
| 555 | } |
| 556 | |
| 557 | /* |
| 558 | * From arch/i386/kernel/pci-i386.c: |
| 559 | * |
| 560 | * We need to avoid collisions with `mirrored' VGA ports |
| 561 | * and other strange ISA hardware, so we always want the |
| 562 | * addresses to be allocated in the 0x000-0x0ff region |
| 563 | * modulo 0x400. |
| 564 | * |
| 565 | * Why? Because some silly external IO cards only decode |
| 566 | * the low 10 bits of the IO address. The 0x00-0xff region |
| 567 | * is reserved for motherboard devices that decode all 16 |
| 568 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, |
| 569 | * but we want to try to avoid allocating at 0x2900-0x2bff |
| 570 | * which might be mirrored at 0x0100-0x03ff.. |
| 571 | */ |
| 572 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
| 573 | resource_size_t size, resource_size_t align) |
| 574 | { |
| 575 | struct pci_dev *dev = data; |
| 576 | resource_size_t start = res->start; |
| 577 | struct pci_host_bridge *host_bridge; |
| 578 | |
| 579 | if (res->flags & IORESOURCE_IO && start & 0x300) |
| 580 | start = (start + 0x3ff) & ~0x3ff; |
| 581 | |
| 582 | start = (start + align - 1) & ~(align - 1); |
| 583 | |
| 584 | host_bridge = pci_find_host_bridge(dev->bus); |
| 585 | |
| 586 | if (host_bridge->align_resource) |
| 587 | return host_bridge->align_resource(dev, res, |
| 588 | start, size, align); |
| 589 | |
| 590 | return start; |
| 591 | } |
| 592 | |
| 593 | /** |
| 594 | * pcibios_enable_device - Enable I/O and memory. |
| 595 | * @dev: PCI device to be enabled |
| 596 | */ |
| 597 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 598 | { |
| 599 | if (pci_has_flag(PCI_PROBE_ONLY)) |
| 600 | return 0; |
| 601 | |
| 602 | return pci_enable_resources(dev, mask); |
| 603 | } |
| 604 | |
| 605 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 606 | enum pci_mmap_state mmap_state, int write_combine) |
| 607 | { |
| 608 | if (mmap_state == pci_mmap_io) |
| 609 | return -EINVAL; |
| 610 | |
| 611 | /* |
| 612 | * Mark this as IO |
| 613 | */ |
| 614 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
| 615 | |
| 616 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
| 617 | vma->vm_end - vma->vm_start, |
| 618 | vma->vm_page_prot)) |
| 619 | return -EAGAIN; |
| 620 | |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | void __init pci_map_io_early(unsigned long pfn) |
| 625 | { |
| 626 | struct map_desc pci_io_desc = { |
| 627 | .virtual = PCI_IO_VIRT_BASE, |
| 628 | .type = MT_DEVICE, |
| 629 | .length = SZ_64K, |
| 630 | }; |
| 631 | |
| 632 | pci_io_desc.pfn = pfn; |
| 633 | iotable_init(&pci_io_desc, 1); |
| 634 | } |