| 1 | /* |
| 2 | * mach-davinci/devices.c |
| 3 | * |
| 4 | * DaVinci platform device setup/initialization |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/dma-mapping.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/reboot.h> |
| 17 | |
| 18 | #include <mach/hardware.h> |
| 19 | #include <linux/platform_data/i2c-davinci.h> |
| 20 | #include <mach/irqs.h> |
| 21 | #include <mach/cputype.h> |
| 22 | #include <mach/mux.h> |
| 23 | #include <linux/platform_data/mmc-davinci.h> |
| 24 | #include <mach/time.h> |
| 25 | #include <linux/platform_data/edma.h> |
| 26 | |
| 27 | |
| 28 | #include "davinci.h" |
| 29 | #include "clock.h" |
| 30 | |
| 31 | #define DAVINCI_I2C_BASE 0x01C21000 |
| 32 | #define DAVINCI_ATA_BASE 0x01C66000 |
| 33 | #define DAVINCI_MMCSD0_BASE 0x01E10000 |
| 34 | #define DM355_MMCSD0_BASE 0x01E11000 |
| 35 | #define DM355_MMCSD1_BASE 0x01E00000 |
| 36 | #define DM365_MMCSD0_BASE 0x01D11000 |
| 37 | #define DM365_MMCSD1_BASE 0x01D00000 |
| 38 | |
| 39 | #define DAVINCI_DMA_MMCRXEVT 26 |
| 40 | #define DAVINCI_DMA_MMCTXEVT 27 |
| 41 | |
| 42 | void __iomem *davinci_sysmod_base; |
| 43 | |
| 44 | void davinci_map_sysmod(void) |
| 45 | { |
| 46 | davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE, |
| 47 | 0x800); |
| 48 | /* |
| 49 | * Throw a bug since a lot of board initialization code depends |
| 50 | * on system module availability. ioremap() failing this early |
| 51 | * need careful looking into anyway. |
| 52 | */ |
| 53 | BUG_ON(!davinci_sysmod_base); |
| 54 | } |
| 55 | |
| 56 | static struct resource i2c_resources[] = { |
| 57 | { |
| 58 | .start = DAVINCI_I2C_BASE, |
| 59 | .end = DAVINCI_I2C_BASE + 0x40, |
| 60 | .flags = IORESOURCE_MEM, |
| 61 | }, |
| 62 | { |
| 63 | .start = IRQ_I2C, |
| 64 | .flags = IORESOURCE_IRQ, |
| 65 | }, |
| 66 | }; |
| 67 | |
| 68 | static struct platform_device davinci_i2c_device = { |
| 69 | .name = "i2c_davinci", |
| 70 | .id = 1, |
| 71 | .num_resources = ARRAY_SIZE(i2c_resources), |
| 72 | .resource = i2c_resources, |
| 73 | }; |
| 74 | |
| 75 | void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) |
| 76 | { |
| 77 | if (cpu_is_davinci_dm644x()) |
| 78 | davinci_cfg_reg(DM644X_I2C); |
| 79 | |
| 80 | davinci_i2c_device.dev.platform_data = pdata; |
| 81 | (void) platform_device_register(&davinci_i2c_device); |
| 82 | } |
| 83 | |
| 84 | static struct resource ide_resources[] = { |
| 85 | { |
| 86 | .start = DAVINCI_ATA_BASE, |
| 87 | .end = DAVINCI_ATA_BASE + 0x7ff, |
| 88 | .flags = IORESOURCE_MEM, |
| 89 | }, |
| 90 | { |
| 91 | .start = IRQ_IDE, |
| 92 | .end = IRQ_IDE, |
| 93 | .flags = IORESOURCE_IRQ, |
| 94 | }, |
| 95 | }; |
| 96 | |
| 97 | static u64 ide_dma_mask = DMA_BIT_MASK(32); |
| 98 | |
| 99 | static struct platform_device ide_device = { |
| 100 | .name = "palm_bk3710", |
| 101 | .id = -1, |
| 102 | .resource = ide_resources, |
| 103 | .num_resources = ARRAY_SIZE(ide_resources), |
| 104 | .dev = { |
| 105 | .dma_mask = &ide_dma_mask, |
| 106 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 107 | }, |
| 108 | }; |
| 109 | |
| 110 | void __init davinci_init_ide(void) |
| 111 | { |
| 112 | if (cpu_is_davinci_dm644x()) { |
| 113 | davinci_cfg_reg(DM644X_HPIEN_DISABLE); |
| 114 | davinci_cfg_reg(DM644X_ATAEN); |
| 115 | davinci_cfg_reg(DM644X_HDIREN); |
| 116 | } else if (cpu_is_davinci_dm646x()) { |
| 117 | /* IRQ_DM646X_IDE is the same as IRQ_IDE */ |
| 118 | davinci_cfg_reg(DM646X_ATAEN); |
| 119 | } else { |
| 120 | WARN_ON(1); |
| 121 | return; |
| 122 | } |
| 123 | |
| 124 | platform_device_register(&ide_device); |
| 125 | } |
| 126 | |
| 127 | #if IS_ENABLED(CONFIG_MMC_DAVINCI) |
| 128 | |
| 129 | static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); |
| 130 | |
| 131 | static struct resource mmcsd0_resources[] = { |
| 132 | { |
| 133 | /* different on dm355 */ |
| 134 | .start = DAVINCI_MMCSD0_BASE, |
| 135 | .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, |
| 136 | .flags = IORESOURCE_MEM, |
| 137 | }, |
| 138 | /* IRQs: MMC/SD, then SDIO */ |
| 139 | { |
| 140 | .start = IRQ_MMCINT, |
| 141 | .flags = IORESOURCE_IRQ, |
| 142 | }, { |
| 143 | /* different on dm355 */ |
| 144 | .start = IRQ_SDIOINT, |
| 145 | .flags = IORESOURCE_IRQ, |
| 146 | }, |
| 147 | }; |
| 148 | |
| 149 | static struct platform_device davinci_mmcsd0_device = { |
| 150 | .name = "dm6441-mmc", |
| 151 | .id = 0, |
| 152 | .dev = { |
| 153 | .dma_mask = &mmcsd0_dma_mask, |
| 154 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 155 | }, |
| 156 | .num_resources = ARRAY_SIZE(mmcsd0_resources), |
| 157 | .resource = mmcsd0_resources, |
| 158 | }; |
| 159 | |
| 160 | static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); |
| 161 | |
| 162 | static struct resource mmcsd1_resources[] = { |
| 163 | { |
| 164 | .start = DM355_MMCSD1_BASE, |
| 165 | .end = DM355_MMCSD1_BASE + SZ_4K - 1, |
| 166 | .flags = IORESOURCE_MEM, |
| 167 | }, |
| 168 | /* IRQs: MMC/SD, then SDIO */ |
| 169 | { |
| 170 | .start = IRQ_DM355_MMCINT1, |
| 171 | .flags = IORESOURCE_IRQ, |
| 172 | }, { |
| 173 | .start = IRQ_DM355_SDIOINT1, |
| 174 | .flags = IORESOURCE_IRQ, |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | static struct platform_device davinci_mmcsd1_device = { |
| 179 | .name = "dm6441-mmc", |
| 180 | .id = 1, |
| 181 | .dev = { |
| 182 | .dma_mask = &mmcsd1_dma_mask, |
| 183 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 184 | }, |
| 185 | .num_resources = ARRAY_SIZE(mmcsd1_resources), |
| 186 | .resource = mmcsd1_resources, |
| 187 | }; |
| 188 | |
| 189 | |
| 190 | void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) |
| 191 | { |
| 192 | struct platform_device *pdev = NULL; |
| 193 | |
| 194 | if (WARN_ON(cpu_is_davinci_dm646x())) |
| 195 | return; |
| 196 | |
| 197 | /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; |
| 198 | * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. |
| 199 | * |
| 200 | * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are |
| 201 | * not handled right here ... |
| 202 | */ |
| 203 | switch (module) { |
| 204 | case 1: |
| 205 | if (cpu_is_davinci_dm355()) { |
| 206 | /* REVISIT we may not need all these pins if e.g. this |
| 207 | * is a hard-wired SDIO device... |
| 208 | */ |
| 209 | davinci_cfg_reg(DM355_SD1_CMD); |
| 210 | davinci_cfg_reg(DM355_SD1_CLK); |
| 211 | davinci_cfg_reg(DM355_SD1_DATA0); |
| 212 | davinci_cfg_reg(DM355_SD1_DATA1); |
| 213 | davinci_cfg_reg(DM355_SD1_DATA2); |
| 214 | davinci_cfg_reg(DM355_SD1_DATA3); |
| 215 | } else if (cpu_is_davinci_dm365()) { |
| 216 | /* Configure pull down control */ |
| 217 | unsigned v; |
| 218 | |
| 219 | v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); |
| 220 | __raw_writel(v & ~0xfc0, |
| 221 | DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); |
| 222 | |
| 223 | mmcsd1_resources[0].start = DM365_MMCSD1_BASE; |
| 224 | mmcsd1_resources[0].end = DM365_MMCSD1_BASE + |
| 225 | SZ_4K - 1; |
| 226 | mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; |
| 227 | davinci_mmcsd1_device.name = "da830-mmc"; |
| 228 | } else |
| 229 | break; |
| 230 | |
| 231 | pdev = &davinci_mmcsd1_device; |
| 232 | break; |
| 233 | case 0: |
| 234 | if (cpu_is_davinci_dm355()) { |
| 235 | mmcsd0_resources[0].start = DM355_MMCSD0_BASE; |
| 236 | mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; |
| 237 | mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; |
| 238 | |
| 239 | /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ |
| 240 | davinci_cfg_reg(DM355_MMCSD0); |
| 241 | |
| 242 | /* enable RX EDMA */ |
| 243 | davinci_cfg_reg(DM355_EVT26_MMC0_RX); |
| 244 | } else if (cpu_is_davinci_dm365()) { |
| 245 | mmcsd0_resources[0].start = DM365_MMCSD0_BASE; |
| 246 | mmcsd0_resources[0].end = DM365_MMCSD0_BASE + |
| 247 | SZ_4K - 1; |
| 248 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; |
| 249 | davinci_mmcsd0_device.name = "da830-mmc"; |
| 250 | } else if (cpu_is_davinci_dm644x()) { |
| 251 | /* REVISIT: should this be in board-init code? */ |
| 252 | /* Power-on 3.3V IO cells */ |
| 253 | __raw_writel(0, |
| 254 | DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); |
| 255 | /*Set up the pull regiter for MMC */ |
| 256 | davinci_cfg_reg(DM644X_MSTK); |
| 257 | } |
| 258 | |
| 259 | pdev = &davinci_mmcsd0_device; |
| 260 | break; |
| 261 | } |
| 262 | |
| 263 | if (WARN_ON(!pdev)) |
| 264 | return; |
| 265 | |
| 266 | pdev->dev.platform_data = config; |
| 267 | platform_device_register(pdev); |
| 268 | } |
| 269 | |
| 270 | #else |
| 271 | |
| 272 | void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) |
| 273 | { |
| 274 | } |
| 275 | |
| 276 | #endif |
| 277 | |
| 278 | /*-------------------------------------------------------------------------*/ |
| 279 | |
| 280 | static struct resource wdt_resources[] = { |
| 281 | { |
| 282 | .start = DAVINCI_WDOG_BASE, |
| 283 | .end = DAVINCI_WDOG_BASE + SZ_1K - 1, |
| 284 | .flags = IORESOURCE_MEM, |
| 285 | }, |
| 286 | }; |
| 287 | |
| 288 | struct platform_device davinci_wdt_device = { |
| 289 | .name = "davinci-wdt", |
| 290 | .id = -1, |
| 291 | .num_resources = ARRAY_SIZE(wdt_resources), |
| 292 | .resource = wdt_resources, |
| 293 | }; |
| 294 | |
| 295 | void davinci_restart(enum reboot_mode mode, const char *cmd) |
| 296 | { |
| 297 | davinci_watchdog_reset(&davinci_wdt_device); |
| 298 | } |
| 299 | |
| 300 | int davinci_init_wdt(void) |
| 301 | { |
| 302 | return platform_device_register(&davinci_wdt_device); |
| 303 | } |
| 304 | |
| 305 | static struct platform_device davinci_gpio_device = { |
| 306 | .name = "davinci_gpio", |
| 307 | .id = -1, |
| 308 | }; |
| 309 | |
| 310 | int davinci_gpio_register(struct resource *res, int size, void *pdata) |
| 311 | { |
| 312 | davinci_gpio_device.resource = res; |
| 313 | davinci_gpio_device.num_resources = size; |
| 314 | davinci_gpio_device.dev.platform_data = pdata; |
| 315 | return platform_device_register(&davinci_gpio_device); |
| 316 | } |
| 317 | |
| 318 | /*-------------------------------------------------------------------------*/ |
| 319 | |
| 320 | /*-------------------------------------------------------------------------*/ |
| 321 | |
| 322 | struct davinci_timer_instance davinci_timer_instance[2] = { |
| 323 | { |
| 324 | .base = DAVINCI_TIMER0_BASE, |
| 325 | .bottom_irq = IRQ_TINT0_TINT12, |
| 326 | .top_irq = IRQ_TINT0_TINT34, |
| 327 | }, |
| 328 | { |
| 329 | .base = DAVINCI_TIMER1_BASE, |
| 330 | .bottom_irq = IRQ_TINT1_TINT12, |
| 331 | .top_irq = IRQ_TINT1_TINT34, |
| 332 | }, |
| 333 | }; |
| 334 | |