| 1 | /* |
| 2 | * arch/arm/mach-ep93xx/clock.c |
| 3 | * Clock control for Cirrus EP93xx chips. |
| 4 | * |
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or (at |
| 10 | * your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/string.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/spinlock.h> |
| 22 | |
| 23 | #include <mach/hardware.h> |
| 24 | |
| 25 | #include <asm/clkdev.h> |
| 26 | #include <asm/div64.h> |
| 27 | |
| 28 | |
| 29 | struct clk { |
| 30 | struct clk *parent; |
| 31 | unsigned long rate; |
| 32 | int users; |
| 33 | int sw_locked; |
| 34 | void __iomem *enable_reg; |
| 35 | u32 enable_mask; |
| 36 | |
| 37 | unsigned long (*get_rate)(struct clk *clk); |
| 38 | int (*set_rate)(struct clk *clk, unsigned long rate); |
| 39 | }; |
| 40 | |
| 41 | |
| 42 | static unsigned long get_uart_rate(struct clk *clk); |
| 43 | |
| 44 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate); |
| 45 | static int set_div_rate(struct clk *clk, unsigned long rate); |
| 46 | |
| 47 | |
| 48 | static struct clk clk_xtali = { |
| 49 | .rate = EP93XX_EXT_CLK_RATE, |
| 50 | }; |
| 51 | static struct clk clk_uart1 = { |
| 52 | .parent = &clk_xtali, |
| 53 | .sw_locked = 1, |
| 54 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 55 | .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, |
| 56 | .get_rate = get_uart_rate, |
| 57 | }; |
| 58 | static struct clk clk_uart2 = { |
| 59 | .parent = &clk_xtali, |
| 60 | .sw_locked = 1, |
| 61 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 62 | .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, |
| 63 | .get_rate = get_uart_rate, |
| 64 | }; |
| 65 | static struct clk clk_uart3 = { |
| 66 | .parent = &clk_xtali, |
| 67 | .sw_locked = 1, |
| 68 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 69 | .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, |
| 70 | .get_rate = get_uart_rate, |
| 71 | }; |
| 72 | static struct clk clk_pll1 = { |
| 73 | .parent = &clk_xtali, |
| 74 | }; |
| 75 | static struct clk clk_f = { |
| 76 | .parent = &clk_pll1, |
| 77 | }; |
| 78 | static struct clk clk_h = { |
| 79 | .parent = &clk_pll1, |
| 80 | }; |
| 81 | static struct clk clk_p = { |
| 82 | .parent = &clk_pll1, |
| 83 | }; |
| 84 | static struct clk clk_pll2 = { |
| 85 | .parent = &clk_xtali, |
| 86 | }; |
| 87 | static struct clk clk_usb_host = { |
| 88 | .parent = &clk_pll2, |
| 89 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 90 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, |
| 91 | }; |
| 92 | static struct clk clk_keypad = { |
| 93 | .parent = &clk_xtali, |
| 94 | .sw_locked = 1, |
| 95 | .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, |
| 96 | .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, |
| 97 | .set_rate = set_keytchclk_rate, |
| 98 | }; |
| 99 | static struct clk clk_pwm = { |
| 100 | .parent = &clk_xtali, |
| 101 | .rate = EP93XX_EXT_CLK_RATE, |
| 102 | }; |
| 103 | |
| 104 | static struct clk clk_video = { |
| 105 | .sw_locked = 1, |
| 106 | .enable_reg = EP93XX_SYSCON_VIDCLKDIV, |
| 107 | .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, |
| 108 | .set_rate = set_div_rate, |
| 109 | }; |
| 110 | |
| 111 | /* DMA Clocks */ |
| 112 | static struct clk clk_m2p0 = { |
| 113 | .parent = &clk_h, |
| 114 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 115 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, |
| 116 | }; |
| 117 | static struct clk clk_m2p1 = { |
| 118 | .parent = &clk_h, |
| 119 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 120 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, |
| 121 | }; |
| 122 | static struct clk clk_m2p2 = { |
| 123 | .parent = &clk_h, |
| 124 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 125 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, |
| 126 | }; |
| 127 | static struct clk clk_m2p3 = { |
| 128 | .parent = &clk_h, |
| 129 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 130 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, |
| 131 | }; |
| 132 | static struct clk clk_m2p4 = { |
| 133 | .parent = &clk_h, |
| 134 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 135 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, |
| 136 | }; |
| 137 | static struct clk clk_m2p5 = { |
| 138 | .parent = &clk_h, |
| 139 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 140 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, |
| 141 | }; |
| 142 | static struct clk clk_m2p6 = { |
| 143 | .parent = &clk_h, |
| 144 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 145 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, |
| 146 | }; |
| 147 | static struct clk clk_m2p7 = { |
| 148 | .parent = &clk_h, |
| 149 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 150 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, |
| 151 | }; |
| 152 | static struct clk clk_m2p8 = { |
| 153 | .parent = &clk_h, |
| 154 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 155 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, |
| 156 | }; |
| 157 | static struct clk clk_m2p9 = { |
| 158 | .parent = &clk_h, |
| 159 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 160 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, |
| 161 | }; |
| 162 | static struct clk clk_m2m0 = { |
| 163 | .parent = &clk_h, |
| 164 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 165 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, |
| 166 | }; |
| 167 | static struct clk clk_m2m1 = { |
| 168 | .parent = &clk_h, |
| 169 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 170 | .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, |
| 171 | }; |
| 172 | |
| 173 | #define INIT_CK(dev,con,ck) \ |
| 174 | { .dev_id = dev, .con_id = con, .clk = ck } |
| 175 | |
| 176 | static struct clk_lookup clocks[] = { |
| 177 | INIT_CK(NULL, "xtali", &clk_xtali), |
| 178 | INIT_CK("apb:uart1", NULL, &clk_uart1), |
| 179 | INIT_CK("apb:uart2", NULL, &clk_uart2), |
| 180 | INIT_CK("apb:uart3", NULL, &clk_uart3), |
| 181 | INIT_CK(NULL, "pll1", &clk_pll1), |
| 182 | INIT_CK(NULL, "fclk", &clk_f), |
| 183 | INIT_CK(NULL, "hclk", &clk_h), |
| 184 | INIT_CK(NULL, "pclk", &clk_p), |
| 185 | INIT_CK(NULL, "pll2", &clk_pll2), |
| 186 | INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), |
| 187 | INIT_CK("ep93xx-keypad", NULL, &clk_keypad), |
| 188 | INIT_CK("ep93xx-fb", NULL, &clk_video), |
| 189 | INIT_CK(NULL, "pwm_clk", &clk_pwm), |
| 190 | INIT_CK(NULL, "m2p0", &clk_m2p0), |
| 191 | INIT_CK(NULL, "m2p1", &clk_m2p1), |
| 192 | INIT_CK(NULL, "m2p2", &clk_m2p2), |
| 193 | INIT_CK(NULL, "m2p3", &clk_m2p3), |
| 194 | INIT_CK(NULL, "m2p4", &clk_m2p4), |
| 195 | INIT_CK(NULL, "m2p5", &clk_m2p5), |
| 196 | INIT_CK(NULL, "m2p6", &clk_m2p6), |
| 197 | INIT_CK(NULL, "m2p7", &clk_m2p7), |
| 198 | INIT_CK(NULL, "m2p8", &clk_m2p8), |
| 199 | INIT_CK(NULL, "m2p9", &clk_m2p9), |
| 200 | INIT_CK(NULL, "m2m0", &clk_m2m0), |
| 201 | INIT_CK(NULL, "m2m1", &clk_m2m1), |
| 202 | }; |
| 203 | |
| 204 | static DEFINE_SPINLOCK(clk_lock); |
| 205 | |
| 206 | static void __clk_enable(struct clk *clk) |
| 207 | { |
| 208 | if (!clk->users++) { |
| 209 | if (clk->parent) |
| 210 | __clk_enable(clk->parent); |
| 211 | |
| 212 | if (clk->enable_reg) { |
| 213 | u32 v; |
| 214 | |
| 215 | v = __raw_readl(clk->enable_reg); |
| 216 | v |= clk->enable_mask; |
| 217 | if (clk->sw_locked) |
| 218 | ep93xx_syscon_swlocked_write(v, clk->enable_reg); |
| 219 | else |
| 220 | __raw_writel(v, clk->enable_reg); |
| 221 | } |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | int clk_enable(struct clk *clk) |
| 226 | { |
| 227 | unsigned long flags; |
| 228 | |
| 229 | if (!clk) |
| 230 | return -EINVAL; |
| 231 | |
| 232 | spin_lock_irqsave(&clk_lock, flags); |
| 233 | __clk_enable(clk); |
| 234 | spin_unlock_irqrestore(&clk_lock, flags); |
| 235 | |
| 236 | return 0; |
| 237 | } |
| 238 | EXPORT_SYMBOL(clk_enable); |
| 239 | |
| 240 | static void __clk_disable(struct clk *clk) |
| 241 | { |
| 242 | if (!--clk->users) { |
| 243 | if (clk->enable_reg) { |
| 244 | u32 v; |
| 245 | |
| 246 | v = __raw_readl(clk->enable_reg); |
| 247 | v &= ~clk->enable_mask; |
| 248 | if (clk->sw_locked) |
| 249 | ep93xx_syscon_swlocked_write(v, clk->enable_reg); |
| 250 | else |
| 251 | __raw_writel(v, clk->enable_reg); |
| 252 | } |
| 253 | |
| 254 | if (clk->parent) |
| 255 | __clk_disable(clk->parent); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | void clk_disable(struct clk *clk) |
| 260 | { |
| 261 | unsigned long flags; |
| 262 | |
| 263 | if (!clk) |
| 264 | return; |
| 265 | |
| 266 | spin_lock_irqsave(&clk_lock, flags); |
| 267 | __clk_disable(clk); |
| 268 | spin_unlock_irqrestore(&clk_lock, flags); |
| 269 | } |
| 270 | EXPORT_SYMBOL(clk_disable); |
| 271 | |
| 272 | static unsigned long get_uart_rate(struct clk *clk) |
| 273 | { |
| 274 | unsigned long rate = clk_get_rate(clk->parent); |
| 275 | u32 value; |
| 276 | |
| 277 | value = __raw_readl(EP93XX_SYSCON_PWRCNT); |
| 278 | if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) |
| 279 | return rate; |
| 280 | else |
| 281 | return rate / 2; |
| 282 | } |
| 283 | |
| 284 | unsigned long clk_get_rate(struct clk *clk) |
| 285 | { |
| 286 | if (clk->get_rate) |
| 287 | return clk->get_rate(clk); |
| 288 | |
| 289 | return clk->rate; |
| 290 | } |
| 291 | EXPORT_SYMBOL(clk_get_rate); |
| 292 | |
| 293 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate) |
| 294 | { |
| 295 | u32 val; |
| 296 | u32 div_bit; |
| 297 | |
| 298 | val = __raw_readl(clk->enable_reg); |
| 299 | |
| 300 | /* |
| 301 | * The Key Matrix and ADC clocks are configured using the same |
| 302 | * System Controller register. The clock used will be either |
| 303 | * 1/4 or 1/16 the external clock rate depending on the |
| 304 | * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV |
| 305 | * bit being set or cleared. |
| 306 | */ |
| 307 | div_bit = clk->enable_mask >> 15; |
| 308 | |
| 309 | if (rate == EP93XX_KEYTCHCLK_DIV4) |
| 310 | val |= div_bit; |
| 311 | else if (rate == EP93XX_KEYTCHCLK_DIV16) |
| 312 | val &= ~div_bit; |
| 313 | else |
| 314 | return -EINVAL; |
| 315 | |
| 316 | ep93xx_syscon_swlocked_write(val, clk->enable_reg); |
| 317 | clk->rate = rate; |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static int calc_clk_div(struct clk *clk, unsigned long rate, |
| 322 | int *psel, int *esel, int *pdiv, int *div) |
| 323 | { |
| 324 | struct clk *mclk; |
| 325 | unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1; |
| 326 | int i, found = 0, __div = 0, __pdiv = 0; |
| 327 | |
| 328 | /* Don't exceed the maximum rate */ |
| 329 | max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4), |
| 330 | clk_xtali.rate / 4); |
| 331 | rate = min(rate, max_rate); |
| 332 | |
| 333 | /* |
| 334 | * Try the two pll's and the external clock |
| 335 | * Because the valid predividers are 2, 2.5 and 3, we multiply |
| 336 | * all the clocks by 2 to avoid floating point math. |
| 337 | * |
| 338 | * This is based on the algorithm in the ep93xx raster guide: |
| 339 | * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf |
| 340 | * |
| 341 | */ |
| 342 | for (i = 0; i < 3; i++) { |
| 343 | if (i == 0) |
| 344 | mclk = &clk_xtali; |
| 345 | else if (i == 1) |
| 346 | mclk = &clk_pll1; |
| 347 | else |
| 348 | mclk = &clk_pll2; |
| 349 | mclk_rate = mclk->rate * 2; |
| 350 | |
| 351 | /* Try each predivider value */ |
| 352 | for (__pdiv = 4; __pdiv <= 6; __pdiv++) { |
| 353 | __div = mclk_rate / (rate * __pdiv); |
| 354 | if (__div < 2 || __div > 127) |
| 355 | continue; |
| 356 | |
| 357 | actual_rate = mclk_rate / (__pdiv * __div); |
| 358 | |
| 359 | if (!found || abs(actual_rate - rate) < rate_err) { |
| 360 | *pdiv = __pdiv - 3; |
| 361 | *div = __div; |
| 362 | *psel = (i == 2); |
| 363 | *esel = (i != 0); |
| 364 | clk->parent = mclk; |
| 365 | clk->rate = actual_rate; |
| 366 | rate_err = abs(actual_rate - rate); |
| 367 | found = 1; |
| 368 | } |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | if (!found) |
| 373 | return -EINVAL; |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | static int set_div_rate(struct clk *clk, unsigned long rate) |
| 379 | { |
| 380 | int err, psel = 0, esel = 0, pdiv = 0, div = 0; |
| 381 | u32 val; |
| 382 | |
| 383 | err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); |
| 384 | if (err) |
| 385 | return err; |
| 386 | |
| 387 | /* Clear the esel, psel, pdiv and div bits */ |
| 388 | val = __raw_readl(clk->enable_reg); |
| 389 | val &= ~0x7fff; |
| 390 | |
| 391 | /* Set the new esel, psel, pdiv and div bits for the new clock rate */ |
| 392 | val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | |
| 393 | (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) | |
| 394 | (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; |
| 395 | ep93xx_syscon_swlocked_write(val, clk->enable_reg); |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 400 | { |
| 401 | if (clk->set_rate) |
| 402 | return clk->set_rate(clk, rate); |
| 403 | |
| 404 | return -EINVAL; |
| 405 | } |
| 406 | EXPORT_SYMBOL(clk_set_rate); |
| 407 | |
| 408 | |
| 409 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; |
| 410 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; |
| 411 | static char pclk_divisors[] = { 1, 2, 4, 8 }; |
| 412 | |
| 413 | /* |
| 414 | * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS |
| 415 | */ |
| 416 | static unsigned long calc_pll_rate(u32 config_word) |
| 417 | { |
| 418 | unsigned long long rate; |
| 419 | int i; |
| 420 | |
| 421 | rate = clk_xtali.rate; |
| 422 | rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ |
| 423 | rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ |
| 424 | do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ |
| 425 | for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ |
| 426 | rate >>= 1; |
| 427 | |
| 428 | return (unsigned long)rate; |
| 429 | } |
| 430 | |
| 431 | static void __init ep93xx_dma_clock_init(void) |
| 432 | { |
| 433 | clk_m2p0.rate = clk_h.rate; |
| 434 | clk_m2p1.rate = clk_h.rate; |
| 435 | clk_m2p2.rate = clk_h.rate; |
| 436 | clk_m2p3.rate = clk_h.rate; |
| 437 | clk_m2p4.rate = clk_h.rate; |
| 438 | clk_m2p5.rate = clk_h.rate; |
| 439 | clk_m2p6.rate = clk_h.rate; |
| 440 | clk_m2p7.rate = clk_h.rate; |
| 441 | clk_m2p8.rate = clk_h.rate; |
| 442 | clk_m2p9.rate = clk_h.rate; |
| 443 | clk_m2m0.rate = clk_h.rate; |
| 444 | clk_m2m1.rate = clk_h.rate; |
| 445 | } |
| 446 | |
| 447 | static int __init ep93xx_clock_init(void) |
| 448 | { |
| 449 | u32 value; |
| 450 | int i; |
| 451 | |
| 452 | /* Determine the bootloader configured pll1 rate */ |
| 453 | value = __raw_readl(EP93XX_SYSCON_CLKSET1); |
| 454 | if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) |
| 455 | clk_pll1.rate = clk_xtali.rate; |
| 456 | else |
| 457 | clk_pll1.rate = calc_pll_rate(value); |
| 458 | |
| 459 | /* Initialize the pll1 derived clocks */ |
| 460 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; |
| 461 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; |
| 462 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; |
| 463 | ep93xx_dma_clock_init(); |
| 464 | |
| 465 | /* Determine the bootloader configured pll2 rate */ |
| 466 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); |
| 467 | if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) |
| 468 | clk_pll2.rate = clk_xtali.rate; |
| 469 | else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) |
| 470 | clk_pll2.rate = calc_pll_rate(value); |
| 471 | else |
| 472 | clk_pll2.rate = 0; |
| 473 | |
| 474 | /* Initialize the pll2 derived clocks */ |
| 475 | clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); |
| 476 | |
| 477 | pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", |
| 478 | clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); |
| 479 | pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", |
| 480 | clk_f.rate / 1000000, clk_h.rate / 1000000, |
| 481 | clk_p.rate / 1000000); |
| 482 | |
| 483 | for (i = 0; i < ARRAY_SIZE(clocks); i++) |
| 484 | clkdev_add(&clocks[i]); |
| 485 | return 0; |
| 486 | } |
| 487 | arch_initcall(ep93xx_clock_init); |