| 1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/dma-mapping.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/irq.h> |
| 21 | #include <linux/gpio.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/mfd/mc13783.h> |
| 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/spi/l4f00242t03.h> |
| 26 | #include <linux/regulator/machine.h> |
| 27 | #include <linux/usb/otg.h> |
| 28 | #include <linux/usb/ulpi.h> |
| 29 | #include <linux/memblock.h> |
| 30 | |
| 31 | #include <media/soc_camera.h> |
| 32 | |
| 33 | #include <mach/hardware.h> |
| 34 | #include <asm/mach-types.h> |
| 35 | #include <asm/mach/arch.h> |
| 36 | #include <asm/mach/time.h> |
| 37 | #include <asm/memory.h> |
| 38 | #include <asm/mach/map.h> |
| 39 | #include <mach/common.h> |
| 40 | #include <mach/iomux-mx3.h> |
| 41 | #include <mach/3ds_debugboard.h> |
| 42 | #include <mach/ulpi.h> |
| 43 | |
| 44 | #include "devices-imx31.h" |
| 45 | |
| 46 | /* CPLD IRQ line for external uart, external ethernet etc */ |
| 47 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) |
| 48 | |
| 49 | static int mx31_3ds_pins[] = { |
| 50 | /* UART1 */ |
| 51 | MX31_PIN_CTS1__CTS1, |
| 52 | MX31_PIN_RTS1__RTS1, |
| 53 | MX31_PIN_TXD1__TXD1, |
| 54 | MX31_PIN_RXD1__RXD1, |
| 55 | IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), |
| 56 | /*SPI0*/ |
| 57 | IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), |
| 58 | IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), |
| 59 | /* SPI 1 */ |
| 60 | MX31_PIN_CSPI2_SCLK__SCLK, |
| 61 | MX31_PIN_CSPI2_MOSI__MOSI, |
| 62 | MX31_PIN_CSPI2_MISO__MISO, |
| 63 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, |
| 64 | MX31_PIN_CSPI2_SS0__SS0, |
| 65 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ |
| 66 | /* MC13783 IRQ */ |
| 67 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), |
| 68 | /* USB OTG reset */ |
| 69 | IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), |
| 70 | /* USB OTG */ |
| 71 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, |
| 72 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, |
| 73 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, |
| 74 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, |
| 75 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, |
| 76 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, |
| 77 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, |
| 78 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, |
| 79 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, |
| 80 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, |
| 81 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, |
| 82 | MX31_PIN_USBOTG_STP__USBOTG_STP, |
| 83 | /*Keyboard*/ |
| 84 | MX31_PIN_KEY_ROW0_KEY_ROW0, |
| 85 | MX31_PIN_KEY_ROW1_KEY_ROW1, |
| 86 | MX31_PIN_KEY_ROW2_KEY_ROW2, |
| 87 | MX31_PIN_KEY_COL0_KEY_COL0, |
| 88 | MX31_PIN_KEY_COL1_KEY_COL1, |
| 89 | MX31_PIN_KEY_COL2_KEY_COL2, |
| 90 | MX31_PIN_KEY_COL3_KEY_COL3, |
| 91 | /* USB Host 2 */ |
| 92 | IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), |
| 93 | IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), |
| 94 | IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), |
| 95 | IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), |
| 96 | IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), |
| 97 | IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), |
| 98 | IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), |
| 99 | IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), |
| 100 | IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), |
| 101 | IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), |
| 102 | IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), |
| 103 | IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), |
| 104 | /* USB Host2 reset */ |
| 105 | IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), |
| 106 | /* I2C1 */ |
| 107 | MX31_PIN_I2C_CLK__I2C1_SCL, |
| 108 | MX31_PIN_I2C_DAT__I2C1_SDA, |
| 109 | /* SDHC1 */ |
| 110 | MX31_PIN_SD1_DATA3__SD1_DATA3, |
| 111 | MX31_PIN_SD1_DATA2__SD1_DATA2, |
| 112 | MX31_PIN_SD1_DATA1__SD1_DATA1, |
| 113 | MX31_PIN_SD1_DATA0__SD1_DATA0, |
| 114 | MX31_PIN_SD1_CLK__SD1_CLK, |
| 115 | MX31_PIN_SD1_CMD__SD1_CMD, |
| 116 | MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ |
| 117 | MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ |
| 118 | /* Framebuffer */ |
| 119 | MX31_PIN_LD0__LD0, |
| 120 | MX31_PIN_LD1__LD1, |
| 121 | MX31_PIN_LD2__LD2, |
| 122 | MX31_PIN_LD3__LD3, |
| 123 | MX31_PIN_LD4__LD4, |
| 124 | MX31_PIN_LD5__LD5, |
| 125 | MX31_PIN_LD6__LD6, |
| 126 | MX31_PIN_LD7__LD7, |
| 127 | MX31_PIN_LD8__LD8, |
| 128 | MX31_PIN_LD9__LD9, |
| 129 | MX31_PIN_LD10__LD10, |
| 130 | MX31_PIN_LD11__LD11, |
| 131 | MX31_PIN_LD12__LD12, |
| 132 | MX31_PIN_LD13__LD13, |
| 133 | MX31_PIN_LD14__LD14, |
| 134 | MX31_PIN_LD15__LD15, |
| 135 | MX31_PIN_LD16__LD16, |
| 136 | MX31_PIN_LD17__LD17, |
| 137 | MX31_PIN_VSYNC3__VSYNC3, |
| 138 | MX31_PIN_HSYNC__HSYNC, |
| 139 | MX31_PIN_FPSHIFT__FPSHIFT, |
| 140 | MX31_PIN_CONTRAST__CONTRAST, |
| 141 | /* CSI */ |
| 142 | MX31_PIN_CSI_D6__CSI_D6, |
| 143 | MX31_PIN_CSI_D7__CSI_D7, |
| 144 | MX31_PIN_CSI_D8__CSI_D8, |
| 145 | MX31_PIN_CSI_D9__CSI_D9, |
| 146 | MX31_PIN_CSI_D10__CSI_D10, |
| 147 | MX31_PIN_CSI_D11__CSI_D11, |
| 148 | MX31_PIN_CSI_D12__CSI_D12, |
| 149 | MX31_PIN_CSI_D13__CSI_D13, |
| 150 | MX31_PIN_CSI_D14__CSI_D14, |
| 151 | MX31_PIN_CSI_D15__CSI_D15, |
| 152 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, |
| 153 | MX31_PIN_CSI_MCLK__CSI_MCLK, |
| 154 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, |
| 155 | MX31_PIN_CSI_VSYNC__CSI_VSYNC, |
| 156 | MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ |
| 157 | IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ |
| 158 | }; |
| 159 | |
| 160 | /* |
| 161 | * Camera support |
| 162 | */ |
| 163 | static phys_addr_t mx3_camera_base __initdata; |
| 164 | #define MX31_3DS_CAMERA_BUF_SIZE SZ_8M |
| 165 | |
| 166 | #define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) |
| 167 | #define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) |
| 168 | |
| 169 | static struct gpio mx31_3ds_camera_gpios[] = { |
| 170 | { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, |
| 171 | { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, |
| 172 | }; |
| 173 | |
| 174 | static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { |
| 175 | .flags = MX3_CAMERA_DATAWIDTH_10, |
| 176 | .mclk_10khz = 2600, |
| 177 | }; |
| 178 | |
| 179 | static int __init mx31_3ds_init_camera(void) |
| 180 | { |
| 181 | int dma, ret = -ENOMEM; |
| 182 | struct platform_device *pdev = |
| 183 | imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); |
| 184 | |
| 185 | if (IS_ERR(pdev)) |
| 186 | return PTR_ERR(pdev); |
| 187 | |
| 188 | if (!mx3_camera_base) |
| 189 | goto err; |
| 190 | |
| 191 | dma = dma_declare_coherent_memory(&pdev->dev, |
| 192 | mx3_camera_base, mx3_camera_base, |
| 193 | MX31_3DS_CAMERA_BUF_SIZE, |
| 194 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); |
| 195 | |
| 196 | if (!(dma & DMA_MEMORY_MAP)) |
| 197 | goto err; |
| 198 | |
| 199 | ret = platform_device_add(pdev); |
| 200 | if (ret) |
| 201 | err: |
| 202 | platform_device_put(pdev); |
| 203 | |
| 204 | return ret; |
| 205 | } |
| 206 | |
| 207 | static int mx31_3ds_camera_power(struct device *dev, int on) |
| 208 | { |
| 209 | /* enable or disable the camera */ |
| 210 | pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); |
| 211 | gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); |
| 212 | |
| 213 | if (!on) |
| 214 | goto out; |
| 215 | |
| 216 | /* If enabled, give a reset impulse */ |
| 217 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); |
| 218 | msleep(20); |
| 219 | gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); |
| 220 | msleep(100); |
| 221 | |
| 222 | out: |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static struct i2c_board_info mx31_3ds_i2c_camera = { |
| 227 | I2C_BOARD_INFO("ov2640", 0x30), |
| 228 | }; |
| 229 | |
| 230 | static struct regulator_bulk_data mx31_3ds_camera_regs[] = { |
| 231 | { .supply = "cmos_vcore" }, |
| 232 | { .supply = "cmos_2v8" }, |
| 233 | }; |
| 234 | |
| 235 | static struct soc_camera_link iclink_ov2640 = { |
| 236 | .bus_id = 0, |
| 237 | .board_info = &mx31_3ds_i2c_camera, |
| 238 | .i2c_adapter_id = 0, |
| 239 | .power = mx31_3ds_camera_power, |
| 240 | .regulators = mx31_3ds_camera_regs, |
| 241 | .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), |
| 242 | }; |
| 243 | |
| 244 | static struct platform_device mx31_3ds_ov2640 = { |
| 245 | .name = "soc-camera-pdrv", |
| 246 | .id = 0, |
| 247 | .dev = { |
| 248 | .platform_data = &iclink_ov2640, |
| 249 | }, |
| 250 | }; |
| 251 | |
| 252 | /* |
| 253 | * FB support |
| 254 | */ |
| 255 | static const struct fb_videomode fb_modedb[] = { |
| 256 | { /* 480x640 @ 60 Hz */ |
| 257 | .name = "Epson-VGA", |
| 258 | .refresh = 60, |
| 259 | .xres = 480, |
| 260 | .yres = 640, |
| 261 | .pixclock = 41701, |
| 262 | .left_margin = 20, |
| 263 | .right_margin = 41, |
| 264 | .upper_margin = 10, |
| 265 | .lower_margin = 5, |
| 266 | .hsync_len = 20, |
| 267 | .vsync_len = 10, |
| 268 | .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, |
| 269 | .vmode = FB_VMODE_NONINTERLACED, |
| 270 | .flag = 0, |
| 271 | }, |
| 272 | }; |
| 273 | |
| 274 | static struct ipu_platform_data mx3_ipu_data = { |
| 275 | .irq_base = MXC_IPU_IRQ_START, |
| 276 | }; |
| 277 | |
| 278 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { |
| 279 | .name = "Epson-VGA", |
| 280 | .mode = fb_modedb, |
| 281 | .num_modes = ARRAY_SIZE(fb_modedb), |
| 282 | }; |
| 283 | |
| 284 | /* LCD */ |
| 285 | static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { |
| 286 | .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), |
| 287 | .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), |
| 288 | }; |
| 289 | |
| 290 | /* |
| 291 | * Support for SD card slot in personality board |
| 292 | */ |
| 293 | #define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) |
| 294 | #define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) |
| 295 | |
| 296 | static struct gpio mx31_3ds_sdhc1_gpios[] = { |
| 297 | { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, |
| 298 | { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, |
| 299 | }; |
| 300 | |
| 301 | static int mx31_3ds_sdhc1_init(struct device *dev, |
| 302 | irq_handler_t detect_irq, |
| 303 | void *data) |
| 304 | { |
| 305 | int ret; |
| 306 | |
| 307 | ret = gpio_request_array(mx31_3ds_sdhc1_gpios, |
| 308 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); |
| 309 | if (ret) { |
| 310 | pr_warning("Unable to request the SD/MMC GPIOs.\n"); |
| 311 | return ret; |
| 312 | } |
| 313 | |
| 314 | ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), |
| 315 | detect_irq, IRQF_DISABLED | |
| 316 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
| 317 | "sdhc1-detect", data); |
| 318 | if (ret) { |
| 319 | pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); |
| 320 | goto gpio_free; |
| 321 | } |
| 322 | |
| 323 | return 0; |
| 324 | |
| 325 | gpio_free: |
| 326 | gpio_free_array(mx31_3ds_sdhc1_gpios, |
| 327 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); |
| 328 | return ret; |
| 329 | } |
| 330 | |
| 331 | static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) |
| 332 | { |
| 333 | free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data); |
| 334 | gpio_free_array(mx31_3ds_sdhc1_gpios, |
| 335 | ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); |
| 336 | } |
| 337 | |
| 338 | static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) |
| 339 | { |
| 340 | /* |
| 341 | * While the voltage stuff is done by the driver, activate the |
| 342 | * Buffer Enable Pin only if there is a card in slot to fix the card |
| 343 | * voltage issue caused by bi-directional chip TXB0108 on 3Stack. |
| 344 | * Done here because at this stage we have for sure a debounced value |
| 345 | * of the presence of the card, showed by the value of vdd. |
| 346 | * 7 == ilog2(MMC_VDD_165_195) |
| 347 | */ |
| 348 | if (vdd > 7) |
| 349 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); |
| 350 | else |
| 351 | gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); |
| 352 | } |
| 353 | |
| 354 | static struct imxmmc_platform_data sdhc1_pdata = { |
| 355 | .init = mx31_3ds_sdhc1_init, |
| 356 | .exit = mx31_3ds_sdhc1_exit, |
| 357 | .setpower = mx31_3ds_sdhc1_setpower, |
| 358 | }; |
| 359 | |
| 360 | /* |
| 361 | * Matrix keyboard |
| 362 | */ |
| 363 | |
| 364 | static const uint32_t mx31_3ds_keymap[] = { |
| 365 | KEY(0, 0, KEY_UP), |
| 366 | KEY(0, 1, KEY_DOWN), |
| 367 | KEY(1, 0, KEY_RIGHT), |
| 368 | KEY(1, 1, KEY_LEFT), |
| 369 | KEY(1, 2, KEY_ENTER), |
| 370 | KEY(2, 0, KEY_F6), |
| 371 | KEY(2, 1, KEY_F8), |
| 372 | KEY(2, 2, KEY_F9), |
| 373 | KEY(2, 3, KEY_F10), |
| 374 | }; |
| 375 | |
| 376 | static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { |
| 377 | .keymap = mx31_3ds_keymap, |
| 378 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), |
| 379 | }; |
| 380 | |
| 381 | /* Regulators */ |
| 382 | static struct regulator_init_data pwgtx_init = { |
| 383 | .constraints = { |
| 384 | .boot_on = 1, |
| 385 | .always_on = 1, |
| 386 | }, |
| 387 | }; |
| 388 | |
| 389 | static struct regulator_init_data gpo_init = { |
| 390 | .constraints = { |
| 391 | .boot_on = 1, |
| 392 | .always_on = 1, |
| 393 | } |
| 394 | }; |
| 395 | |
| 396 | static struct regulator_consumer_supply vmmc2_consumers[] = { |
| 397 | REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"), |
| 398 | }; |
| 399 | |
| 400 | static struct regulator_init_data vmmc2_init = { |
| 401 | .constraints = { |
| 402 | .min_uV = 3000000, |
| 403 | .max_uV = 3000000, |
| 404 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
| 405 | REGULATOR_CHANGE_STATUS, |
| 406 | }, |
| 407 | .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), |
| 408 | .consumer_supplies = vmmc2_consumers, |
| 409 | }; |
| 410 | |
| 411 | static struct regulator_consumer_supply vmmc1_consumers[] = { |
| 412 | REGULATOR_SUPPLY("vcore", "spi0.0"), |
| 413 | REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), |
| 414 | }; |
| 415 | |
| 416 | static struct regulator_init_data vmmc1_init = { |
| 417 | .constraints = { |
| 418 | .min_uV = 2800000, |
| 419 | .max_uV = 2800000, |
| 420 | .apply_uV = 1, |
| 421 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
| 422 | REGULATOR_CHANGE_STATUS, |
| 423 | }, |
| 424 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), |
| 425 | .consumer_supplies = vmmc1_consumers, |
| 426 | }; |
| 427 | |
| 428 | static struct regulator_consumer_supply vgen_consumers[] = { |
| 429 | REGULATOR_SUPPLY("vdd", "spi0.0"), |
| 430 | }; |
| 431 | |
| 432 | static struct regulator_init_data vgen_init = { |
| 433 | .constraints = { |
| 434 | .min_uV = 1800000, |
| 435 | .max_uV = 1800000, |
| 436 | .apply_uV = 1, |
| 437 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
| 438 | REGULATOR_CHANGE_STATUS, |
| 439 | }, |
| 440 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), |
| 441 | .consumer_supplies = vgen_consumers, |
| 442 | }; |
| 443 | |
| 444 | static struct regulator_consumer_supply vvib_consumers[] = { |
| 445 | REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), |
| 446 | }; |
| 447 | |
| 448 | static struct regulator_init_data vvib_init = { |
| 449 | .constraints = { |
| 450 | .min_uV = 1300000, |
| 451 | .max_uV = 1300000, |
| 452 | .apply_uV = 1, |
| 453 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
| 454 | REGULATOR_CHANGE_STATUS, |
| 455 | }, |
| 456 | .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), |
| 457 | .consumer_supplies = vvib_consumers, |
| 458 | }; |
| 459 | |
| 460 | static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { |
| 461 | { |
| 462 | .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ |
| 463 | .init_data = &pwgtx_init, |
| 464 | }, { |
| 465 | .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ |
| 466 | .init_data = &pwgtx_init, |
| 467 | }, { |
| 468 | |
| 469 | .id = MC13783_REG_GPO1, /* Turn on 1.8V */ |
| 470 | .init_data = &gpo_init, |
| 471 | }, { |
| 472 | .id = MC13783_REG_GPO3, /* Turn on 3.3V */ |
| 473 | .init_data = &gpo_init, |
| 474 | }, { |
| 475 | .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ |
| 476 | .init_data = &vmmc2_init, |
| 477 | }, { |
| 478 | .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ |
| 479 | .init_data = &vmmc1_init, |
| 480 | }, { |
| 481 | .id = MC13783_REG_VGEN, /* Power LCD */ |
| 482 | .init_data = &vgen_init, |
| 483 | }, { |
| 484 | .id = MC13783_REG_VVIB, /* Power CMOS */ |
| 485 | .init_data = &vvib_init, |
| 486 | }, |
| 487 | }; |
| 488 | |
| 489 | /* MC13783 */ |
| 490 | static struct mc13xxx_platform_data mc13783_pdata = { |
| 491 | .regulators = { |
| 492 | .regulators = mx31_3ds_regulators, |
| 493 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), |
| 494 | }, |
| 495 | .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, |
| 496 | }; |
| 497 | |
| 498 | /* SPI */ |
| 499 | static int spi0_internal_chipselect[] = { |
| 500 | MXC_SPI_CS(2), |
| 501 | }; |
| 502 | |
| 503 | static const struct spi_imx_master spi0_pdata __initconst = { |
| 504 | .chipselect = spi0_internal_chipselect, |
| 505 | .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), |
| 506 | }; |
| 507 | |
| 508 | static int spi1_internal_chipselect[] = { |
| 509 | MXC_SPI_CS(0), |
| 510 | MXC_SPI_CS(2), |
| 511 | }; |
| 512 | |
| 513 | static const struct spi_imx_master spi1_pdata __initconst = { |
| 514 | .chipselect = spi1_internal_chipselect, |
| 515 | .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), |
| 516 | }; |
| 517 | |
| 518 | static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { |
| 519 | { |
| 520 | .modalias = "mc13783", |
| 521 | .max_speed_hz = 1000000, |
| 522 | .bus_num = 1, |
| 523 | .chip_select = 1, /* SS2 */ |
| 524 | .platform_data = &mc13783_pdata, |
| 525 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), |
| 526 | .mode = SPI_CS_HIGH, |
| 527 | }, { |
| 528 | .modalias = "l4f00242t03", |
| 529 | .max_speed_hz = 5000000, |
| 530 | .bus_num = 0, |
| 531 | .chip_select = 0, /* SS2 */ |
| 532 | .platform_data = &mx31_3ds_l4f00242t03_pdata, |
| 533 | }, |
| 534 | }; |
| 535 | |
| 536 | /* |
| 537 | * NAND Flash |
| 538 | */ |
| 539 | static const struct mxc_nand_platform_data |
| 540 | mx31_3ds_nand_board_info __initconst = { |
| 541 | .width = 1, |
| 542 | .hw_ecc = 1, |
| 543 | #ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT |
| 544 | .flash_bbt = 1, |
| 545 | #endif |
| 546 | }; |
| 547 | |
| 548 | /* |
| 549 | * USB OTG |
| 550 | */ |
| 551 | |
| 552 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ |
| 553 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) |
| 554 | |
| 555 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) |
| 556 | #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) |
| 557 | |
| 558 | static int mx31_3ds_usbotg_init(void) |
| 559 | { |
| 560 | int err; |
| 561 | |
| 562 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); |
| 563 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); |
| 564 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); |
| 565 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); |
| 566 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); |
| 567 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); |
| 568 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); |
| 569 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); |
| 570 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); |
| 571 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); |
| 572 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); |
| 573 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); |
| 574 | |
| 575 | err = gpio_request(USBOTG_RST_B, "otgusb-reset"); |
| 576 | if (err) { |
| 577 | pr_err("Failed to request the USB OTG reset gpio\n"); |
| 578 | return err; |
| 579 | } |
| 580 | |
| 581 | err = gpio_direction_output(USBOTG_RST_B, 0); |
| 582 | if (err) { |
| 583 | pr_err("Failed to drive the USB OTG reset gpio\n"); |
| 584 | goto usbotg_free_reset; |
| 585 | } |
| 586 | |
| 587 | mdelay(1); |
| 588 | gpio_set_value(USBOTG_RST_B, 1); |
| 589 | return 0; |
| 590 | |
| 591 | usbotg_free_reset: |
| 592 | gpio_free(USBOTG_RST_B); |
| 593 | return err; |
| 594 | } |
| 595 | |
| 596 | static int mx31_3ds_otg_init(struct platform_device *pdev) |
| 597 | { |
| 598 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); |
| 599 | } |
| 600 | |
| 601 | static int mx31_3ds_host2_init(struct platform_device *pdev) |
| 602 | { |
| 603 | int err; |
| 604 | |
| 605 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); |
| 606 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); |
| 607 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); |
| 608 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); |
| 609 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); |
| 610 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); |
| 611 | mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); |
| 612 | mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); |
| 613 | mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); |
| 614 | mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); |
| 615 | mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); |
| 616 | mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); |
| 617 | |
| 618 | err = gpio_request(USBH2_RST_B, "usbh2-reset"); |
| 619 | if (err) { |
| 620 | pr_err("Failed to request the USB Host 2 reset gpio\n"); |
| 621 | return err; |
| 622 | } |
| 623 | |
| 624 | err = gpio_direction_output(USBH2_RST_B, 0); |
| 625 | if (err) { |
| 626 | pr_err("Failed to drive the USB Host 2 reset gpio\n"); |
| 627 | goto usbotg_free_reset; |
| 628 | } |
| 629 | |
| 630 | mdelay(1); |
| 631 | gpio_set_value(USBH2_RST_B, 1); |
| 632 | |
| 633 | mdelay(10); |
| 634 | |
| 635 | return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); |
| 636 | |
| 637 | usbotg_free_reset: |
| 638 | gpio_free(USBH2_RST_B); |
| 639 | return err; |
| 640 | } |
| 641 | |
| 642 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 643 | .init = mx31_3ds_otg_init, |
| 644 | .portsc = MXC_EHCI_MODE_ULPI, |
| 645 | }; |
| 646 | |
| 647 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 648 | .init = mx31_3ds_host2_init, |
| 649 | .portsc = MXC_EHCI_MODE_ULPI, |
| 650 | }; |
| 651 | |
| 652 | static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { |
| 653 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 654 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 655 | }; |
| 656 | |
| 657 | static int otg_mode_host; |
| 658 | |
| 659 | static int __init mx31_3ds_otg_mode(char *options) |
| 660 | { |
| 661 | if (!strcmp(options, "host")) |
| 662 | otg_mode_host = 1; |
| 663 | else if (!strcmp(options, "device")) |
| 664 | otg_mode_host = 0; |
| 665 | else |
| 666 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 667 | "Defaulting to device\n"); |
| 668 | return 0; |
| 669 | } |
| 670 | __setup("otg_mode=", mx31_3ds_otg_mode); |
| 671 | |
| 672 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 673 | .flags = IMXUART_HAVE_RTSCTS, |
| 674 | }; |
| 675 | |
| 676 | static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { |
| 677 | .bitrate = 100000, |
| 678 | }; |
| 679 | |
| 680 | static struct platform_device *devices[] __initdata = { |
| 681 | &mx31_3ds_ov2640, |
| 682 | }; |
| 683 | |
| 684 | static void __init mx31_3ds_init(void) |
| 685 | { |
| 686 | int ret; |
| 687 | |
| 688 | imx31_soc_init(); |
| 689 | |
| 690 | /* Configure SPI1 IOMUX */ |
| 691 | mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); |
| 692 | |
| 693 | mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), |
| 694 | "mx31_3ds"); |
| 695 | |
| 696 | imx31_add_imx_uart0(&uart_pdata); |
| 697 | imx31_add_mxc_nand(&mx31_3ds_nand_board_info); |
| 698 | |
| 699 | imx31_add_spi_imx1(&spi1_pdata); |
| 700 | spi_register_board_info(mx31_3ds_spi_devs, |
| 701 | ARRAY_SIZE(mx31_3ds_spi_devs)); |
| 702 | |
| 703 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 704 | |
| 705 | imx31_add_imx_keypad(&mx31_3ds_keymap_data); |
| 706 | |
| 707 | mx31_3ds_usbotg_init(); |
| 708 | if (otg_mode_host) { |
| 709 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
| 710 | ULPI_OTG_DRVVBUS_EXT); |
| 711 | if (otg_pdata.otg) |
| 712 | imx31_add_mxc_ehci_otg(&otg_pdata); |
| 713 | } |
| 714 | usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
| 715 | ULPI_OTG_DRVVBUS_EXT); |
| 716 | if (usbh2_pdata.otg) |
| 717 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 718 | |
| 719 | if (!otg_mode_host) |
| 720 | imx31_add_fsl_usb2_udc(&usbotg_pdata); |
| 721 | |
| 722 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
| 723 | printk(KERN_WARNING "Init of the debug board failed, all " |
| 724 | "devices on the debug board are unusable.\n"); |
| 725 | imx31_add_imx2_wdt(NULL); |
| 726 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); |
| 727 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
| 728 | |
| 729 | imx31_add_spi_imx0(&spi0_pdata); |
| 730 | imx31_add_ipu_core(&mx3_ipu_data); |
| 731 | imx31_add_mx3_sdc_fb(&mx3fb_pdata); |
| 732 | |
| 733 | /* CSI */ |
| 734 | /* Camera power: default - off */ |
| 735 | ret = gpio_request_array(mx31_3ds_camera_gpios, |
| 736 | ARRAY_SIZE(mx31_3ds_camera_gpios)); |
| 737 | if (ret) { |
| 738 | pr_err("Failed to request camera gpios"); |
| 739 | iclink_ov2640.power = NULL; |
| 740 | } |
| 741 | |
| 742 | mx31_3ds_init_camera(); |
| 743 | } |
| 744 | |
| 745 | static void __init mx31_3ds_timer_init(void) |
| 746 | { |
| 747 | mx31_clocks_init(26000000); |
| 748 | } |
| 749 | |
| 750 | static struct sys_timer mx31_3ds_timer = { |
| 751 | .init = mx31_3ds_timer_init, |
| 752 | }; |
| 753 | |
| 754 | static void __init mx31_3ds_reserve(void) |
| 755 | { |
| 756 | /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ |
| 757 | mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE, |
| 758 | MX31_3DS_CAMERA_BUF_SIZE); |
| 759 | memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE); |
| 760 | memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE); |
| 761 | } |
| 762 | |
| 763 | MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") |
| 764 | /* Maintainer: Freescale Semiconductor, Inc. */ |
| 765 | .atag_offset = 0x100, |
| 766 | .map_io = mx31_map_io, |
| 767 | .init_early = imx31_init_early, |
| 768 | .init_irq = mx31_init_irq, |
| 769 | .handle_irq = imx31_handle_irq, |
| 770 | .timer = &mx31_3ds_timer, |
| 771 | .init_machine = mx31_3ds_init, |
| 772 | .reserve = mx31_3ds_reserve, |
| 773 | .restart = mxc_restart, |
| 774 | MACHINE_END |