[deliverable/linux.git] / arch / arm / mach-iop32x / irq.c

/*
 * arch/arm/mach-iop32x/irq.c
 *
 * Generic IOP32X IRQ handling functionality
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>

static u32 iop32x_mask;

static void intctl_write(u32 val)
{
	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
}

static void intstr_write(u32 val)
{
	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
}

static void
iop32x_irq_mask(struct irq_data *d)
{
	iop32x_mask &= ~(1 << d->irq);
	intctl_write(iop32x_mask);
}

static void
iop32x_irq_unmask(struct irq_data *d)
{
	iop32x_mask |= 1 << d->irq;
	intctl_write(iop32x_mask);
}

struct irq_chip ext_chip = {
	.name		= "IOP32x",
	.irq_ack	= iop32x_irq_mask,
	.irq_mask	= iop32x_irq_mask,
	.irq_unmask	= iop32x_irq_unmask,
};

void __init iop32x_init_irq(void)
{
	int i;

	iop_init_cp6_handler();

	intctl_write(0);
	intstr_write(0);
	if (machine_is_glantank() ||
	    machine_is_iq80321() ||
	    machine_is_iq31244() ||
	    machine_is_n2100() ||
	    machine_is_em7210())
		*IOP3XX_PCIIRSR = 0x0f;

	for (i = 0; i < NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}
}
Commit	Line	Data
	1	/*
	2	* arch/arm/mach-iop32x/irq.c
	3	*
	4	* Generic IOP32X IRQ handling functionality
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <asm/mach/irq.h>
	18	#include <asm/irq.h>
	19	#include <mach/hardware.h>
	20	#include <asm/mach-types.h>
	21
	22	static u32 iop32x_mask;
	23
	24	static void intctl_write(u32 val)
	25	{
	26	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
	27	}
	28
	29	static void intstr_write(u32 val)
	30	{
	31	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
	32	}
	33
	34	static void
	35	iop32x_irq_mask(struct irq_data *d)
	36	{
	37	iop32x_mask &= ~(1 << d->irq);
	38	intctl_write(iop32x_mask);
	39	}
	40
	41	static void
	42	iop32x_irq_unmask(struct irq_data *d)
	43	{
	44	iop32x_mask \|= 1 << d->irq;
	45	intctl_write(iop32x_mask);
	46	}
	47
	48	struct irq_chip ext_chip = {
	49	.name = "IOP32x",
	50	.irq_ack = iop32x_irq_mask,
	51	.irq_mask = iop32x_irq_mask,
	52	.irq_unmask = iop32x_irq_unmask,
	53	};
	54
	55	void __init iop32x_init_irq(void)
	56	{
	57	int i;
	58
	59	iop_init_cp6_handler();
	60
	61	intctl_write(0);
	62	intstr_write(0);
	63	if (machine_is_glantank() \|\|
	64	machine_is_iq80321() \|\|
	65	machine_is_iq31244() \|\|
	66	machine_is_n2100() \|\|
	67	machine_is_em7210())
	68	*IOP3XX_PCIIRSR = 0x0f;
	69
	70	for (i = 0; i < NR_IRQS; i++) {
	71	irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
	72	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
	73	}
	74	}