| | 1 | /* |
| | 2 | * OMAP44xx Clock Management register bits |
| | 3 | * |
| | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
| | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| | 6 | * |
| | 7 | * Paul Walmsley (paul@pwsan.com) |
| | 8 | * Rajendra Nayak (rnayak@ti.com) |
| | 9 | * Benoit Cousson (b-cousson@ti.com) |
| | 10 | * |
| | 11 | * This file is automatically generated from the OMAP hardware databases. |
| | 12 | * We respectfully ask that any modifications to this file be coordinated |
| | 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
| | 14 | * authors above to ensure that the autogeneration scripts are kept |
| | 15 | * up-to-date with the file contents. |
| | 16 | * |
| | 17 | * This program is free software; you can redistribute it and/or modify |
| | 18 | * it under the terms of the GNU General Public License version 2 as |
| | 19 | * published by the Free Software Foundation. |
| | 20 | */ |
| | 21 | |
| | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| | 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| | 24 | |
| | 25 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| | 26 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 |
| | 27 | #define OMAP4430_ABE_DYNDEP_WIDTH 0x1 |
| | 28 | #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) |
| | 29 | |
| | 30 | /* |
| | 31 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| | 32 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 33 | */ |
| | 34 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
| | 35 | #define OMAP4430_ABE_STATDEP_WIDTH 0x1 |
| | 36 | #define OMAP4430_ABE_STATDEP_MASK (1 << 3) |
| | 37 | |
| | 38 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 39 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 |
| | 40 | #define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 |
| | 41 | #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) |
| | 42 | |
| | 43 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| | 44 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 |
| | 45 | #define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 |
| | 46 | #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) |
| | 47 | |
| | 48 | /* |
| | 49 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, |
| | 50 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, |
| | 51 | * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB |
| | 52 | */ |
| | 53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 |
| | 54 | #define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 |
| | 55 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
| | 56 | |
| | 57 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 58 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 |
| | 59 | #define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 |
| | 60 | #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) |
| | 61 | |
| | 62 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ |
| | 63 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 |
| | 64 | #define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 |
| | 65 | #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) |
| | 66 | |
| | 67 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 68 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 |
| | 69 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 |
| | 70 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) |
| | 71 | |
| | 72 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 73 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 |
| | 74 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 |
| | 75 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) |
| | 76 | |
| | 77 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 78 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 |
| | 79 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 |
| | 80 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) |
| | 81 | |
| | 82 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 83 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 |
| | 84 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 |
| | 85 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) |
| | 86 | |
| | 87 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 88 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 |
| | 89 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 |
| | 90 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) |
| | 91 | |
| | 92 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 93 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 |
| | 94 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 |
| | 95 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) |
| | 96 | |
| | 97 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 98 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 |
| | 99 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 |
| | 100 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) |
| | 101 | |
| | 102 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 103 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 |
| | 104 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 |
| | 105 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) |
| | 106 | |
| | 107 | /* Used by CM_CAM_CLKSTCTRL */ |
| | 108 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 |
| | 109 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 |
| | 110 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) |
| | 111 | |
| | 112 | /* Used by CM_ALWON_CLKSTCTRL */ |
| | 113 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 |
| | 114 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 |
| | 115 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) |
| | 116 | |
| | 117 | /* Used by CM_EMU_CLKSTCTRL */ |
| | 118 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 |
| | 119 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 |
| | 120 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) |
| | 121 | |
| | 122 | /* Used by CM_L4CFG_CLKSTCTRL */ |
| | 123 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 |
| | 124 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 |
| | 125 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) |
| | 126 | |
| | 127 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| | 128 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 |
| | 129 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 |
| | 130 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) |
| | 131 | |
| | 132 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 133 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 |
| | 134 | #define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 |
| | 135 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) |
| | 136 | |
| | 137 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 138 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 |
| | 139 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 |
| | 140 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) |
| | 141 | |
| | 142 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 143 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 |
| | 144 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 |
| | 145 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) |
| | 146 | |
| | 147 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 148 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 |
| | 149 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 |
| | 150 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) |
| | 151 | |
| | 152 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 153 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 |
| | 154 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 |
| | 155 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) |
| | 156 | |
| | 157 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 158 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 |
| | 159 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 |
| | 160 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) |
| | 161 | |
| | 162 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 163 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 |
| | 164 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 |
| | 165 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) |
| | 166 | |
| | 167 | /* Used by CM_DSS_CLKSTCTRL */ |
| | 168 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 |
| | 169 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 |
| | 170 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) |
| | 171 | |
| | 172 | /* Used by CM_DSS_CLKSTCTRL */ |
| | 173 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 |
| | 174 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 |
| | 175 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) |
| | 176 | |
| | 177 | /* Used by CM_DUCATI_CLKSTCTRL */ |
| | 178 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 |
| | 179 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 |
| | 180 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) |
| | 181 | |
| | 182 | /* Used by CM_EMU_CLKSTCTRL */ |
| | 183 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 |
| | 184 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 |
| | 185 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) |
| | 186 | |
| | 187 | /* Used by CM_CAM_CLKSTCTRL */ |
| | 188 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 |
| | 189 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 |
| | 190 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) |
| | 191 | |
| | 192 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 193 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 |
| | 194 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 |
| | 195 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) |
| | 196 | |
| | 197 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 198 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 |
| | 199 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 |
| | 200 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) |
| | 201 | |
| | 202 | /* Used by CM_DSS_CLKSTCTRL */ |
| | 203 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 |
| | 204 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 |
| | 205 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) |
| | 206 | |
| | 207 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 208 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 |
| | 209 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 |
| | 210 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) |
| | 211 | |
| | 212 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 213 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 |
| | 214 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 |
| | 215 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) |
| | 216 | |
| | 217 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 218 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 |
| | 219 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 |
| | 220 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) |
| | 221 | |
| | 222 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 223 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 |
| | 224 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 |
| | 225 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) |
| | 226 | |
| | 227 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 228 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 |
| | 229 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 |
| | 230 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) |
| | 231 | |
| | 232 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 233 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 |
| | 234 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 |
| | 235 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) |
| | 236 | |
| | 237 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 238 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 |
| | 239 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 |
| | 240 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) |
| | 241 | |
| | 242 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 243 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 |
| | 244 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 |
| | 245 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) |
| | 246 | |
| | 247 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 248 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 |
| | 249 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 |
| | 250 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) |
| | 251 | |
| | 252 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 253 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 |
| | 254 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 |
| | 255 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) |
| | 256 | |
| | 257 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 258 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 |
| | 259 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 |
| | 260 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) |
| | 261 | |
| | 262 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 263 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 |
| | 264 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 |
| | 265 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) |
| | 266 | |
| | 267 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 268 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 |
| | 269 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 |
| | 270 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) |
| | 271 | |
| | 272 | /* Used by CM_CAM_CLKSTCTRL */ |
| | 273 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 |
| | 274 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 |
| | 275 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) |
| | 276 | |
| | 277 | /* Used by CM_IVAHD_CLKSTCTRL */ |
| | 278 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 |
| | 279 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 |
| | 280 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) |
| | 281 | |
| | 282 | /* Used by CM_D2D_CLKSTCTRL */ |
| | 283 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 |
| | 284 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 |
| | 285 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) |
| | 286 | |
| | 287 | /* Used by CM_L3_1_CLKSTCTRL */ |
| | 288 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 |
| | 289 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 |
| | 290 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) |
| | 291 | |
| | 292 | /* Used by CM_L3_2_CLKSTCTRL */ |
| | 293 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 |
| | 294 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 |
| | 295 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) |
| | 296 | |
| | 297 | /* Used by CM_D2D_CLKSTCTRL */ |
| | 298 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 |
| | 299 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 |
| | 300 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) |
| | 301 | |
| | 302 | /* Used by CM_SDMA_CLKSTCTRL */ |
| | 303 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 |
| | 304 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 |
| | 305 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) |
| | 306 | |
| | 307 | /* Used by CM_DSS_CLKSTCTRL */ |
| | 308 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 |
| | 309 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 |
| | 310 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) |
| | 311 | |
| | 312 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 313 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 |
| | 314 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 |
| | 315 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) |
| | 316 | |
| | 317 | /* Used by CM_GFX_CLKSTCTRL */ |
| | 318 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 |
| | 319 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 |
| | 320 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) |
| | 321 | |
| | 322 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 323 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 |
| | 324 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 |
| | 325 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) |
| | 326 | |
| | 327 | /* Used by CM_L3INSTR_CLKSTCTRL */ |
| | 328 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 |
| | 329 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 |
| | 330 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) |
| | 331 | |
| | 332 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| | 333 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 |
| | 334 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 |
| | 335 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) |
| | 336 | |
| | 337 | /* Used by CM_ALWON_CLKSTCTRL */ |
| | 338 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 |
| | 339 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 |
| | 340 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) |
| | 341 | |
| | 342 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| | 343 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 |
| | 344 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 |
| | 345 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) |
| | 346 | |
| | 347 | /* Used by CM_L4CFG_CLKSTCTRL */ |
| | 348 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 |
| | 349 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 |
| | 350 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) |
| | 351 | |
| | 352 | /* Used by CM_D2D_CLKSTCTRL */ |
| | 353 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 |
| | 354 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 |
| | 355 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) |
| | 356 | |
| | 357 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 358 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 |
| | 359 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 |
| | 360 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) |
| | 361 | |
| | 362 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 363 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 |
| | 364 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 |
| | 365 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) |
| | 366 | |
| | 367 | /* Used by CM_L4SEC_CLKSTCTRL */ |
| | 368 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 |
| | 369 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 |
| | 370 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) |
| | 371 | |
| | 372 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 373 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 |
| | 374 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 |
| | 375 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) |
| | 376 | |
| | 377 | /* Used by CM_MPU_CLKSTCTRL */ |
| | 378 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 |
| | 379 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 |
| | 380 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) |
| | 381 | |
| | 382 | /* Used by CM1_ABE_CLKSTCTRL */ |
| | 383 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 |
| | 384 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 |
| | 385 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) |
| | 386 | |
| | 387 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 388 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 |
| | 389 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 |
| | 390 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) |
| | 391 | |
| | 392 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 393 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 |
| | 394 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 |
| | 395 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) |
| | 396 | |
| | 397 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 398 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 |
| | 399 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 |
| | 400 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) |
| | 401 | |
| | 402 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 403 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 |
| | 404 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 |
| | 405 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) |
| | 406 | |
| | 407 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 408 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 |
| | 409 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 |
| | 410 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) |
| | 411 | |
| | 412 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 413 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 |
| | 414 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 |
| | 415 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) |
| | 416 | |
| | 417 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 418 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 |
| | 419 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) |
| | 420 | |
| | 421 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 422 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 |
| | 423 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 |
| | 424 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) |
| | 425 | |
| | 426 | /* Used by CM_L4PER_CLKSTCTRL */ |
| | 427 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 |
| | 428 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 |
| | 429 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) |
| | 430 | |
| | 431 | /* Used by CM_MEMIF_CLKSTCTRL */ |
| | 432 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 |
| | 433 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 |
| | 434 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) |
| | 435 | |
| | 436 | /* Used by CM_GFX_CLKSTCTRL */ |
| | 437 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 |
| | 438 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 |
| | 439 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) |
| | 440 | |
| | 441 | /* Used by CM_ALWON_CLKSTCTRL */ |
| | 442 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 |
| | 443 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 |
| | 444 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) |
| | 445 | |
| | 446 | /* Used by CM_ALWON_CLKSTCTRL */ |
| | 447 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 |
| | 448 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 |
| | 449 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) |
| | 450 | |
| | 451 | /* Used by CM_ALWON_CLKSTCTRL */ |
| | 452 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 |
| | 453 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 |
| | 454 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) |
| | 455 | |
| | 456 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 457 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 |
| | 458 | #define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 |
| | 459 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) |
| | 460 | |
| | 461 | /* Used by CM_TESLA_CLKSTCTRL */ |
| | 462 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 |
| | 463 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 |
| | 464 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) |
| | 465 | |
| | 466 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 467 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 |
| | 468 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 |
| | 469 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) |
| | 470 | |
| | 471 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 472 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 |
| | 473 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 |
| | 474 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) |
| | 475 | |
| | 476 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 477 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 |
| | 478 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 |
| | 479 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) |
| | 480 | |
| | 481 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 482 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 |
| | 483 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 |
| | 484 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) |
| | 485 | |
| | 486 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 487 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 |
| | 488 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 |
| | 489 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) |
| | 490 | |
| | 491 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 492 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 |
| | 493 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 |
| | 494 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) |
| | 495 | |
| | 496 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 497 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 |
| | 498 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 |
| | 499 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) |
| | 500 | |
| | 501 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 502 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 |
| | 503 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 |
| | 504 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) |
| | 505 | |
| | 506 | /* Used by CM_L3INIT_CLKSTCTRL */ |
| | 507 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 |
| | 508 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 |
| | 509 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) |
| | 510 | |
| | 511 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 512 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 |
| | 513 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 |
| | 514 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) |
| | 515 | |
| | 516 | /* Used by CM_WKUP_CLKSTCTRL */ |
| | 517 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 |
| | 518 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 |
| | 519 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) |
| | 520 | |
| | 521 | /* |
| | 522 | * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, |
| | 523 | * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
| | 524 | * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, |
| | 525 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, |
| | 526 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, |
| | 527 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL |
| | 528 | */ |
| | 529 | #define OMAP4430_CLKSEL_SHIFT 24 |
| | 530 | #define OMAP4430_CLKSEL_WIDTH 0x1 |
| | 531 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
| | 532 | |
| | 533 | /* |
| | 534 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, |
| | 535 | * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL |
| | 536 | */ |
| | 537 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
| | 538 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 |
| | 539 | #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) |
| | 540 | |
| | 541 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ |
| | 542 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
| | 543 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 |
| | 544 | #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) |
| | 545 | |
| | 546 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ |
| | 547 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
| | 548 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 |
| | 549 | #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) |
| | 550 | |
| | 551 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| | 552 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
| | 553 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 |
| | 554 | #define OMAP4430_CLKSEL_60M_MASK (1 << 24) |
| | 555 | |
| | 556 | /* Used by CM_MPU_MPU_CLKCTRL */ |
| | 557 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 |
| | 558 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 |
| | 559 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) |
| | 560 | |
| | 561 | /* Used by CM1_ABE_AESS_CLKCTRL */ |
| | 562 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
| | 563 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 |
| | 564 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) |
| | 565 | |
| | 566 | /* Used by CM_CLKSEL_CORE */ |
| | 567 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
| | 568 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 |
| | 569 | #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) |
| | 570 | |
| | 571 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ |
| | 572 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 |
| | 573 | #define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 |
| | 574 | #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) |
| | 575 | |
| | 576 | /* Used by CM_WKUP_USIM_CLKCTRL */ |
| | 577 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
| | 578 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 |
| | 579 | #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) |
| | 580 | |
| | 581 | /* Used by CM_MPU_MPU_CLKCTRL */ |
| | 582 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 |
| | 583 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 |
| | 584 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) |
| | 585 | |
| | 586 | /* Used by CM_CAM_FDIF_CLKCTRL */ |
| | 587 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
| | 588 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 |
| | 589 | #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) |
| | 590 | |
| | 591 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| | 592 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
| | 593 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 |
| | 594 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) |
| | 595 | |
| | 596 | /* |
| | 597 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, |
| | 598 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| | 599 | * CM1_ABE_MCBSP3_CLKCTRL |
| | 600 | */ |
| | 601 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 |
| | 602 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 |
| | 603 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) |
| | 604 | |
| | 605 | /* Used by CM_CLKSEL_CORE */ |
| | 606 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
| | 607 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 |
| | 608 | #define OMAP4430_CLKSEL_L3_MASK (1 << 4) |
| | 609 | |
| | 610 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ |
| | 611 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 |
| | 612 | #define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 |
| | 613 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) |
| | 614 | |
| | 615 | /* Used by CM_CLKSEL_CORE */ |
| | 616 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
| | 617 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 |
| | 618 | #define OMAP4430_CLKSEL_L4_MASK (1 << 8) |
| | 619 | |
| | 620 | /* Used by CM_CLKSEL_ABE */ |
| | 621 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
| | 622 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 |
| | 623 | #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) |
| | 624 | |
| | 625 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| | 626 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
| | 627 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 |
| | 628 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) |
| | 629 | |
| | 630 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| | 631 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 |
| | 632 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 |
| | 633 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
| | 634 | |
| | 635 | /* Used by CM_GFX_GFX_CLKCTRL */ |
| | 636 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 |
| | 637 | #define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 |
| | 638 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
| | 639 | |
| | 640 | /* |
| | 641 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, |
| | 642 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL |
| | 643 | */ |
| | 644 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 |
| | 645 | #define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 |
| | 646 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
| | 647 | |
| | 648 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ |
| | 649 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 |
| | 650 | #define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 |
| | 651 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
| | 652 | |
| | 653 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 654 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
| | 655 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 |
| | 656 | #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) |
| | 657 | |
| | 658 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 659 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
| | 660 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 |
| | 661 | #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) |
| | 662 | |
| | 663 | /* |
| | 664 | * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, |
| | 665 | * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, |
| | 666 | * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, |
| | 667 | * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, |
| | 668 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, |
| | 669 | * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, |
| | 670 | * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL |
| | 671 | */ |
| | 672 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
| | 673 | #define OMAP4430_CLKTRCTRL_WIDTH 0x2 |
| | 674 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
| | 675 | |
| | 676 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| | 677 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 |
| | 678 | #define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 |
| | 679 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) |
| | 680 | |
| | 681 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| | 682 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 |
| | 683 | #define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb |
| | 684 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) |
| | 685 | |
| | 686 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 687 | #define OMAP4430_CUSTOM_SHIFT 6 |
| | 688 | #define OMAP4430_CUSTOM_WIDTH 0x2 |
| | 689 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) |
| | 690 | |
| | 691 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| | 692 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 |
| | 693 | #define OMAP4430_D2D_DYNDEP_WIDTH 0x1 |
| | 694 | #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) |
| | 695 | |
| | 696 | /* Used by CM_MPU_STATICDEP */ |
| | 697 | #define OMAP4430_D2D_STATDEP_SHIFT 18 |
| | 698 | #define OMAP4430_D2D_STATDEP_WIDTH 0x1 |
| | 699 | #define OMAP4430_D2D_STATDEP_MASK (1 << 18) |
| | 700 | |
| | 701 | /* Used by CM_CLKSEL_DPLL_MPU */ |
| | 702 | #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 |
| | 703 | #define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 |
| | 704 | #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) |
| | 705 | |
| | 706 | /* Used by CM_CLKSEL_DPLL_MPU */ |
| | 707 | #define OMAP4460_DCC_EN_SHIFT 22 |
| | 708 | #define OMAP4460_DCC_EN_MASK (1 << 22) |
| | 709 | |
| | 710 | /* |
| | 711 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, |
| | 712 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, |
| | 713 | * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, |
| | 714 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB |
| | 715 | */ |
| | 716 | #define OMAP4430_DELTAMSTEP_SHIFT 0 |
| | 717 | #define OMAP4430_DELTAMSTEP_WIDTH 0x14 |
| | 718 | #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) |
| | 719 | |
| | 720 | /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ |
| | 721 | #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 |
| | 722 | #define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 |
| | 723 | #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) |
| | 724 | |
| | 725 | /* Used by CM_DLL_CTRL */ |
| | 726 | #define OMAP4430_DLL_OVERRIDE_SHIFT 0 |
| | 727 | #define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 |
| | 728 | #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) |
| | 729 | |
| | 730 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ |
| | 731 | #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 |
| | 732 | #define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 |
| | 733 | #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) |
| | 734 | |
| | 735 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| | 736 | #define OMAP4430_DLL_RESET_SHIFT 3 |
| | 737 | #define OMAP4430_DLL_RESET_WIDTH 0x1 |
| | 738 | #define OMAP4430_DLL_RESET_MASK (1 << 3) |
| | 739 | |
| | 740 | /* |
| | 741 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| | 742 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| | 743 | * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB |
| | 744 | */ |
| | 745 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
| | 746 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 |
| | 747 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) |
| | 748 | |
| | 749 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| | 750 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 |
| | 751 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 |
| | 752 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) |
| | 753 | |
| | 754 | /* Used by CM_CLKSEL_DPLL_CORE */ |
| | 755 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 |
| | 756 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 |
| | 757 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) |
| | 758 | |
| | 759 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| | 760 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 |
| | 761 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 |
| | 762 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
| | 763 | |
| | 764 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| | 765 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 |
| | 766 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 |
| | 767 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) |
| | 768 | |
| | 769 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| | 770 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
| | 771 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 |
| | 772 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) |
| | 773 | |
| | 774 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
| | 775 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 |
| | 776 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 |
| | 777 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
| | 778 | |
| | 779 | /* |
| | 780 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| | 781 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO |
| | 782 | */ |
| | 783 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
| | 784 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 |
| | 785 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| | 786 | |
| | 787 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ |
| | 788 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 |
| | 789 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 |
| | 790 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
| | 791 | |
| | 792 | /* |
| | 793 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| | 794 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO |
| | 795 | */ |
| | 796 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 |
| | 797 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 |
| | 798 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) |
| | 799 | |
| | 800 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ |
| | 801 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 |
| | 802 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 |
| | 803 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) |
| | 804 | |
| | 805 | /* |
| | 806 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| | 807 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB |
| | 808 | */ |
| | 809 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 |
| | 810 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 |
| | 811 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
| | 812 | |
| | 813 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| | 814 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 |
| | 815 | #define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 |
| | 816 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) |
| | 817 | |
| | 818 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| | 819 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 |
| | 820 | #define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 |
| | 821 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) |
| | 822 | |
| | 823 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| | 824 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 |
| | 825 | #define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 |
| | 826 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) |
| | 827 | |
| | 828 | /* |
| | 829 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| | 830 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| | 831 | * CM_CLKSEL_DPLL_UNIPRO |
| | 832 | */ |
| | 833 | #define OMAP4430_DPLL_DIV_SHIFT 0 |
| | 834 | #define OMAP4430_DPLL_DIV_WIDTH 0x7 |
| | 835 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
| | 836 | |
| | 837 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ |
| | 838 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 |
| | 839 | #define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 |
| | 840 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
| | 841 | |
| | 842 | /* |
| | 843 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 844 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| | 845 | */ |
| | 846 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 |
| | 847 | #define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 |
| | 848 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
| | 849 | |
| | 850 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ |
| | 851 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 |
| | 852 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 |
| | 853 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) |
| | 854 | |
| | 855 | /* |
| | 856 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 857 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 858 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| | 859 | */ |
| | 860 | #define OMAP4430_DPLL_EN_SHIFT 0 |
| | 861 | #define OMAP4430_DPLL_EN_WIDTH 0x3 |
| | 862 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
| | 863 | |
| | 864 | /* |
| | 865 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 866 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 867 | * CM_CLKMODE_DPLL_UNIPRO |
| | 868 | */ |
| | 869 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 |
| | 870 | #define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 |
| | 871 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
| | 872 | |
| | 873 | /* |
| | 874 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, |
| | 875 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, |
| | 876 | * CM_CLKSEL_DPLL_UNIPRO |
| | 877 | */ |
| | 878 | #define OMAP4430_DPLL_MULT_SHIFT 8 |
| | 879 | #define OMAP4430_DPLL_MULT_WIDTH 0xb |
| | 880 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
| | 881 | |
| | 882 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ |
| | 883 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 |
| | 884 | #define OMAP4430_DPLL_MULT_USB_WIDTH 0xc |
| | 885 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
| | 886 | |
| | 887 | /* |
| | 888 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 889 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 890 | * CM_CLKMODE_DPLL_UNIPRO |
| | 891 | */ |
| | 892 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 |
| | 893 | #define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 |
| | 894 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
| | 895 | |
| | 896 | /* Used by CM_CLKSEL_DPLL_USB */ |
| | 897 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 |
| | 898 | #define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 |
| | 899 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
| | 900 | |
| | 901 | /* |
| | 902 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 903 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 904 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| | 905 | */ |
| | 906 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 |
| | 907 | #define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 |
| | 908 | #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) |
| | 909 | |
| | 910 | /* |
| | 911 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 912 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 913 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| | 914 | */ |
| | 915 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 |
| | 916 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 |
| | 917 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) |
| | 918 | |
| | 919 | /* |
| | 920 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, |
| | 921 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, |
| | 922 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB |
| | 923 | */ |
| | 924 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 |
| | 925 | #define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 |
| | 926 | #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) |
| | 927 | |
| | 928 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| | 929 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 |
| | 930 | #define OMAP4430_DSS_DYNDEP_WIDTH 0x1 |
| | 931 | #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) |
| | 932 | |
| | 933 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
| | 934 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
| | 935 | #define OMAP4430_DSS_STATDEP_WIDTH 0x1 |
| | 936 | #define OMAP4430_DSS_STATDEP_MASK (1 << 8) |
| | 937 | |
| | 938 | /* Used by CM_L3_2_DYNAMICDEP */ |
| | 939 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 |
| | 940 | #define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 |
| | 941 | #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) |
| | 942 | |
| | 943 | /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ |
| | 944 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
| | 945 | #define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 |
| | 946 | #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) |
| | 947 | |
| | 948 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ |
| | 949 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 |
| | 950 | #define OMAP4430_FREQ_UPDATE_WIDTH 0x1 |
| | 951 | #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) |
| | 952 | |
| | 953 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 954 | #define OMAP4430_FUNC_SHIFT 16 |
| | 955 | #define OMAP4430_FUNC_WIDTH 0xc |
| | 956 | #define OMAP4430_FUNC_MASK (0xfff << 16) |
| | 957 | |
| | 958 | /* Used by CM_L3_2_DYNAMICDEP */ |
| | 959 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 |
| | 960 | #define OMAP4430_GFX_DYNDEP_WIDTH 0x1 |
| | 961 | #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) |
| | 962 | |
| | 963 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| | 964 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
| | 965 | #define OMAP4430_GFX_STATDEP_WIDTH 0x1 |
| | 966 | #define OMAP4430_GFX_STATDEP_MASK (1 << 10) |
| | 967 | |
| | 968 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ |
| | 969 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 |
| | 970 | #define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 |
| | 971 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) |
| | 972 | |
| | 973 | /* |
| | 974 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| | 975 | * CM_DIV_M4_DPLL_PER |
| | 976 | */ |
| | 977 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
| | 978 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 |
| | 979 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
| | 980 | |
| | 981 | /* |
| | 982 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| | 983 | * CM_DIV_M4_DPLL_PER |
| | 984 | */ |
| | 985 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 |
| | 986 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 |
| | 987 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) |
| | 988 | |
| | 989 | /* |
| | 990 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| | 991 | * CM_DIV_M4_DPLL_PER |
| | 992 | */ |
| | 993 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 |
| | 994 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 |
| | 995 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) |
| | 996 | |
| | 997 | /* |
| | 998 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| | 999 | * CM_DIV_M4_DPLL_PER |
| | 1000 | */ |
| | 1001 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 |
| | 1002 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 |
| | 1003 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) |
| | 1004 | |
| | 1005 | /* |
| | 1006 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| | 1007 | * CM_DIV_M5_DPLL_PER |
| | 1008 | */ |
| | 1009 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
| | 1010 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 |
| | 1011 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
| | 1012 | |
| | 1013 | /* |
| | 1014 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| | 1015 | * CM_DIV_M5_DPLL_PER |
| | 1016 | */ |
| | 1017 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 |
| | 1018 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 |
| | 1019 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) |
| | 1020 | |
| | 1021 | /* |
| | 1022 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| | 1023 | * CM_DIV_M5_DPLL_PER |
| | 1024 | */ |
| | 1025 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 |
| | 1026 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 |
| | 1027 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) |
| | 1028 | |
| | 1029 | /* |
| | 1030 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| | 1031 | * CM_DIV_M5_DPLL_PER |
| | 1032 | */ |
| | 1033 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 |
| | 1034 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 |
| | 1035 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) |
| | 1036 | |
| | 1037 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| | 1038 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
| | 1039 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 |
| | 1040 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
| | 1041 | |
| | 1042 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| | 1043 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 |
| | 1044 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 |
| | 1045 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) |
| | 1046 | |
| | 1047 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| | 1048 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 |
| | 1049 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 |
| | 1050 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) |
| | 1051 | |
| | 1052 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| | 1053 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 |
| | 1054 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 |
| | 1055 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) |
| | 1056 | |
| | 1057 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| | 1058 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 |
| | 1059 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 |
| | 1060 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
| | 1061 | |
| | 1062 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| | 1063 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 |
| | 1064 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 |
| | 1065 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) |
| | 1066 | |
| | 1067 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| | 1068 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 |
| | 1069 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 |
| | 1070 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) |
| | 1071 | |
| | 1072 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| | 1073 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 |
| | 1074 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 |
| | 1075 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) |
| | 1076 | |
| | 1077 | /* |
| | 1078 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, |
| | 1079 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| | 1080 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, |
| | 1081 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, |
| | 1082 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, |
| | 1083 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, |
| | 1084 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, |
| | 1085 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, |
| | 1086 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
| | 1087 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
| | 1088 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
| | 1089 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| | 1090 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| | 1091 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, |
| | 1092 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, |
| | 1093 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, |
| | 1094 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, |
| | 1095 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, |
| | 1096 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
| | 1097 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, |
| | 1098 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, |
| | 1099 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
| | 1100 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, |
| | 1101 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, |
| | 1102 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, |
| | 1103 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, |
| | 1104 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, |
| | 1105 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, |
| | 1106 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, |
| | 1107 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, |
| | 1108 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, |
| | 1109 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
| | 1110 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, |
| | 1111 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
| | 1112 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
| | 1113 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, |
| | 1114 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, |
| | 1115 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL |
| | 1116 | */ |
| | 1117 | #define OMAP4430_IDLEST_SHIFT 16 |
| | 1118 | #define OMAP4430_IDLEST_WIDTH 0x2 |
| | 1119 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
| | 1120 | |
| | 1121 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ |
| | 1122 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 |
| | 1123 | #define OMAP4430_ISS_DYNDEP_WIDTH 0x1 |
| | 1124 | #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) |
| | 1125 | |
| | 1126 | /* |
| | 1127 | * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, |
| | 1128 | * CM_TESLA_STATICDEP |
| | 1129 | */ |
| | 1130 | #define OMAP4430_ISS_STATDEP_SHIFT 9 |
| | 1131 | #define OMAP4430_ISS_STATDEP_WIDTH 0x1 |
| | 1132 | #define OMAP4430_ISS_STATDEP_MASK (1 << 9) |
| | 1133 | |
| | 1134 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ |
| | 1135 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 |
| | 1136 | #define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 |
| | 1137 | #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) |
| | 1138 | |
| | 1139 | /* |
| | 1140 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| | 1141 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, |
| | 1142 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1143 | */ |
| | 1144 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
| | 1145 | #define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 |
| | 1146 | #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) |
| | 1147 | |
| | 1148 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| | 1149 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 |
| | 1150 | #define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 |
| | 1151 | #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) |
| | 1152 | |
| | 1153 | /* |
| | 1154 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, |
| | 1155 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1156 | */ |
| | 1157 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
| | 1158 | #define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 |
| | 1159 | #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) |
| | 1160 | |
| | 1161 | /* |
| | 1162 | * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, |
| | 1163 | * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| | 1164 | */ |
| | 1165 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 |
| | 1166 | #define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 |
| | 1167 | #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) |
| | 1168 | |
| | 1169 | /* |
| | 1170 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| | 1171 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| | 1172 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| | 1173 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1174 | */ |
| | 1175 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
| | 1176 | #define OMAP4430_L3_1_STATDEP_WIDTH 0x1 |
| | 1177 | #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) |
| | 1178 | |
| | 1179 | /* |
| | 1180 | * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, |
| | 1181 | * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, |
| | 1182 | * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| | 1183 | * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP |
| | 1184 | */ |
| | 1185 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 |
| | 1186 | #define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 |
| | 1187 | #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) |
| | 1188 | |
| | 1189 | /* |
| | 1190 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| | 1191 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| | 1192 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| | 1193 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1194 | */ |
| | 1195 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
| | 1196 | #define OMAP4430_L3_2_STATDEP_WIDTH 0x1 |
| | 1197 | #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) |
| | 1198 | |
| | 1199 | /* Used by CM_L3_1_DYNAMICDEP */ |
| | 1200 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 |
| | 1201 | #define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 |
| | 1202 | #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) |
| | 1203 | |
| | 1204 | /* |
| | 1205 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| | 1206 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1207 | */ |
| | 1208 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
| | 1209 | #define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 |
| | 1210 | #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) |
| | 1211 | |
| | 1212 | /* Used by CM_L3_2_DYNAMICDEP */ |
| | 1213 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 |
| | 1214 | #define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 |
| | 1215 | #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) |
| | 1216 | |
| | 1217 | /* |
| | 1218 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, |
| | 1219 | * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1220 | */ |
| | 1221 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
| | 1222 | #define OMAP4430_L4PER_STATDEP_WIDTH 0x1 |
| | 1223 | #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) |
| | 1224 | |
| | 1225 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ |
| | 1226 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 |
| | 1227 | #define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 |
| | 1228 | #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) |
| | 1229 | |
| | 1230 | /* |
| | 1231 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
| | 1232 | * CM_SDMA_STATICDEP |
| | 1233 | */ |
| | 1234 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
| | 1235 | #define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 |
| | 1236 | #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) |
| | 1237 | |
| | 1238 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 1239 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 |
| | 1240 | #define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 |
| | 1241 | #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) |
| | 1242 | |
| | 1243 | /* |
| | 1244 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, |
| | 1245 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1246 | */ |
| | 1247 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
| | 1248 | #define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 |
| | 1249 | #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) |
| | 1250 | |
| | 1251 | /* |
| | 1252 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| | 1253 | * CM_MPU_DYNAMICDEP |
| | 1254 | */ |
| | 1255 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 |
| | 1256 | #define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 |
| | 1257 | #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) |
| | 1258 | |
| | 1259 | /* |
| | 1260 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, |
| | 1261 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, |
| | 1262 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, |
| | 1263 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP |
| | 1264 | */ |
| | 1265 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
| | 1266 | #define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 |
| | 1267 | #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) |
| | 1268 | |
| | 1269 | /* |
| | 1270 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
| | 1271 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| | 1272 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, |
| | 1273 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB |
| | 1274 | */ |
| | 1275 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 |
| | 1276 | #define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 |
| | 1277 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) |
| | 1278 | |
| | 1279 | /* |
| | 1280 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, |
| | 1281 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, |
| | 1282 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, |
| | 1283 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB |
| | 1284 | */ |
| | 1285 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 |
| | 1286 | #define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 |
| | 1287 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) |
| | 1288 | |
| | 1289 | /* |
| | 1290 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, |
| | 1291 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, |
| | 1292 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, |
| | 1293 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, |
| | 1294 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, |
| | 1295 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, |
| | 1296 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, |
| | 1297 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, |
| | 1298 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
| | 1299 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
| | 1300 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, |
| | 1301 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| | 1302 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| | 1303 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, |
| | 1304 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, |
| | 1305 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, |
| | 1306 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, |
| | 1307 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, |
| | 1308 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, |
| | 1309 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, |
| | 1310 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, |
| | 1311 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, |
| | 1312 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, |
| | 1313 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, |
| | 1314 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, |
| | 1315 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, |
| | 1316 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, |
| | 1317 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, |
| | 1318 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, |
| | 1319 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, |
| | 1320 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, |
| | 1321 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, |
| | 1322 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, |
| | 1323 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, |
| | 1324 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, |
| | 1325 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, |
| | 1326 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, |
| | 1327 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL |
| | 1328 | */ |
| | 1329 | #define OMAP4430_MODULEMODE_SHIFT 0 |
| | 1330 | #define OMAP4430_MODULEMODE_WIDTH 0x2 |
| | 1331 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
| | 1332 | |
| | 1333 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 1334 | #define OMAP4460_MPU_DYNDEP_SHIFT 19 |
| | 1335 | #define OMAP4460_MPU_DYNDEP_WIDTH 0x1 |
| | 1336 | #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) |
| | 1337 | |
| | 1338 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| | 1339 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
| | 1340 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 |
| | 1341 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) |
| | 1342 | |
| | 1343 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
| | 1344 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
| | 1345 | #define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 |
| | 1346 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) |
| | 1347 | |
| | 1348 | /* Used by CM_ALWON_USBPHY_CLKCTRL */ |
| | 1349 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 |
| | 1350 | #define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 |
| | 1351 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) |
| | 1352 | |
| | 1353 | /* Used by CM_CAM_ISS_CLKCTRL */ |
| | 1354 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
| | 1355 | #define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 |
| | 1356 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) |
| | 1357 | |
| | 1358 | /* |
| | 1359 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, |
| | 1360 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, |
| | 1361 | * CM_WKUP_GPIO1_CLKCTRL |
| | 1362 | */ |
| | 1363 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
| | 1364 | #define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 |
| | 1365 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) |
| | 1366 | |
| | 1367 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ |
| | 1368 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 |
| | 1369 | #define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 |
| | 1370 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) |
| | 1371 | |
| | 1372 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| | 1373 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
| | 1374 | #define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 |
| | 1375 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) |
| | 1376 | |
| | 1377 | /* Used by CM_WKUP_USIM_CLKCTRL */ |
| | 1378 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 |
| | 1379 | #define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 |
| | 1380 | #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) |
| | 1381 | |
| | 1382 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| | 1383 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
| | 1384 | #define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 |
| | 1385 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) |
| | 1386 | |
| | 1387 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| | 1388 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
| | 1389 | #define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 |
| | 1390 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) |
| | 1391 | |
| | 1392 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| | 1393 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
| | 1394 | #define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 |
| | 1395 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) |
| | 1396 | |
| | 1397 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1398 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
| | 1399 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 |
| | 1400 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) |
| | 1401 | |
| | 1402 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1403 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
| | 1404 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 |
| | 1405 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) |
| | 1406 | |
| | 1407 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1408 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
| | 1409 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 |
| | 1410 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) |
| | 1411 | |
| | 1412 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1413 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
| | 1414 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 |
| | 1415 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) |
| | 1416 | |
| | 1417 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1418 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
| | 1419 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 |
| | 1420 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) |
| | 1421 | |
| | 1422 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| | 1423 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
| | 1424 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 |
| | 1425 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) |
| | 1426 | |
| | 1427 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| | 1428 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
| | 1429 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 |
| | 1430 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) |
| | 1431 | |
| | 1432 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ |
| | 1433 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
| | 1434 | #define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 |
| | 1435 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) |
| | 1436 | |
| | 1437 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ |
| | 1438 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
| | 1439 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 |
| | 1440 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) |
| | 1441 | |
| | 1442 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ |
| | 1443 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
| | 1444 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 |
| | 1445 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) |
| | 1446 | |
| | 1447 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| | 1448 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
| | 1449 | #define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 |
| | 1450 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) |
| | 1451 | |
| | 1452 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ |
| | 1453 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 |
| | 1454 | #define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 |
| | 1455 | #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) |
| | 1456 | |
| | 1457 | /* Used by CM_DSS_DSS_CLKCTRL */ |
| | 1458 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
| | 1459 | #define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 |
| | 1460 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) |
| | 1461 | |
| | 1462 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ |
| | 1463 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 |
| | 1464 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 |
| | 1465 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) |
| | 1466 | |
| | 1467 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| | 1468 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
| | 1469 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 |
| | 1470 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) |
| | 1471 | |
| | 1472 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| | 1473 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
| | 1474 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 |
| | 1475 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) |
| | 1476 | |
| | 1477 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ |
| | 1478 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
| | 1479 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 |
| | 1480 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) |
| | 1481 | |
| | 1482 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1483 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
| | 1484 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 |
| | 1485 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) |
| | 1486 | |
| | 1487 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1488 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
| | 1489 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 |
| | 1490 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) |
| | 1491 | |
| | 1492 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ |
| | 1493 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
| | 1494 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 |
| | 1495 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) |
| | 1496 | |
| | 1497 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ |
| | 1498 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
| | 1499 | #define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 |
| | 1500 | #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) |
| | 1501 | |
| | 1502 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ |
| | 1503 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 |
| | 1504 | #define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 |
| | 1505 | #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) |
| | 1506 | |
| | 1507 | /* Used by CM_CLKSEL_ABE */ |
| | 1508 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
| | 1509 | #define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 |
| | 1510 | #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) |
| | 1511 | |
| | 1512 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ |
| | 1513 | #define OMAP4430_PERF_CURRENT_SHIFT 0 |
| | 1514 | #define OMAP4430_PERF_CURRENT_WIDTH 0x8 |
| | 1515 | #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) |
| | 1516 | |
| | 1517 | /* |
| | 1518 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, |
| | 1519 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, |
| | 1520 | * CM_IVA_DVFS_PERF_TESLA |
| | 1521 | */ |
| | 1522 | #define OMAP4430_PERF_REQ_SHIFT 0 |
| | 1523 | #define OMAP4430_PERF_REQ_WIDTH 0x8 |
| | 1524 | #define OMAP4430_PERF_REQ_MASK (0xff << 0) |
| | 1525 | |
| | 1526 | /* Used by CM_RESTORE_ST */ |
| | 1527 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 |
| | 1528 | #define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 |
| | 1529 | #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) |
| | 1530 | |
| | 1531 | /* Used by CM_RESTORE_ST */ |
| | 1532 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 |
| | 1533 | #define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 |
| | 1534 | #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) |
| | 1535 | |
| | 1536 | /* Used by CM_RESTORE_ST */ |
| | 1537 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 |
| | 1538 | #define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 |
| | 1539 | #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) |
| | 1540 | |
| | 1541 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| | 1542 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
| | 1543 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 |
| | 1544 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) |
| | 1545 | |
| | 1546 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ |
| | 1547 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
| | 1548 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 |
| | 1549 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) |
| | 1550 | |
| | 1551 | /* Used by CM_DYN_DEP_PRESCAL */ |
| | 1552 | #define OMAP4430_PRESCAL_SHIFT 0 |
| | 1553 | #define OMAP4430_PRESCAL_WIDTH 0x6 |
| | 1554 | #define OMAP4430_PRESCAL_MASK (0x3f << 0) |
| | 1555 | |
| | 1556 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 1557 | #define OMAP4430_R_RTL_SHIFT 11 |
| | 1558 | #define OMAP4430_R_RTL_WIDTH 0x5 |
| | 1559 | #define OMAP4430_R_RTL_MASK (0x1f << 11) |
| | 1560 | |
| | 1561 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ |
| | 1562 | #define OMAP4430_SAR_MODE_SHIFT 4 |
| | 1563 | #define OMAP4430_SAR_MODE_WIDTH 0x1 |
| | 1564 | #define OMAP4430_SAR_MODE_MASK (1 << 4) |
| | 1565 | |
| | 1566 | /* Used by CM_SCALE_FCLK */ |
| | 1567 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
| | 1568 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 |
| | 1569 | #define OMAP4430_SCALE_FCLK_MASK (1 << 0) |
| | 1570 | |
| | 1571 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 1572 | #define OMAP4430_SCHEME_SHIFT 30 |
| | 1573 | #define OMAP4430_SCHEME_WIDTH 0x2 |
| | 1574 | #define OMAP4430_SCHEME_MASK (0x3 << 30) |
| | 1575 | |
| | 1576 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 1577 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 |
| | 1578 | #define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 |
| | 1579 | #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) |
| | 1580 | |
| | 1581 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| | 1582 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 |
| | 1583 | #define OMAP4430_SDMA_STATDEP_WIDTH 0x1 |
| | 1584 | #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) |
| | 1585 | |
| | 1586 | /* Used by CM_CLKSEL_ABE */ |
| | 1587 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
| | 1588 | #define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 |
| | 1589 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) |
| | 1590 | |
| | 1591 | /* |
| | 1592 | * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, |
| | 1593 | * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, |
| | 1594 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, |
| | 1595 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, |
| | 1596 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| | 1597 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, |
| | 1598 | * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL |
| | 1599 | */ |
| | 1600 | #define OMAP4430_STBYST_SHIFT 18 |
| | 1601 | #define OMAP4430_STBYST_WIDTH 0x1 |
| | 1602 | #define OMAP4430_STBYST_MASK (1 << 18) |
| | 1603 | |
| | 1604 | /* |
| | 1605 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
| | 1606 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, |
| | 1607 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB |
| | 1608 | */ |
| | 1609 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 |
| | 1610 | #define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 |
| | 1611 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
| | 1612 | |
| | 1613 | /* Used by CM_CLKDCOLDO_DPLL_USB */ |
| | 1614 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 |
| | 1615 | #define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 |
| | 1616 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) |
| | 1617 | |
| | 1618 | /* |
| | 1619 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, |
| | 1620 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB |
| | 1621 | */ |
| | 1622 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 |
| | 1623 | #define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 |
| | 1624 | #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) |
| | 1625 | |
| | 1626 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ |
| | 1627 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 |
| | 1628 | #define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 |
| | 1629 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) |
| | 1630 | |
| | 1631 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ |
| | 1632 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 |
| | 1633 | #define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 |
| | 1634 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) |
| | 1635 | |
| | 1636 | /* |
| | 1637 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, |
| | 1638 | * CM_DIV_M4_DPLL_PER |
| | 1639 | */ |
| | 1640 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 |
| | 1641 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 |
| | 1642 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) |
| | 1643 | |
| | 1644 | /* |
| | 1645 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, |
| | 1646 | * CM_DIV_M5_DPLL_PER |
| | 1647 | */ |
| | 1648 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 |
| | 1649 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 |
| | 1650 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) |
| | 1651 | |
| | 1652 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ |
| | 1653 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 |
| | 1654 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 |
| | 1655 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) |
| | 1656 | |
| | 1657 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ |
| | 1658 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 |
| | 1659 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 |
| | 1660 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) |
| | 1661 | |
| | 1662 | /* |
| | 1663 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, |
| | 1664 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, |
| | 1665 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB |
| | 1666 | */ |
| | 1667 | #define OMAP4430_ST_MN_BYPASS_SHIFT 8 |
| | 1668 | #define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 |
| | 1669 | #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) |
| | 1670 | |
| | 1671 | /* Used by CM_SYS_CLKSEL */ |
| | 1672 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
| | 1673 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 |
| | 1674 | #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) |
| | 1675 | |
| | 1676 | /* Used by CM_L4CFG_DYNAMICDEP */ |
| | 1677 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 |
| | 1678 | #define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 |
| | 1679 | #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) |
| | 1680 | |
| | 1681 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ |
| | 1682 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
| | 1683 | #define OMAP4430_TESLA_STATDEP_WIDTH 0x1 |
| | 1684 | #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) |
| | 1685 | |
| | 1686 | /* |
| | 1687 | * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, |
| | 1688 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, |
| | 1689 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP |
| | 1690 | */ |
| | 1691 | #define OMAP4430_WINDOWSIZE_SHIFT 24 |
| | 1692 | #define OMAP4430_WINDOWSIZE_WIDTH 0x4 |
| | 1693 | #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) |
| | 1694 | |
| | 1695 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 1696 | #define OMAP4430_X_MAJOR_SHIFT 8 |
| | 1697 | #define OMAP4430_X_MAJOR_WIDTH 0x3 |
| | 1698 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) |
| | 1699 | |
| | 1700 | /* Used by REVISION_CM1, REVISION_CM2 */ |
| | 1701 | #define OMAP4430_Y_MINOR_SHIFT 0 |
| | 1702 | #define OMAP4430_Y_MINOR_WIDTH 0x6 |
| | 1703 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) |
| | 1704 | #endif |
projects / deliverable / linux.git / blame_incremental