[deliverable/linux.git] / arch / arm / mach-omap2 / io.c

/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
 *
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <asm/tlb.h>
#include <asm/mach/map.h>

#include <linux/omap-dma.h>

#include "omap_hwmod.h"
#include "soc.h"
#include "iomap.h"
#include "voltage.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "common.h"
#include "clock.h"
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "clock44xx.h"
#include "omap-pm.h"
#include "sdrc.h"
#include "control.h"
#include "serial.h"
#include "sram.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "prm.h"
#include "cm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
#include "cminst44xx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"

/*
 * omap_clk_init: points to a function that does the SoC-specific
 * clock initializations
 */
int (*omap_clk_init)(void);

/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */

#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#ifdef CONFIG_SOC_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
	{
		.virtual	= DSP_MEM_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_2420_PHYS),
		.length		= DSP_MEM_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_IPI_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_2420_PHYS),
		.length		= DSP_IPI_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_MMU_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_2420_PHYS),
		.length		= DSP_MMU_2420_SIZE,
		.type		= MT_DEVICE
	},
};

#endif

#ifdef CONFIG_SOC_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#endif

#ifdef	CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
	{
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
#if defined(CONFIG_DEBUG_LL) &&							\
	(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
	{
		.virtual	= ZOOM_UART_VIRT,
		.pfn		= __phys_to_pfn(ZOOM_UART_BASE),
		.length		= SZ_1M,
		.type		= MT_DEVICE
	},
#endif
};
#endif

#ifdef CONFIG_SOC_TI81XX
static struct map_desc omapti81xx_io_desc[] __initdata = {
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	}
};
#endif

#ifdef CONFIG_SOC_AM33XX
static struct map_desc omapam33xx_io_desc[] __initdata = {
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_WK_AM33XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
		.length		= L4_WK_AM33XX_SIZE,
		.type		= MT_DEVICE
	}
};
#endif

#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
#ifdef CONFIG_OMAP4_ERRATA_I688
	{
		.virtual	= OMAP4_SRAM_VA,
		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
		.length		= PAGE_SIZE,
		.type		= MT_MEMORY_SO,
	},
#endif

};
#endif

#ifdef	CONFIG_SOC_OMAP5
static struct map_desc omap54xx_io_desc[] __initdata = {
	{
		.virtual	= L3_54XX_VIRT,
		.pfn		= __phys_to_pfn(L3_54XX_PHYS),
		.length		= L3_54XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_54XX_VIRT,
		.pfn		= __phys_to_pfn(L4_54XX_PHYS),
		.length		= L4_54XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_WK_54XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_54XX_PHYS),
		.length		= L4_WK_54XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_54XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_54XX_PHYS),
		.length		= L4_PER_54XX_SIZE,
		.type		= MT_DEVICE,
	},
};
#endif

#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_io(void)
{
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
}
#endif

#ifdef CONFIG_SOC_OMAP2430
void __init omap243x_map_io(void)
{
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
}
#endif

#ifdef CONFIG_ARCH_OMAP3
void __init omap3_map_io(void)
{
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
}
#endif

#ifdef CONFIG_SOC_TI81XX
void __init ti81xx_map_io(void)
{
	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
}
#endif

#ifdef CONFIG_SOC_AM33XX
void __init am33xx_map_io(void)
{
	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void __init omap4_map_io(void)
{
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	omap_barriers_init();
}
#endif

#ifdef CONFIG_SOC_OMAP5
void __init omap5_map_io(void)
{
	iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
}
#endif
/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (IS_ERR(dpll3_m2_ck))
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}

static void __init omap_hwmod_init_postsetup(void)
{
	u8 postsetup_state;

	/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM_RUNTIME
	postsetup_state = _HWMOD_STATE_IDLE;
#else
	postsetup_state = _HWMOD_STATE_ENABLED;
#endif
	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);

	omap_pm_if_early_init();
}

#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
	omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
			       OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
				  NULL);
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
	omap2xxx_check_revision();
	omap2xxx_prm_init();
	omap2xxx_cm_init();
	omap2xxx_voltagedomains_init();
	omap242x_powerdomains_init();
	omap242x_clockdomains_init();
	omap2420_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = omap2420_clk_init;
}

void __init omap2420_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap2_pm_init();
	omap2_clk_enable_autoidle_all();
}
#endif

#ifdef CONFIG_SOC_OMAP2430
void __init omap2430_init_early(void)
{
	omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
			       OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
				  NULL);
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
	omap2xxx_check_revision();
	omap2xxx_prm_init();
	omap2xxx_cm_init();
	omap2xxx_voltagedomains_init();
	omap243x_powerdomains_init();
	omap243x_clockdomains_init();
	omap2430_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = omap2430_clk_init;
}

void __init omap2430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap2_pm_init();
	omap2_clk_enable_autoidle_all();
}
#endif

/*
 * Currently only board-omap3beagle.c should call this because of the
 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 */
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
{
	omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
			       OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
				  NULL);
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
	omap3xxx_check_revision();
	omap3xxx_check_features();
	omap3xxx_prm_init();
	omap3xxx_cm_init();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = omap3xxx_clk_init;
}

void __init omap3430_init_early(void)
{
	omap3_init_early();
}

void __init omap35xx_init_early(void)
{
	omap3_init_early();
}

void __init omap3630_init_early(void)
{
	omap3_init_early();
}

void __init am35xx_init_early(void)
{
	omap3_init_early();
}

void __init ti81xx_init_early(void)
{
	omap2_set_globals_tap(OMAP343X_CLASS,
			      OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
				  NULL);
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
	omap3xxx_check_revision();
	ti81xx_check_features();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = omap3xxx_clk_init;
}

void __init omap3_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}

void __init omap3430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}

void __init omap35xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}

void __init omap3630_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}

void __init am35xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}

void __init ti81xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
	omap2_clk_enable_autoidle_all();
}
#endif

#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
	omap2_set_globals_tap(AM335X_CLASS,
			      AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
	omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
				  NULL);
	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
	omap3xxx_check_revision();
	ti81xx_check_features();
	am33xx_voltagedomains_init();
	am33xx_powerdomains_init();
	am33xx_clockdomains_init();
	am33xx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = am33xx_clk_init;
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
	omap2_set_globals_tap(OMAP443X_CLASS,
			      OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
				  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
			     OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
	omap_prm_base_init();
	omap_cm_base_init();
	omap4xxx_check_revision();
	omap4xxx_check_features();
	omap44xx_prm_init();
	omap44xx_voltagedomains_init();
	omap44xx_powerdomains_init();
	omap44xx_clockdomains_init();
	omap44xx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap_clk_init = omap4xxx_clk_init;
}

void __init omap4430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap4_pm_init();
	omap2_clk_enable_autoidle_all();
}
#endif

#ifdef CONFIG_SOC_OMAP5
void __init omap5_init_early(void)
{
	omap2_set_globals_tap(OMAP54XX_CLASS,
			      OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
				  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
			     OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
	omap_prm_base_init();
	omap_cm_base_init();
	omap5xxx_check_revision();
}
#endif

void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
				      struct omap_sdrc_params *sdrc_cs1)
{
	omap_sram_init();

	if (cpu_is_omap24xx() || omap3_has_sdrc()) {
		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
		_omap2_init_reprogram_sdrc();
	}
}
Commit	Line	Data
	1	/*
	2	* linux/arch/arm/mach-omap2/io.c
	3	*
	4	* OMAP2 I/O mapping code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Copyright (C) 2007-2009 Texas Instruments
	8	*
	9	* Author:
	10	* Juha Yrjola <juha.yrjola@nokia.com>
	11	* Syed Khasim <x0khasim@ti.com>
	12	*
	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24
	25	#include <asm/tlb.h>
	26	#include <asm/mach/map.h>
	27
	28	#include <linux/omap-dma.h>
	29
	30	#include "omap_hwmod.h"
	31	#include "soc.h"
	32	#include "iomap.h"
	33	#include "voltage.h"
	34	#include "powerdomain.h"
	35	#include "clockdomain.h"
	36	#include "common.h"
	37	#include "clock.h"
	38	#include "clock2xxx.h"
	39	#include "clock3xxx.h"
	40	#include "clock44xx.h"
	41	#include "omap-pm.h"
	42	#include "sdrc.h"
	43	#include "control.h"
	44	#include "serial.h"
	45	#include "sram.h"
	46	#include "cm2xxx.h"
	47	#include "cm3xxx.h"
	48	#include "prm.h"
	49	#include "cm.h"
	50	#include "prcm_mpu44xx.h"
	51	#include "prminst44xx.h"
	52	#include "cminst44xx.h"
	53	#include "prm2xxx.h"
	54	#include "prm3xxx.h"
	55	#include "prm44xx.h"
	56
	57	/*
	58	* omap_clk_init: points to a function that does the SoC-specific
	59	* clock initializations
	60	*/
	61	int (*omap_clk_init)(void);
	62
	63	/*
	64	* The machine specific code may provide the extra mapping besides the
	65	* default mapping provided here.
	66	*/
	67
	68	#if defined(CONFIG_SOC_OMAP2420) \|\| defined(CONFIG_SOC_OMAP2430)
	69	static struct map_desc omap24xx_io_desc[] __initdata = {
	70	{
	71	.virtual = L3_24XX_VIRT,
	72	.pfn = __phys_to_pfn(L3_24XX_PHYS),
	73	.length = L3_24XX_SIZE,
	74	.type = MT_DEVICE
	75	},
	76	{
	77	.virtual = L4_24XX_VIRT,
	78	.pfn = __phys_to_pfn(L4_24XX_PHYS),
	79	.length = L4_24XX_SIZE,
	80	.type = MT_DEVICE
	81	},
	82	};
	83
	84	#ifdef CONFIG_SOC_OMAP2420
	85	static struct map_desc omap242x_io_desc[] __initdata = {
	86	{
	87	.virtual = DSP_MEM_2420_VIRT,
	88	.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
	89	.length = DSP_MEM_2420_SIZE,
	90	.type = MT_DEVICE
	91	},
	92	{
	93	.virtual = DSP_IPI_2420_VIRT,
	94	.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
	95	.length = DSP_IPI_2420_SIZE,
	96	.type = MT_DEVICE
	97	},
	98	{
	99	.virtual = DSP_MMU_2420_VIRT,
	100	.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
	101	.length = DSP_MMU_2420_SIZE,
	102	.type = MT_DEVICE
	103	},
	104	};
	105
	106	#endif
	107
	108	#ifdef CONFIG_SOC_OMAP2430
	109	static struct map_desc omap243x_io_desc[] __initdata = {
	110	{
	111	.virtual = L4_WK_243X_VIRT,
	112	.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
	113	.length = L4_WK_243X_SIZE,
	114	.type = MT_DEVICE
	115	},
	116	{
	117	.virtual = OMAP243X_GPMC_VIRT,
	118	.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
	119	.length = OMAP243X_GPMC_SIZE,
	120	.type = MT_DEVICE
	121	},
	122	{
	123	.virtual = OMAP243X_SDRC_VIRT,
	124	.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
	125	.length = OMAP243X_SDRC_SIZE,
	126	.type = MT_DEVICE
	127	},
	128	{
	129	.virtual = OMAP243X_SMS_VIRT,
	130	.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
	131	.length = OMAP243X_SMS_SIZE,
	132	.type = MT_DEVICE
	133	},
	134	};
	135	#endif
	136	#endif
	137
	138	#ifdef CONFIG_ARCH_OMAP3
	139	static struct map_desc omap34xx_io_desc[] __initdata = {
	140	{
	141	.virtual = L3_34XX_VIRT,
	142	.pfn = __phys_to_pfn(L3_34XX_PHYS),
	143	.length = L3_34XX_SIZE,
	144	.type = MT_DEVICE
	145	},
	146	{
	147	.virtual = L4_34XX_VIRT,
	148	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	149	.length = L4_34XX_SIZE,
	150	.type = MT_DEVICE
	151	},
	152	{
	153	.virtual = OMAP34XX_GPMC_VIRT,
	154	.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
	155	.length = OMAP34XX_GPMC_SIZE,
	156	.type = MT_DEVICE
	157	},
	158	{
	159	.virtual = OMAP343X_SMS_VIRT,
	160	.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
	161	.length = OMAP343X_SMS_SIZE,
	162	.type = MT_DEVICE
	163	},
	164	{
	165	.virtual = OMAP343X_SDRC_VIRT,
	166	.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
	167	.length = OMAP343X_SDRC_SIZE,
	168	.type = MT_DEVICE
	169	},
	170	{
	171	.virtual = L4_PER_34XX_VIRT,
	172	.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
	173	.length = L4_PER_34XX_SIZE,
	174	.type = MT_DEVICE
	175	},
	176	{
	177	.virtual = L4_EMU_34XX_VIRT,
	178	.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
	179	.length = L4_EMU_34XX_SIZE,
	180	.type = MT_DEVICE
	181	},
	182	#if defined(CONFIG_DEBUG_LL) && \
	183	(defined(CONFIG_MACH_OMAP_ZOOM2) \|\| defined(CONFIG_MACH_OMAP_ZOOM3))
	184	{
	185	.virtual = ZOOM_UART_VIRT,
	186	.pfn = __phys_to_pfn(ZOOM_UART_BASE),
	187	.length = SZ_1M,
	188	.type = MT_DEVICE
	189	},
	190	#endif
	191	};
	192	#endif
	193
	194	#ifdef CONFIG_SOC_TI81XX
	195	static struct map_desc omapti81xx_io_desc[] __initdata = {
	196	{
	197	.virtual = L4_34XX_VIRT,
	198	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	199	.length = L4_34XX_SIZE,
	200	.type = MT_DEVICE
	201	}
	202	};
	203	#endif
	204
	205	#ifdef CONFIG_SOC_AM33XX
	206	static struct map_desc omapam33xx_io_desc[] __initdata = {
	207	{
	208	.virtual = L4_34XX_VIRT,
	209	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	210	.length = L4_34XX_SIZE,
	211	.type = MT_DEVICE
	212	},
	213	{
	214	.virtual = L4_WK_AM33XX_VIRT,
	215	.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
	216	.length = L4_WK_AM33XX_SIZE,
	217	.type = MT_DEVICE
	218	}
	219	};
	220	#endif
	221
	222	#ifdef CONFIG_ARCH_OMAP4
	223	static struct map_desc omap44xx_io_desc[] __initdata = {
	224	{
	225	.virtual = L3_44XX_VIRT,
	226	.pfn = __phys_to_pfn(L3_44XX_PHYS),
	227	.length = L3_44XX_SIZE,
	228	.type = MT_DEVICE,
	229	},
	230	{
	231	.virtual = L4_44XX_VIRT,
	232	.pfn = __phys_to_pfn(L4_44XX_PHYS),
	233	.length = L4_44XX_SIZE,
	234	.type = MT_DEVICE,
	235	},
	236	{
	237	.virtual = L4_PER_44XX_VIRT,
	238	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
	239	.length = L4_PER_44XX_SIZE,
	240	.type = MT_DEVICE,
	241	},
	242	#ifdef CONFIG_OMAP4_ERRATA_I688
	243	{
	244	.virtual = OMAP4_SRAM_VA,
	245	.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
	246	.length = PAGE_SIZE,
	247	.type = MT_MEMORY_SO,
	248	},
	249	#endif
	250
	251	};
	252	#endif
	253
	254	#ifdef CONFIG_SOC_OMAP5
	255	static struct map_desc omap54xx_io_desc[] __initdata = {
	256	{
	257	.virtual = L3_54XX_VIRT,
	258	.pfn = __phys_to_pfn(L3_54XX_PHYS),
	259	.length = L3_54XX_SIZE,
	260	.type = MT_DEVICE,
	261	},
	262	{
	263	.virtual = L4_54XX_VIRT,
	264	.pfn = __phys_to_pfn(L4_54XX_PHYS),
	265	.length = L4_54XX_SIZE,
	266	.type = MT_DEVICE,
	267	},
	268	{
	269	.virtual = L4_WK_54XX_VIRT,
	270	.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
	271	.length = L4_WK_54XX_SIZE,
	272	.type = MT_DEVICE,
	273	},
	274	{
	275	.virtual = L4_PER_54XX_VIRT,
	276	.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
	277	.length = L4_PER_54XX_SIZE,
	278	.type = MT_DEVICE,
	279	},
	280	};
	281	#endif
	282
	283	#ifdef CONFIG_SOC_OMAP2420
	284	void __init omap242x_map_io(void)
	285	{
	286	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	287	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
	288	}
	289	#endif
	290
	291	#ifdef CONFIG_SOC_OMAP2430
	292	void __init omap243x_map_io(void)
	293	{
	294	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	295	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
	296	}
	297	#endif
	298
	299	#ifdef CONFIG_ARCH_OMAP3
	300	void __init omap3_map_io(void)
	301	{
	302	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
	303	}
	304	#endif
	305
	306	#ifdef CONFIG_SOC_TI81XX
	307	void __init ti81xx_map_io(void)
	308	{
	309	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
	310	}
	311	#endif
	312
	313	#ifdef CONFIG_SOC_AM33XX
	314	void __init am33xx_map_io(void)
	315	{
	316	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
	317	}
	318	#endif
	319
	320	#ifdef CONFIG_ARCH_OMAP4
	321	void __init omap4_map_io(void)
	322	{
	323	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	324	omap_barriers_init();
	325	}
	326	#endif
	327
	328	#ifdef CONFIG_SOC_OMAP5
	329	void __init omap5_map_io(void)
	330	{
	331	iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
	332	}
	333	#endif
	334	/*
	335	* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
	336	*
	337	* Sets the CORE DPLL3 M2 divider to the same value that it's at
	338	* currently. This has the effect of setting the SDRC SDRAM AC timing
	339	* registers to the values currently defined by the kernel. Currently
	340	* only defined for OMAP3; will return 0 if called on OMAP2. Returns
	341	* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
	342	* or passes along the return value of clk_set_rate().
	343	*/
	344	static int __init _omap2_init_reprogram_sdrc(void)
	345	{
	346	struct clk *dpll3_m2_ck;
	347	int v = -EINVAL;
	348	long rate;
	349
	350	if (!cpu_is_omap34xx())
	351	return 0;
	352
	353	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	354	if (IS_ERR(dpll3_m2_ck))
	355	return -EINVAL;
	356
	357	rate = clk_get_rate(dpll3_m2_ck);
	358	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	359	v = clk_set_rate(dpll3_m2_ck, rate);
	360	if (v)
	361	pr_err("dpll3_m2_clk rate change failed: %d\n", v);
	362
	363	clk_put(dpll3_m2_ck);
	364
	365	return v;
	366	}
	367
	368	static int _set_hwmod_postsetup_state(struct omap_hwmod oh, void data)
	369	{
	370	return omap_hwmod_set_postsetup_state(oh, (u8 )data);
	371	}
	372
	373	static void __init omap_hwmod_init_postsetup(void)
	374	{
	375	u8 postsetup_state;
	376
	377	/* Set the default postsetup state for all hwmods */
	378	#ifdef CONFIG_PM_RUNTIME
	379	postsetup_state = _HWMOD_STATE_IDLE;
	380	#else
	381	postsetup_state = _HWMOD_STATE_ENABLED;
	382	#endif
	383	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
	384
	385	omap_pm_if_early_init();
	386	}
	387
	388	#ifdef CONFIG_SOC_OMAP2420
	389	void __init omap2420_init_early(void)
	390	{
	391	omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
	392	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
	393	OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
	394	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
	395	NULL);
	396	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
	397	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
	398	omap2xxx_check_revision();
	399	omap2xxx_prm_init();
	400	omap2xxx_cm_init();
	401	omap2xxx_voltagedomains_init();
	402	omap242x_powerdomains_init();
	403	omap242x_clockdomains_init();
	404	omap2420_hwmod_init();
	405	omap_hwmod_init_postsetup();
	406	omap_clk_init = omap2420_clk_init;
	407	}
	408
	409	void __init omap2420_init_late(void)
	410	{
	411	omap_mux_late_init();
	412	omap2_common_pm_late_init();
	413	omap2_pm_init();
	414	omap2_clk_enable_autoidle_all();
	415	}
	416	#endif
	417
	418	#ifdef CONFIG_SOC_OMAP2430
	419	void __init omap2430_init_early(void)
	420	{
	421	omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
	422	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
	423	OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
	424	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
	425	NULL);
	426	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
	427	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
	428	omap2xxx_check_revision();
	429	omap2xxx_prm_init();
	430	omap2xxx_cm_init();
	431	omap2xxx_voltagedomains_init();
	432	omap243x_powerdomains_init();
	433	omap243x_clockdomains_init();
	434	omap2430_hwmod_init();
	435	omap_hwmod_init_postsetup();
	436	omap_clk_init = omap2430_clk_init;
	437	}
	438
	439	void __init omap2430_init_late(void)
	440	{
	441	omap_mux_late_init();
	442	omap2_common_pm_late_init();
	443	omap2_pm_init();
	444	omap2_clk_enable_autoidle_all();
	445	}
	446	#endif
	447
	448	/*
	449	* Currently only board-omap3beagle.c should call this because of the
	450	* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
	451	*/
	452	#ifdef CONFIG_ARCH_OMAP3
	453	void __init omap3_init_early(void)
	454	{
	455	omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
	456	omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
	457	OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
	458	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
	459	NULL);
	460	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
	461	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
	462	omap3xxx_check_revision();
	463	omap3xxx_check_features();
	464	omap3xxx_prm_init();
	465	omap3xxx_cm_init();
	466	omap3xxx_voltagedomains_init();
	467	omap3xxx_powerdomains_init();
	468	omap3xxx_clockdomains_init();
	469	omap3xxx_hwmod_init();
	470	omap_hwmod_init_postsetup();
	471	omap_clk_init = omap3xxx_clk_init;
	472	}
	473
	474	void __init omap3430_init_early(void)
	475	{
	476	omap3_init_early();
	477	}
	478
	479	void __init omap35xx_init_early(void)
	480	{
	481	omap3_init_early();
	482	}
	483
	484	void __init omap3630_init_early(void)
	485	{
	486	omap3_init_early();
	487	}
	488
	489	void __init am35xx_init_early(void)
	490	{
	491	omap3_init_early();
	492	}
	493
	494	void __init ti81xx_init_early(void)
	495	{
	496	omap2_set_globals_tap(OMAP343X_CLASS,
	497	OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
	498	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
	499	NULL);
	500	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
	501	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
	502	omap3xxx_check_revision();
	503	ti81xx_check_features();
	504	omap3xxx_voltagedomains_init();
	505	omap3xxx_powerdomains_init();
	506	omap3xxx_clockdomains_init();
	507	omap3xxx_hwmod_init();
	508	omap_hwmod_init_postsetup();
	509	omap_clk_init = omap3xxx_clk_init;
	510	}
	511
	512	void __init omap3_init_late(void)
	513	{
	514	omap_mux_late_init();
	515	omap2_common_pm_late_init();
	516	omap3_pm_init();
	517	omap2_clk_enable_autoidle_all();
	518	}
	519
	520	void __init omap3430_init_late(void)
	521	{
	522	omap_mux_late_init();
	523	omap2_common_pm_late_init();
	524	omap3_pm_init();
	525	omap2_clk_enable_autoidle_all();
	526	}
	527
	528	void __init omap35xx_init_late(void)
	529	{
	530	omap_mux_late_init();
	531	omap2_common_pm_late_init();
	532	omap3_pm_init();
	533	omap2_clk_enable_autoidle_all();
	534	}
	535
	536	void __init omap3630_init_late(void)
	537	{
	538	omap_mux_late_init();
	539	omap2_common_pm_late_init();
	540	omap3_pm_init();
	541	omap2_clk_enable_autoidle_all();
	542	}
	543
	544	void __init am35xx_init_late(void)
	545	{
	546	omap_mux_late_init();
	547	omap2_common_pm_late_init();
	548	omap3_pm_init();
	549	omap2_clk_enable_autoidle_all();
	550	}
	551
	552	void __init ti81xx_init_late(void)
	553	{
	554	omap_mux_late_init();
	555	omap2_common_pm_late_init();
	556	omap3_pm_init();
	557	omap2_clk_enable_autoidle_all();
	558	}
	559	#endif
	560
	561	#ifdef CONFIG_SOC_AM33XX
	562	void __init am33xx_init_early(void)
	563	{
	564	omap2_set_globals_tap(AM335X_CLASS,
	565	AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
	566	omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
	567	NULL);
	568	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
	569	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
	570	omap3xxx_check_revision();
	571	ti81xx_check_features();
	572	am33xx_voltagedomains_init();
	573	am33xx_powerdomains_init();
	574	am33xx_clockdomains_init();
	575	am33xx_hwmod_init();
	576	omap_hwmod_init_postsetup();
	577	omap_clk_init = am33xx_clk_init;
	578	}
	579	#endif
	580
	581	#ifdef CONFIG_ARCH_OMAP4
	582	void __init omap4430_init_early(void)
	583	{
	584	omap2_set_globals_tap(OMAP443X_CLASS,
	585	OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
	586	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
	587	OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
	588	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
	589	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
	590	OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
	591	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
	592	omap_prm_base_init();
	593	omap_cm_base_init();
	594	omap4xxx_check_revision();
	595	omap4xxx_check_features();
	596	omap44xx_prm_init();
	597	omap44xx_voltagedomains_init();
	598	omap44xx_powerdomains_init();
	599	omap44xx_clockdomains_init();
	600	omap44xx_hwmod_init();
	601	omap_hwmod_init_postsetup();
	602	omap_clk_init = omap4xxx_clk_init;
	603	}
	604
	605	void __init omap4430_init_late(void)
	606	{
	607	omap_mux_late_init();
	608	omap2_common_pm_late_init();
	609	omap4_pm_init();
	610	omap2_clk_enable_autoidle_all();
	611	}
	612	#endif
	613
	614	#ifdef CONFIG_SOC_OMAP5
	615	void __init omap5_init_early(void)
	616	{
	617	omap2_set_globals_tap(OMAP54XX_CLASS,
	618	OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
	619	omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
	620	OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
	621	omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
	622	omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
	623	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
	624	omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
	625	omap_prm_base_init();
	626	omap_cm_base_init();
	627	omap5xxx_check_revision();
	628	}
	629	#endif
	630
	631	void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
	632	struct omap_sdrc_params *sdrc_cs1)
	633	{
	634	omap_sram_init();
	635
	636	if (cpu_is_omap24xx() \|\| omap3_has_sdrc()) {
	637	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
	638	_omap2_init_reprogram_sdrc();
	639	}
	640	}