| 1 | /* |
| 2 | * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 |
| 3 | * |
| 4 | * Copyright (C) 2011 Nokia Corporation |
| 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
| 6 | * Paul Walmsley |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/dmaengine.h> |
| 14 | #include <linux/omap-dma.h> |
| 15 | |
| 16 | #include "omap_hwmod.h" |
| 17 | #include "hdq1w.h" |
| 18 | |
| 19 | #include "omap_hwmod_common_data.h" |
| 20 | #include "dma.h" |
| 21 | |
| 22 | /* UART */ |
| 23 | |
| 24 | static struct omap_hwmod_class_sysconfig omap2_uart_sysc = { |
| 25 | .rev_offs = 0x50, |
| 26 | .sysc_offs = 0x54, |
| 27 | .syss_offs = 0x58, |
| 28 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 29 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 30 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 31 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 32 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 33 | }; |
| 34 | |
| 35 | struct omap_hwmod_class omap2_uart_class = { |
| 36 | .name = "uart", |
| 37 | .sysc = &omap2_uart_sysc, |
| 38 | }; |
| 39 | |
| 40 | /* |
| 41 | * 'dss' class |
| 42 | * display sub-system |
| 43 | */ |
| 44 | |
| 45 | static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { |
| 46 | .rev_offs = 0x0000, |
| 47 | .sysc_offs = 0x0010, |
| 48 | .syss_offs = 0x0014, |
| 49 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 50 | SYSS_HAS_RESET_STATUS), |
| 51 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 52 | }; |
| 53 | |
| 54 | struct omap_hwmod_class omap2_dss_hwmod_class = { |
| 55 | .name = "dss", |
| 56 | .sysc = &omap2_dss_sysc, |
| 57 | .reset = omap_dss_reset, |
| 58 | }; |
| 59 | |
| 60 | /* |
| 61 | * 'rfbi' class |
| 62 | * remote frame buffer interface |
| 63 | */ |
| 64 | |
| 65 | static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = { |
| 66 | .rev_offs = 0x0000, |
| 67 | .sysc_offs = 0x0010, |
| 68 | .syss_offs = 0x0014, |
| 69 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 70 | SYSC_HAS_AUTOIDLE), |
| 71 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 72 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 73 | }; |
| 74 | |
| 75 | struct omap_hwmod_class omap2_rfbi_hwmod_class = { |
| 76 | .name = "rfbi", |
| 77 | .sysc = &omap2_rfbi_sysc, |
| 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * 'venc' class |
| 82 | * video encoder |
| 83 | */ |
| 84 | |
| 85 | struct omap_hwmod_class omap2_venc_hwmod_class = { |
| 86 | .name = "venc", |
| 87 | }; |
| 88 | |
| 89 | |
| 90 | /* Common DMA request line data */ |
| 91 | struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = { |
| 92 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 93 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 94 | { .dma_req = -1 } |
| 95 | }; |
| 96 | |
| 97 | struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = { |
| 98 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 99 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 100 | { .dma_req = -1 } |
| 101 | }; |
| 102 | |
| 103 | struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = { |
| 104 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 105 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 106 | { .dma_req = -1 } |
| 107 | }; |
| 108 | |
| 109 | struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = { |
| 110 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 111 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 112 | { .dma_req = -1 } |
| 113 | }; |
| 114 | |
| 115 | struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = { |
| 116 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 117 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 118 | { .dma_req = -1 } |
| 119 | }; |
| 120 | |
| 121 | struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = { |
| 122 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 123 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 124 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 125 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 126 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 127 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 128 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 129 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 130 | { .dma_req = -1 } |
| 131 | }; |
| 132 | |
| 133 | struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = { |
| 134 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 135 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 136 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 137 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 138 | { .dma_req = -1 } |
| 139 | }; |
| 140 | |
| 141 | struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = { |
| 142 | { .name = "rx", .dma_req = 32 }, |
| 143 | { .name = "tx", .dma_req = 31 }, |
| 144 | { .dma_req = -1 } |
| 145 | }; |
| 146 | |
| 147 | struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = { |
| 148 | { .name = "rx", .dma_req = 34 }, |
| 149 | { .name = "tx", .dma_req = 33 }, |
| 150 | { .dma_req = -1 } |
| 151 | }; |
| 152 | |
| 153 | struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = { |
| 154 | { .name = "rx", .dma_req = 18 }, |
| 155 | { .name = "tx", .dma_req = 17 }, |
| 156 | { .dma_req = -1 } |
| 157 | }; |
| 158 | |
| 159 | /* Other IP block data */ |
| 160 | |
| 161 | |
| 162 | /* |
| 163 | * omap_hwmod class data |
| 164 | */ |
| 165 | |
| 166 | struct omap_hwmod_class l3_hwmod_class = { |
| 167 | .name = "l3" |
| 168 | }; |
| 169 | |
| 170 | struct omap_hwmod_class l4_hwmod_class = { |
| 171 | .name = "l4" |
| 172 | }; |
| 173 | |
| 174 | struct omap_hwmod_class mpu_hwmod_class = { |
| 175 | .name = "mpu" |
| 176 | }; |
| 177 | |
| 178 | struct omap_hwmod_class iva_hwmod_class = { |
| 179 | .name = "iva" |
| 180 | }; |
| 181 | |
| 182 | /* Common MPU IRQ line data */ |
| 183 | |
| 184 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { |
| 185 | { .irq = 37 + OMAP_INTC_START, }, |
| 186 | { .irq = -1 }, |
| 187 | }; |
| 188 | |
| 189 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { |
| 190 | { .irq = 38 + OMAP_INTC_START, }, |
| 191 | { .irq = -1 }, |
| 192 | }; |
| 193 | |
| 194 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { |
| 195 | { .irq = 39 + OMAP_INTC_START, }, |
| 196 | { .irq = -1 }, |
| 197 | }; |
| 198 | |
| 199 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { |
| 200 | { .irq = 40 + OMAP_INTC_START, }, |
| 201 | { .irq = -1 }, |
| 202 | }; |
| 203 | |
| 204 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { |
| 205 | { .irq = 41 + OMAP_INTC_START, }, |
| 206 | { .irq = -1 }, |
| 207 | }; |
| 208 | |
| 209 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { |
| 210 | { .irq = 42 + OMAP_INTC_START, }, |
| 211 | { .irq = -1 }, |
| 212 | }; |
| 213 | |
| 214 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { |
| 215 | { .irq = 43 + OMAP_INTC_START, }, |
| 216 | { .irq = -1 }, |
| 217 | }; |
| 218 | |
| 219 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { |
| 220 | { .irq = 44 + OMAP_INTC_START, }, |
| 221 | { .irq = -1 }, |
| 222 | }; |
| 223 | |
| 224 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { |
| 225 | { .irq = 45 + OMAP_INTC_START, }, |
| 226 | { .irq = -1 }, |
| 227 | }; |
| 228 | |
| 229 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { |
| 230 | { .irq = 46 + OMAP_INTC_START, }, |
| 231 | { .irq = -1 }, |
| 232 | }; |
| 233 | |
| 234 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { |
| 235 | { .irq = 47 + OMAP_INTC_START, }, |
| 236 | { .irq = -1 }, |
| 237 | }; |
| 238 | |
| 239 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { |
| 240 | { .irq = 72 + OMAP_INTC_START, }, |
| 241 | { .irq = -1 }, |
| 242 | }; |
| 243 | |
| 244 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { |
| 245 | { .irq = 73 + OMAP_INTC_START, }, |
| 246 | { .irq = -1 }, |
| 247 | }; |
| 248 | |
| 249 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { |
| 250 | { .irq = 74 + OMAP_INTC_START, }, |
| 251 | { .irq = -1 }, |
| 252 | }; |
| 253 | |
| 254 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { |
| 255 | { .irq = 25 + OMAP_INTC_START, }, |
| 256 | { .irq = -1 }, |
| 257 | }; |
| 258 | |
| 259 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { |
| 260 | { .irq = 56 + OMAP_INTC_START, }, |
| 261 | { .irq = -1 }, |
| 262 | }; |
| 263 | |
| 264 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { |
| 265 | { .irq = 57 + OMAP_INTC_START, }, |
| 266 | { .irq = -1 }, |
| 267 | }; |
| 268 | |
| 269 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { |
| 270 | { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ |
| 271 | { .irq = -1 }, |
| 272 | }; |
| 273 | |
| 274 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { |
| 275 | { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ |
| 276 | { .irq = -1 }, |
| 277 | }; |
| 278 | |
| 279 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { |
| 280 | { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ |
| 281 | { .irq = -1 }, |
| 282 | }; |
| 283 | |
| 284 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { |
| 285 | { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ |
| 286 | { .irq = -1 }, |
| 287 | }; |
| 288 | |
| 289 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { |
| 290 | { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ |
| 291 | { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ |
| 292 | { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ |
| 293 | { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ |
| 294 | { .irq = -1 }, |
| 295 | }; |
| 296 | |
| 297 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { |
| 298 | { .irq = 65 + OMAP_INTC_START, }, |
| 299 | { .irq = -1 }, |
| 300 | }; |
| 301 | |
| 302 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { |
| 303 | { .irq = 66 + OMAP_INTC_START, }, |
| 304 | { .irq = -1 }, |
| 305 | }; |
| 306 | |
| 307 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { |
| 308 | .rev_offs = 0x0, |
| 309 | .sysc_offs = 0x14, |
| 310 | .syss_offs = 0x18, |
| 311 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 312 | SYSS_HAS_RESET_STATUS), |
| 313 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 314 | }; |
| 315 | |
| 316 | struct omap_hwmod_class omap2_hdq1w_class = { |
| 317 | .name = "hdq1w", |
| 318 | .sysc = &omap2_hdq1w_sysc, |
| 319 | .reset = &omap_hdq1w_reset, |
| 320 | }; |
| 321 | |
| 322 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { |
| 323 | { .irq = 58 + OMAP_INTC_START, }, |
| 324 | { .irq = -1 }, |
| 325 | }; |
| 326 | |