Merge tag 'kvm-arm-for-v4.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-pxa / pxa27x.c
... / ...
CommitLineData
1/*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/gpio.h>
15#include <linux/gpio-pxa.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/suspend.h>
20#include <linux/platform_device.h>
21#include <linux/syscore_ops.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/i2c/pxa-i2c.h>
25
26#include <asm/mach/map.h>
27#include <mach/hardware.h>
28#include <asm/irq.h>
29#include <asm/suspend.h>
30#include <mach/irqs.h>
31#include "pxa27x.h"
32#include <mach/reset.h>
33#include <linux/platform_data/usb-ohci-pxa27x.h>
34#include "pm.h"
35#include <mach/dma.h>
36#include <mach/smemc.h>
37
38#include "generic.h"
39#include "devices.h"
40#include <linux/clk-provider.h>
41#include <linux/clkdev.h>
42
43void pxa27x_clear_otgph(void)
44{
45 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
46 PSSR |= PSSR_OTGPH;
47}
48EXPORT_SYMBOL(pxa27x_clear_otgph);
49
50static unsigned long ac97_reset_config[] = {
51 GPIO113_AC97_nRESET_GPIO_HIGH,
52 GPIO113_AC97_nRESET,
53 GPIO95_AC97_nRESET_GPIO_HIGH,
54 GPIO95_AC97_nRESET,
55};
56
57void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
58{
59 /*
60 * This helper function is used to work around a bug in the pxa27x's
61 * ac97 controller during a warm reset. The configuration of the
62 * reset_gpio is changed as follows:
63 * to_gpio == true: configured to generic output gpio and driven high
64 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
65 */
66
67 if (reset_gpio == 113)
68 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
69 &ac97_reset_config[1], 1);
70
71 if (reset_gpio == 95)
72 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
73 &ac97_reset_config[3], 1);
74}
75EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
76
77#ifdef CONFIG_PM
78
79#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
80#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
81
82/*
83 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
84 */
85static unsigned int pwrmode = PWRMODE_SLEEP;
86
87int pxa27x_set_pwrmode(unsigned int mode)
88{
89 switch (mode) {
90 case PWRMODE_SLEEP:
91 case PWRMODE_DEEPSLEEP:
92 pwrmode = mode;
93 return 0;
94 }
95
96 return -EINVAL;
97}
98
99/*
100 * List of global PXA peripheral registers to preserve.
101 * More ones like CP and general purpose register values are preserved
102 * with the stack pointer in sleep.S.
103 */
104enum {
105 SLEEP_SAVE_PSTR,
106 SLEEP_SAVE_MDREFR,
107 SLEEP_SAVE_PCFR,
108 SLEEP_SAVE_COUNT
109};
110
111void pxa27x_cpu_pm_save(unsigned long *sleep_save)
112{
113 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
114 SAVE(PCFR);
115
116 SAVE(PSTR);
117}
118
119void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
120{
121 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
122 RESTORE(PCFR);
123
124 PSSR = PSSR_RDH | PSSR_PH;
125
126 RESTORE(PSTR);
127}
128
129void pxa27x_cpu_pm_enter(suspend_state_t state)
130{
131 extern void pxa_cpu_standby(void);
132#ifndef CONFIG_IWMMXT
133 u64 acc0;
134
135 asm volatile(".arch_extension xscale\n\t"
136 "mra %Q0, %R0, acc0" : "=r" (acc0));
137#endif
138
139 /* ensure voltage-change sequencer not initiated, which hangs */
140 PCFR &= ~PCFR_FVC;
141
142 /* Clear edge-detect status register. */
143 PEDR = 0xDF12FE1B;
144
145 /* Clear reset status */
146 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
147
148 switch (state) {
149 case PM_SUSPEND_STANDBY:
150 pxa_cpu_standby();
151 break;
152 case PM_SUSPEND_MEM:
153 cpu_suspend(pwrmode, pxa27x_finish_suspend);
154#ifndef CONFIG_IWMMXT
155 asm volatile(".arch_extension xscale\n\t"
156 "mar acc0, %Q0, %R0" : "=r" (acc0));
157#endif
158 break;
159 }
160}
161
162static int pxa27x_cpu_pm_valid(suspend_state_t state)
163{
164 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
165}
166
167static int pxa27x_cpu_pm_prepare(void)
168{
169 /* set resume return address */
170 PSPR = virt_to_phys(cpu_resume);
171 return 0;
172}
173
174static void pxa27x_cpu_pm_finish(void)
175{
176 /* ensure not to come back here if it wasn't intended */
177 PSPR = 0;
178}
179
180static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
181 .save_count = SLEEP_SAVE_COUNT,
182 .save = pxa27x_cpu_pm_save,
183 .restore = pxa27x_cpu_pm_restore,
184 .valid = pxa27x_cpu_pm_valid,
185 .enter = pxa27x_cpu_pm_enter,
186 .prepare = pxa27x_cpu_pm_prepare,
187 .finish = pxa27x_cpu_pm_finish,
188};
189
190static void __init pxa27x_init_pm(void)
191{
192 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
193}
194#else
195static inline void pxa27x_init_pm(void) {}
196#endif
197
198/* PXA27x: Various gpios can issue wakeup events. This logic only
199 * handles the simple cases, not the WEMUX2 and WEMUX3 options
200 */
201static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
202{
203 int gpio = pxa_irq_to_gpio(d->irq);
204 uint32_t mask;
205
206 if (gpio >= 0 && gpio < 128)
207 return gpio_set_wake(gpio, on);
208
209 if (d->irq == IRQ_KEYPAD)
210 return keypad_set_wake(on);
211
212 switch (d->irq) {
213 case IRQ_RTCAlrm:
214 mask = PWER_RTC;
215 break;
216 case IRQ_USB:
217 mask = 1u << 26;
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 if (on)
224 PWER |= mask;
225 else
226 PWER &=~mask;
227
228 return 0;
229}
230
231void __init pxa27x_init_irq(void)
232{
233 pxa_init_irq(34, pxa27x_set_wake);
234}
235
236void __init pxa27x_dt_init_irq(void)
237{
238 if (IS_ENABLED(CONFIG_OF))
239 pxa_dt_irq_init(pxa27x_set_wake);
240}
241
242static struct map_desc pxa27x_io_desc[] __initdata = {
243 { /* Mem Ctl */
244 .virtual = (unsigned long)SMEMC_VIRT,
245 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
246 .length = SMEMC_SIZE,
247 .type = MT_DEVICE
248 }, { /* UNCACHED_PHYS_0 */
249 .virtual = UNCACHED_PHYS_0,
250 .pfn = __phys_to_pfn(0x00000000),
251 .length = UNCACHED_PHYS_0_SIZE,
252 .type = MT_DEVICE
253 },
254};
255
256void __init pxa27x_map_io(void)
257{
258 pxa_map_io();
259 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
260 pxa27x_get_clk_frequency_khz(1);
261}
262
263/*
264 * device registration specific to PXA27x.
265 */
266void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
267{
268 local_irq_disable();
269 PCFR |= PCFR_PI2CEN;
270 local_irq_enable();
271 pxa_register_device(&pxa27x_device_i2c_power, info);
272}
273
274static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
275 .irq_base = PXA_GPIO_TO_IRQ(0),
276 .gpio_set_wake = gpio_set_wake,
277};
278
279static struct platform_device *devices[] __initdata = {
280 &pxa27x_device_udc,
281 &pxa_device_pmu,
282 &pxa_device_i2s,
283 &pxa_device_asoc_ssp1,
284 &pxa_device_asoc_ssp2,
285 &pxa_device_asoc_ssp3,
286 &pxa_device_asoc_platform,
287 &pxa_device_rtc,
288 &pxa27x_device_ssp1,
289 &pxa27x_device_ssp2,
290 &pxa27x_device_ssp3,
291 &pxa27x_device_pwm0,
292 &pxa27x_device_pwm1,
293};
294
295static int __init pxa27x_init(void)
296{
297 int ret = 0;
298
299 if (cpu_is_pxa27x()) {
300
301 reset_status = RCSR;
302
303 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
304 return ret;
305
306 pxa27x_init_pm();
307
308 register_syscore_ops(&pxa_irq_syscore_ops);
309 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
310
311 if (!of_have_populated_dt()) {
312 pxa_register_device(&pxa27x_device_gpio,
313 &pxa27x_gpio_info);
314 pxa2xx_set_dmac_info(32, 75);
315 ret = platform_add_devices(devices,
316 ARRAY_SIZE(devices));
317 }
318 }
319
320 return ret;
321}
322
323postcore_initcall(pxa27x_init);
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