| 1 | /* |
| 2 | * r8a7779 processor support |
| 3 | * |
| 4 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2011 Magnus Damm |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/irq.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/input.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/serial_sci.h> |
| 29 | #include <linux/sh_intc.h> |
| 30 | #include <linux/sh_timer.h> |
| 31 | #include <mach/hardware.h> |
| 32 | #include <mach/r8a7779.h> |
| 33 | #include <mach/common.h> |
| 34 | #include <asm/mach-types.h> |
| 35 | #include <asm/mach/arch.h> |
| 36 | #include <asm/mach/map.h> |
| 37 | |
| 38 | static struct map_desc r8a7779_io_desc[] __initdata = { |
| 39 | /* 2M entity map for 0xf0000000 (MPCORE) */ |
| 40 | { |
| 41 | .virtual = 0xf0000000, |
| 42 | .pfn = __phys_to_pfn(0xf0000000), |
| 43 | .length = SZ_2M, |
| 44 | .type = MT_DEVICE_NONSHARED |
| 45 | }, |
| 46 | /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ |
| 47 | { |
| 48 | .virtual = 0xfe000000, |
| 49 | .pfn = __phys_to_pfn(0xfe000000), |
| 50 | .length = SZ_16M, |
| 51 | .type = MT_DEVICE_NONSHARED |
| 52 | }, |
| 53 | }; |
| 54 | |
| 55 | void __init r8a7779_map_io(void) |
| 56 | { |
| 57 | iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); |
| 58 | } |
| 59 | |
| 60 | static struct plat_sci_port scif0_platform_data = { |
| 61 | .mapbase = 0xffe40000, |
| 62 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 63 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 64 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 65 | .type = PORT_SCIF, |
| 66 | .irqs = { gic_spi(88), gic_spi(88), |
| 67 | gic_spi(88), gic_spi(88) }, |
| 68 | }; |
| 69 | |
| 70 | static struct platform_device scif0_device = { |
| 71 | .name = "sh-sci", |
| 72 | .id = 0, |
| 73 | .dev = { |
| 74 | .platform_data = &scif0_platform_data, |
| 75 | }, |
| 76 | }; |
| 77 | |
| 78 | static struct plat_sci_port scif1_platform_data = { |
| 79 | .mapbase = 0xffe41000, |
| 80 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 81 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 82 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 83 | .type = PORT_SCIF, |
| 84 | .irqs = { gic_spi(89), gic_spi(89), |
| 85 | gic_spi(89), gic_spi(89) }, |
| 86 | }; |
| 87 | |
| 88 | static struct platform_device scif1_device = { |
| 89 | .name = "sh-sci", |
| 90 | .id = 1, |
| 91 | .dev = { |
| 92 | .platform_data = &scif1_platform_data, |
| 93 | }, |
| 94 | }; |
| 95 | |
| 96 | static struct plat_sci_port scif2_platform_data = { |
| 97 | .mapbase = 0xffe42000, |
| 98 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 99 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 100 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 101 | .type = PORT_SCIF, |
| 102 | .irqs = { gic_spi(90), gic_spi(90), |
| 103 | gic_spi(90), gic_spi(90) }, |
| 104 | }; |
| 105 | |
| 106 | static struct platform_device scif2_device = { |
| 107 | .name = "sh-sci", |
| 108 | .id = 2, |
| 109 | .dev = { |
| 110 | .platform_data = &scif2_platform_data, |
| 111 | }, |
| 112 | }; |
| 113 | |
| 114 | static struct plat_sci_port scif3_platform_data = { |
| 115 | .mapbase = 0xffe43000, |
| 116 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 117 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 118 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 119 | .type = PORT_SCIF, |
| 120 | .irqs = { gic_spi(91), gic_spi(91), |
| 121 | gic_spi(91), gic_spi(91) }, |
| 122 | }; |
| 123 | |
| 124 | static struct platform_device scif3_device = { |
| 125 | .name = "sh-sci", |
| 126 | .id = 3, |
| 127 | .dev = { |
| 128 | .platform_data = &scif3_platform_data, |
| 129 | }, |
| 130 | }; |
| 131 | |
| 132 | static struct plat_sci_port scif4_platform_data = { |
| 133 | .mapbase = 0xffe44000, |
| 134 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 135 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 136 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 137 | .type = PORT_SCIF, |
| 138 | .irqs = { gic_spi(92), gic_spi(92), |
| 139 | gic_spi(92), gic_spi(92) }, |
| 140 | }; |
| 141 | |
| 142 | static struct platform_device scif4_device = { |
| 143 | .name = "sh-sci", |
| 144 | .id = 4, |
| 145 | .dev = { |
| 146 | .platform_data = &scif4_platform_data, |
| 147 | }, |
| 148 | }; |
| 149 | |
| 150 | static struct plat_sci_port scif5_platform_data = { |
| 151 | .mapbase = 0xffe45000, |
| 152 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 153 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 154 | .scbrr_algo_id = SCBRR_ALGO_2, |
| 155 | .type = PORT_SCIF, |
| 156 | .irqs = { gic_spi(93), gic_spi(93), |
| 157 | gic_spi(93), gic_spi(93) }, |
| 158 | }; |
| 159 | |
| 160 | static struct platform_device scif5_device = { |
| 161 | .name = "sh-sci", |
| 162 | .id = 5, |
| 163 | .dev = { |
| 164 | .platform_data = &scif5_platform_data, |
| 165 | }, |
| 166 | }; |
| 167 | |
| 168 | /* TMU */ |
| 169 | static struct sh_timer_config tmu00_platform_data = { |
| 170 | .name = "TMU00", |
| 171 | .channel_offset = 0x4, |
| 172 | .timer_bit = 0, |
| 173 | .clockevent_rating = 200, |
| 174 | }; |
| 175 | |
| 176 | static struct resource tmu00_resources[] = { |
| 177 | [0] = { |
| 178 | .name = "TMU00", |
| 179 | .start = 0xffd80008, |
| 180 | .end = 0xffd80013, |
| 181 | .flags = IORESOURCE_MEM, |
| 182 | }, |
| 183 | [1] = { |
| 184 | .start = gic_spi(32), |
| 185 | .flags = IORESOURCE_IRQ, |
| 186 | }, |
| 187 | }; |
| 188 | |
| 189 | static struct platform_device tmu00_device = { |
| 190 | .name = "sh_tmu", |
| 191 | .id = 0, |
| 192 | .dev = { |
| 193 | .platform_data = &tmu00_platform_data, |
| 194 | }, |
| 195 | .resource = tmu00_resources, |
| 196 | .num_resources = ARRAY_SIZE(tmu00_resources), |
| 197 | }; |
| 198 | |
| 199 | static struct sh_timer_config tmu01_platform_data = { |
| 200 | .name = "TMU01", |
| 201 | .channel_offset = 0x10, |
| 202 | .timer_bit = 1, |
| 203 | .clocksource_rating = 200, |
| 204 | }; |
| 205 | |
| 206 | static struct resource tmu01_resources[] = { |
| 207 | [0] = { |
| 208 | .name = "TMU01", |
| 209 | .start = 0xffd80014, |
| 210 | .end = 0xffd8001f, |
| 211 | .flags = IORESOURCE_MEM, |
| 212 | }, |
| 213 | [1] = { |
| 214 | .start = gic_spi(33), |
| 215 | .flags = IORESOURCE_IRQ, |
| 216 | }, |
| 217 | }; |
| 218 | |
| 219 | static struct platform_device tmu01_device = { |
| 220 | .name = "sh_tmu", |
| 221 | .id = 1, |
| 222 | .dev = { |
| 223 | .platform_data = &tmu01_platform_data, |
| 224 | }, |
| 225 | .resource = tmu01_resources, |
| 226 | .num_resources = ARRAY_SIZE(tmu01_resources), |
| 227 | }; |
| 228 | |
| 229 | static struct platform_device *r8a7779_early_devices[] __initdata = { |
| 230 | &scif0_device, |
| 231 | &scif1_device, |
| 232 | &scif2_device, |
| 233 | &scif3_device, |
| 234 | &scif4_device, |
| 235 | &scif5_device, |
| 236 | &tmu00_device, |
| 237 | &tmu01_device, |
| 238 | }; |
| 239 | |
| 240 | static struct platform_device *r8a7779_late_devices[] __initdata = { |
| 241 | }; |
| 242 | |
| 243 | void __init r8a7779_add_standard_devices(void) |
| 244 | { |
| 245 | r8a7779_pm_init(); |
| 246 | |
| 247 | r8a7779_init_pm_domain(&r8a7779_sh4a); |
| 248 | r8a7779_init_pm_domain(&r8a7779_sgx); |
| 249 | r8a7779_init_pm_domain(&r8a7779_vdp1); |
| 250 | r8a7779_init_pm_domain(&r8a7779_impx3); |
| 251 | |
| 252 | platform_add_devices(r8a7779_early_devices, |
| 253 | ARRAY_SIZE(r8a7779_early_devices)); |
| 254 | platform_add_devices(r8a7779_late_devices, |
| 255 | ARRAY_SIZE(r8a7779_late_devices)); |
| 256 | } |
| 257 | |
| 258 | void __init r8a7779_add_early_devices(void) |
| 259 | { |
| 260 | early_platform_add_devices(r8a7779_early_devices, |
| 261 | ARRAY_SIZE(r8a7779_early_devices)); |
| 262 | |
| 263 | /* Early serial console setup is not included here due to |
| 264 | * memory map collisions. The SCIF serial ports in r8a7779 |
| 265 | * are difficult to entity map 1:1 due to collision with the |
| 266 | * virtual memory range used by the coherent DMA code on ARM. |
| 267 | * |
| 268 | * Anyone wanting to debug early can remove UPF_IOREMAP from |
| 269 | * the sh-sci serial console platform data, adjust mapbase |
| 270 | * to a static M:N virt:phys mapping that needs to be added to |
| 271 | * the mappings passed with iotable_init() above. |
| 272 | * |
| 273 | * Then add a call to shmobile_setup_console() from this function. |
| 274 | * |
| 275 | * As a final step pass earlyprint=sh-sci.2,115200 on the kernel |
| 276 | * command line in case of the marzen board. |
| 277 | */ |
| 278 | } |