[deliverable/linux.git] / arch / arm / mach-ux500 / cache-l2x0.c

/*
 * Copyright (C) ST-Ericsson SA 2011
 *
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/outercache.h>
#include <asm/hardware/cache-l2x0.h>

#include "db8500-regs.h"
#include "id.h"

static int __init ux500_l2x0_unlock(void)
{
	int i;
	struct device_node *np;
	void __iomem *l2x0_base;

	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	l2x0_base = of_iomap(np, 0);
	of_node_put(np);
	if (!l2x0_base)
		return -ENODEV;

	/*
	 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
	 * apparently locks both caches before jumping to the kernel. The
	 * l2x0 core will not touch the unlock registers if the l2x0 is
	 * already enabled, so we do it right here instead. The PL310 has
	 * 8 sets of registers, one per possible CPU.
	 */
	for (i = 0; i < 8; i++) {
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
			       i * L2X0_LOCKDOWN_STRIDE);
	}
	iounmap(l2x0_base);
	return 0;
}

static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
{
	/*
	 * We can't write to secure registers as we are in non-secure
	 * mode, until we have some SMI service available.
	 */
}

static int __init ux500_l2x0_init(void)
{
	/* Multiplatform guard */
	if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
		return -ENODEV;

	/* Unlock before init */
	ux500_l2x0_unlock();
	outer_cache.write_sec = ux500_l2c310_write_sec;
	l2x0_of_init(0, ~0);

	return 0;
}
early_initcall(ux500_l2x0_init);
Commit	Line	Data
	1	/*
	2	* Copyright (C) ST-Ericsson SA 2011
	3	*
	4	* License terms: GNU General Public License (GPL) version 2
	5	*/
	6
	7	#include <linux/io.h>
	8	#include <linux/of.h>
	9	#include <linux/of_address.h>
	10
	11	#include <asm/outercache.h>
	12	#include <asm/hardware/cache-l2x0.h>
	13
	14	#include "db8500-regs.h"
	15	#include "id.h"
	16
	17	static int __init ux500_l2x0_unlock(void)
	18	{
	19	int i;
	20	struct device_node *np;
	21	void __iomem *l2x0_base;
	22
	23	np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
	24	l2x0_base = of_iomap(np, 0);
	25	of_node_put(np);
	26	if (!l2x0_base)
	27	return -ENODEV;
	28
	29	/*
	30	* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
	31	* apparently locks both caches before jumping to the kernel. The
	32	* l2x0 core will not touch the unlock registers if the l2x0 is
	33	* already enabled, so we do it right here instead. The PL310 has
	34	* 8 sets of registers, one per possible CPU.
	35	*/
	36	for (i = 0; i < 8; i++) {
	37	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
	38	i * L2X0_LOCKDOWN_STRIDE);
	39	writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
	40	i * L2X0_LOCKDOWN_STRIDE);
	41	}
	42	iounmap(l2x0_base);
	43	return 0;
	44	}
	45
	46	static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
	47	{
	48	/*
	49	* We can't write to secure registers as we are in non-secure
	50	* mode, until we have some SMI service available.
	51	*/
	52	}
	53
	54	static int __init ux500_l2x0_init(void)
	55	{
	56	/* Multiplatform guard */
	57	if (!((cpu_is_u8500_family() \|\| cpu_is_ux540_family())))
	58	return -ENODEV;
	59
	60	/* Unlock before init */
	61	ux500_l2x0_unlock();
	62	outer_cache.write_sec = ux500_l2c310_write_sec;
	63	l2x0_of_init(0, ~0);
	64
	65	return 0;
	66	}
	67	early_initcall(ux500_l2x0_init);