| 1 | /* |
| 2 | * Xilinx SLCR driver |
| 3 | * |
| 4 | * Copyright (c) 2011-2013 Xilinx Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * You should have received a copy of the GNU General Public |
| 12 | * License along with this program; if not, write to the Free |
| 13 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA |
| 14 | * 02139, USA. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/mfd/syscon.h> |
| 19 | #include <linux/of_address.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <linux/clk/zynq.h> |
| 22 | #include "common.h" |
| 23 | |
| 24 | /* register offsets */ |
| 25 | #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ |
| 26 | #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ |
| 27 | #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ |
| 28 | #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ |
| 29 | |
| 30 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
| 31 | #define SLCR_A9_CPU_CLKSTOP 0x10 |
| 32 | #define SLCR_A9_CPU_RST 0x1 |
| 33 | |
| 34 | static void __iomem *zynq_slcr_base; |
| 35 | static struct regmap *zynq_slcr_regmap; |
| 36 | |
| 37 | /** |
| 38 | * zynq_slcr_write - Write to a register in SLCR block |
| 39 | * |
| 40 | * @val: Value to write to the register |
| 41 | * @offset: Register offset in SLCR block |
| 42 | * |
| 43 | * Return: a negative value on error, 0 on success |
| 44 | */ |
| 45 | static int zynq_slcr_write(u32 val, u32 offset) |
| 46 | { |
| 47 | if (!zynq_slcr_regmap) { |
| 48 | writel(val, zynq_slcr_base + offset); |
| 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | return regmap_write(zynq_slcr_regmap, offset, val); |
| 53 | } |
| 54 | |
| 55 | /** |
| 56 | * zynq_slcr_read - Read a register in SLCR block |
| 57 | * |
| 58 | * @val: Pointer to value to be read from SLCR |
| 59 | * @offset: Register offset in SLCR block |
| 60 | * |
| 61 | * Return: a negative value on error, 0 on success |
| 62 | */ |
| 63 | static int zynq_slcr_read(u32 *val, u32 offset) |
| 64 | { |
| 65 | if (zynq_slcr_regmap) |
| 66 | return regmap_read(zynq_slcr_regmap, offset, val); |
| 67 | |
| 68 | *val = readl(zynq_slcr_base + offset); |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | /** |
| 74 | * zynq_slcr_unlock - Unlock SLCR registers |
| 75 | * |
| 76 | * Return: a negative value on error, 0 on success |
| 77 | */ |
| 78 | static inline int zynq_slcr_unlock(void) |
| 79 | { |
| 80 | zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET); |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | /** |
| 86 | * zynq_slcr_system_reset - Reset the entire system. |
| 87 | */ |
| 88 | void zynq_slcr_system_reset(void) |
| 89 | { |
| 90 | u32 reboot; |
| 91 | |
| 92 | /* |
| 93 | * Unlock the SLCR then reset the system. |
| 94 | * Note that this seems to require raw i/o |
| 95 | * functions or there's a lockup? |
| 96 | */ |
| 97 | zynq_slcr_unlock(); |
| 98 | |
| 99 | /* |
| 100 | * Clear 0x0F000000 bits of reboot status register to workaround |
| 101 | * the FSBL not loading the bitstream after soft-reboot |
| 102 | * This is a temporary solution until we know more. |
| 103 | */ |
| 104 | zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); |
| 105 | zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); |
| 106 | zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); |
| 107 | } |
| 108 | |
| 109 | /** |
| 110 | * zynq_slcr_cpu_start - Start cpu |
| 111 | * @cpu: cpu number |
| 112 | */ |
| 113 | void zynq_slcr_cpu_start(int cpu) |
| 114 | { |
| 115 | u32 reg; |
| 116 | |
| 117 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); |
| 118 | reg &= ~(SLCR_A9_CPU_RST << cpu); |
| 119 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
| 120 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); |
| 121 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
| 122 | } |
| 123 | |
| 124 | /** |
| 125 | * zynq_slcr_cpu_stop - Stop cpu |
| 126 | * @cpu: cpu number |
| 127 | */ |
| 128 | void zynq_slcr_cpu_stop(int cpu) |
| 129 | { |
| 130 | u32 reg; |
| 131 | |
| 132 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); |
| 133 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; |
| 134 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
| 135 | } |
| 136 | |
| 137 | /** |
| 138 | * zynq_slcr_init - Regular slcr driver init |
| 139 | * |
| 140 | * Return: 0 on success, negative errno otherwise. |
| 141 | * |
| 142 | * Called early during boot from platform code to remap SLCR area. |
| 143 | */ |
| 144 | int __init zynq_slcr_init(void) |
| 145 | { |
| 146 | zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); |
| 147 | if (IS_ERR(zynq_slcr_regmap)) { |
| 148 | pr_err("%s: failed to find zynq-slcr\n", __func__); |
| 149 | return -ENODEV; |
| 150 | } |
| 151 | |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | /** |
| 156 | * zynq_early_slcr_init - Early slcr init function |
| 157 | * |
| 158 | * Return: 0 on success, negative errno otherwise. |
| 159 | * |
| 160 | * Called very early during boot from platform code to unlock SLCR. |
| 161 | */ |
| 162 | int __init zynq_early_slcr_init(void) |
| 163 | { |
| 164 | struct device_node *np; |
| 165 | |
| 166 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); |
| 167 | if (!np) { |
| 168 | pr_err("%s: no slcr node found\n", __func__); |
| 169 | BUG(); |
| 170 | } |
| 171 | |
| 172 | zynq_slcr_base = of_iomap(np, 0); |
| 173 | if (!zynq_slcr_base) { |
| 174 | pr_err("%s: Unable to map I/O memory\n", __func__); |
| 175 | BUG(); |
| 176 | } |
| 177 | |
| 178 | np->data = (__force void *)zynq_slcr_base; |
| 179 | |
| 180 | /* unlock the SLCR so that registers can be changed */ |
| 181 | zynq_slcr_unlock(); |
| 182 | |
| 183 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); |
| 184 | |
| 185 | of_node_put(np); |
| 186 | |
| 187 | return 0; |
| 188 | } |