| 1 | /* |
| 2 | * linux/arch/arm/vfp/vfphw.S |
| 3 | * |
| 4 | * Copyright (C) 2004 ARM Limited. |
| 5 | * Written by Deep Blue Solutions Limited. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This code is called from the kernel's undefined instruction trap. |
| 12 | * r9 holds the return address for successful handling. |
| 13 | * lr holds the return address for unrecognised instructions. |
| 14 | * r10 points at the start of the private FP workspace in the thread structure |
| 15 | * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) |
| 16 | */ |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/linkage.h> |
| 19 | #include <asm/thread_info.h> |
| 20 | #include <asm/vfpmacros.h> |
| 21 | #include <linux/kern_levels.h> |
| 22 | #include <asm/assembler.h> |
| 23 | #include <asm/asm-offsets.h> |
| 24 | |
| 25 | .macro DBGSTR, str |
| 26 | #ifdef DEBUG |
| 27 | stmfd sp!, {r0-r3, ip, lr} |
| 28 | ldr r0, =1f |
| 29 | bl printk |
| 30 | ldmfd sp!, {r0-r3, ip, lr} |
| 31 | |
| 32 | .pushsection .rodata, "a" |
| 33 | 1: .ascii KERN_DEBUG "VFP: \str\n" |
| 34 | .byte 0 |
| 35 | .previous |
| 36 | #endif |
| 37 | .endm |
| 38 | |
| 39 | .macro DBGSTR1, str, arg |
| 40 | #ifdef DEBUG |
| 41 | stmfd sp!, {r0-r3, ip, lr} |
| 42 | mov r1, \arg |
| 43 | ldr r0, =1f |
| 44 | bl printk |
| 45 | ldmfd sp!, {r0-r3, ip, lr} |
| 46 | |
| 47 | .pushsection .rodata, "a" |
| 48 | 1: .ascii KERN_DEBUG "VFP: \str\n" |
| 49 | .byte 0 |
| 50 | .previous |
| 51 | #endif |
| 52 | .endm |
| 53 | |
| 54 | .macro DBGSTR3, str, arg1, arg2, arg3 |
| 55 | #ifdef DEBUG |
| 56 | stmfd sp!, {r0-r3, ip, lr} |
| 57 | mov r3, \arg3 |
| 58 | mov r2, \arg2 |
| 59 | mov r1, \arg1 |
| 60 | ldr r0, =1f |
| 61 | bl printk |
| 62 | ldmfd sp!, {r0-r3, ip, lr} |
| 63 | |
| 64 | .pushsection .rodata, "a" |
| 65 | 1: .ascii KERN_DEBUG "VFP: \str\n" |
| 66 | .byte 0 |
| 67 | .previous |
| 68 | #endif |
| 69 | .endm |
| 70 | |
| 71 | |
| 72 | @ VFP hardware support entry point. |
| 73 | @ |
| 74 | @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
| 75 | @ r2 = PC value to resume execution after successful emulation |
| 76 | @ r9 = normal "successful" return address |
| 77 | @ r10 = vfp_state union |
| 78 | @ r11 = CPU number |
| 79 | @ lr = unrecognised instruction return address |
| 80 | @ IRQs enabled. |
| 81 | ENTRY(vfp_support_entry) |
| 82 | DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 |
| 83 | |
| 84 | ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions |
| 85 | and r3, r3, #MODE_MASK @ are supported in kernel mode |
| 86 | teq r3, #USR_MODE |
| 87 | bne vfp_kmode_exception @ Returns through lr |
| 88 | |
| 89 | VFPFMRX r1, FPEXC @ Is the VFP enabled? |
| 90 | DBGSTR1 "fpexc %08x", r1 |
| 91 | tst r1, #FPEXC_EN |
| 92 | bne look_for_VFP_exceptions @ VFP is already enabled |
| 93 | |
| 94 | DBGSTR1 "enable %x", r10 |
| 95 | ldr r3, vfp_current_hw_state_address |
| 96 | orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set |
| 97 | ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer |
| 98 | bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled |
| 99 | cmp r4, r10 @ this thread owns the hw context? |
| 100 | #ifndef CONFIG_SMP |
| 101 | @ For UP, checking that this thread owns the hw context is |
| 102 | @ sufficient to determine that the hardware state is valid. |
| 103 | beq vfp_hw_state_valid |
| 104 | |
| 105 | @ On UP, we lazily save the VFP context. As a different |
| 106 | @ thread wants ownership of the VFP hardware, save the old |
| 107 | @ state if there was a previous (valid) owner. |
| 108 | |
| 109 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending |
| 110 | @ exceptions, so we can get at the |
| 111 | @ rest of it |
| 112 | |
| 113 | DBGSTR1 "save old state %p", r4 |
| 114 | cmp r4, #0 @ if the vfp_current_hw_state is NULL |
| 115 | beq vfp_reload_hw @ then the hw state needs reloading |
| 116 | VFPFSTMIA r4, r5 @ save the working registers |
| 117 | VFPFMRX r5, FPSCR @ current status |
| 118 | #ifndef CONFIG_CPU_FEROCEON |
| 119 | tst r1, #FPEXC_EX @ is there additional state to save? |
| 120 | beq 1f |
| 121 | VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) |
| 122 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? |
| 123 | beq 1f |
| 124 | VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) |
| 125 | 1: |
| 126 | #endif |
| 127 | stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 |
| 128 | vfp_reload_hw: |
| 129 | |
| 130 | #else |
| 131 | @ For SMP, if this thread does not own the hw context, then we |
| 132 | @ need to reload it. No need to save the old state as on SMP, |
| 133 | @ we always save the state when we switch away from a thread. |
| 134 | bne vfp_reload_hw |
| 135 | |
| 136 | @ This thread has ownership of the current hardware context. |
| 137 | @ However, it may have been migrated to another CPU, in which |
| 138 | @ case the saved state is newer than the hardware context. |
| 139 | @ Check this by looking at the CPU number which the state was |
| 140 | @ last loaded onto. |
| 141 | ldr ip, [r10, #VFP_CPU] |
| 142 | teq ip, r11 |
| 143 | beq vfp_hw_state_valid |
| 144 | |
| 145 | vfp_reload_hw: |
| 146 | @ We're loading this threads state into the VFP hardware. Update |
| 147 | @ the CPU number which contains the most up to date VFP context. |
| 148 | str r11, [r10, #VFP_CPU] |
| 149 | |
| 150 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending |
| 151 | @ exceptions, so we can get at the |
| 152 | @ rest of it |
| 153 | #endif |
| 154 | |
| 155 | DBGSTR1 "load state %p", r10 |
| 156 | str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer |
| 157 | @ Load the saved state back into the VFP |
| 158 | VFPFLDMIA r10, r5 @ reload the working registers while |
| 159 | @ FPEXC is in a safe state |
| 160 | ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 |
| 161 | #ifndef CONFIG_CPU_FEROCEON |
| 162 | tst r1, #FPEXC_EX @ is there additional state to restore? |
| 163 | beq 1f |
| 164 | VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) |
| 165 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? |
| 166 | beq 1f |
| 167 | VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) |
| 168 | 1: |
| 169 | #endif |
| 170 | VFPFMXR FPSCR, r5 @ restore status |
| 171 | |
| 172 | @ The context stored in the VFP hardware is up to date with this thread |
| 173 | vfp_hw_state_valid: |
| 174 | tst r1, #FPEXC_EX |
| 175 | bne process_exception @ might as well handle the pending |
| 176 | @ exception before retrying branch |
| 177 | @ out before setting an FPEXC that |
| 178 | @ stops us reading stuff |
| 179 | VFPFMXR FPEXC, r1 @ Restore FPEXC last |
| 180 | sub r2, r2, #4 @ Retry current instruction - if Thumb |
| 181 | str r2, [sp, #S_PC] @ mode it's two 16-bit instructions, |
| 182 | @ else it's one 32-bit instruction, so |
| 183 | @ always subtract 4 from the following |
| 184 | @ instruction address. |
| 185 | #ifdef CONFIG_PREEMPT_COUNT |
| 186 | get_thread_info r10 |
| 187 | ldr r4, [r10, #TI_PREEMPT] @ get preempt count |
| 188 | sub r11, r4, #1 @ decrement it |
| 189 | str r11, [r10, #TI_PREEMPT] |
| 190 | #endif |
| 191 | mov pc, r9 @ we think we have handled things |
| 192 | |
| 193 | |
| 194 | look_for_VFP_exceptions: |
| 195 | @ Check for synchronous or asynchronous exception |
| 196 | tst r1, #FPEXC_EX | FPEXC_DEX |
| 197 | bne process_exception |
| 198 | @ On some implementations of the VFP subarch 1, setting FPSCR.IXE |
| 199 | @ causes all the CDP instructions to be bounced synchronously without |
| 200 | @ setting the FPEXC.EX bit |
| 201 | VFPFMRX r5, FPSCR |
| 202 | tst r5, #FPSCR_IXE |
| 203 | bne process_exception |
| 204 | |
| 205 | @ Fall into hand on to next handler - appropriate coproc instr |
| 206 | @ not recognised by VFP |
| 207 | |
| 208 | DBGSTR "not VFP" |
| 209 | #ifdef CONFIG_PREEMPT_COUNT |
| 210 | get_thread_info r10 |
| 211 | ldr r4, [r10, #TI_PREEMPT] @ get preempt count |
| 212 | sub r11, r4, #1 @ decrement it |
| 213 | str r11, [r10, #TI_PREEMPT] |
| 214 | #endif |
| 215 | mov pc, lr |
| 216 | |
| 217 | process_exception: |
| 218 | DBGSTR "bounce" |
| 219 | mov r2, sp @ nothing stacked - regdump is at TOS |
| 220 | mov lr, r9 @ setup for a return to the user code. |
| 221 | |
| 222 | @ Now call the C code to package up the bounce to the support code |
| 223 | @ r0 holds the trigger instruction |
| 224 | @ r1 holds the FPEXC value |
| 225 | @ r2 pointer to register dump |
| 226 | b VFP_bounce @ we have handled this - the support |
| 227 | @ code will raise an exception if |
| 228 | @ required. If not, the user code will |
| 229 | @ retry the faulted instruction |
| 230 | ENDPROC(vfp_support_entry) |
| 231 | |
| 232 | ENTRY(vfp_save_state) |
| 233 | @ Save the current VFP state |
| 234 | @ r0 - save location |
| 235 | @ r1 - FPEXC |
| 236 | DBGSTR1 "save VFP state %p", r0 |
| 237 | VFPFSTMIA r0, r2 @ save the working registers |
| 238 | VFPFMRX r2, FPSCR @ current status |
| 239 | tst r1, #FPEXC_EX @ is there additional state to save? |
| 240 | beq 1f |
| 241 | VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) |
| 242 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? |
| 243 | beq 1f |
| 244 | VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) |
| 245 | 1: |
| 246 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 |
| 247 | mov pc, lr |
| 248 | ENDPROC(vfp_save_state) |
| 249 | |
| 250 | .align |
| 251 | vfp_current_hw_state_address: |
| 252 | .word vfp_current_hw_state |
| 253 | |
| 254 | .macro tbl_branch, base, tmp, shift |
| 255 | #ifdef CONFIG_THUMB2_KERNEL |
| 256 | adr \tmp, 1f |
| 257 | add \tmp, \tmp, \base, lsl \shift |
| 258 | mov pc, \tmp |
| 259 | #else |
| 260 | add pc, pc, \base, lsl \shift |
| 261 | mov r0, r0 |
| 262 | #endif |
| 263 | 1: |
| 264 | .endm |
| 265 | |
| 266 | ENTRY(vfp_get_float) |
| 267 | tbl_branch r0, r3, #3 |
| 268 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 269 | 1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 |
| 270 | mov pc, lr |
| 271 | .org 1b + 8 |
| 272 | 1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 |
| 273 | mov pc, lr |
| 274 | .org 1b + 8 |
| 275 | .endr |
| 276 | ENDPROC(vfp_get_float) |
| 277 | |
| 278 | ENTRY(vfp_put_float) |
| 279 | tbl_branch r1, r3, #3 |
| 280 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 281 | 1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 |
| 282 | mov pc, lr |
| 283 | .org 1b + 8 |
| 284 | 1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 |
| 285 | mov pc, lr |
| 286 | .org 1b + 8 |
| 287 | .endr |
| 288 | ENDPROC(vfp_put_float) |
| 289 | |
| 290 | ENTRY(vfp_get_double) |
| 291 | tbl_branch r0, r3, #3 |
| 292 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 293 | 1: fmrrd r0, r1, d\dr |
| 294 | mov pc, lr |
| 295 | .org 1b + 8 |
| 296 | .endr |
| 297 | #ifdef CONFIG_VFPv3 |
| 298 | @ d16 - d31 registers |
| 299 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 300 | 1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr |
| 301 | mov pc, lr |
| 302 | .org 1b + 8 |
| 303 | .endr |
| 304 | #endif |
| 305 | |
| 306 | @ virtual register 16 (or 32 if VFPv3) for compare with zero |
| 307 | mov r0, #0 |
| 308 | mov r1, #0 |
| 309 | mov pc, lr |
| 310 | ENDPROC(vfp_get_double) |
| 311 | |
| 312 | ENTRY(vfp_put_double) |
| 313 | tbl_branch r2, r3, #3 |
| 314 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 315 | 1: fmdrr d\dr, r0, r1 |
| 316 | mov pc, lr |
| 317 | .org 1b + 8 |
| 318 | .endr |
| 319 | #ifdef CONFIG_VFPv3 |
| 320 | @ d16 - d31 registers |
| 321 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| 322 | 1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr |
| 323 | mov pc, lr |
| 324 | .org 1b + 8 |
| 325 | .endr |
| 326 | #endif |
| 327 | ENDPROC(vfp_put_double) |