[deliverable/linux.git] / arch / blackfin / mach-bf537 / include / mach / anomaly.h

/*
 * File: include/asm-blackfin/mach-bf537/anomaly.h
 * Bugs: Enter bugs at http://blackfin.uclinux.org/
 *
 * Copyright (C) 2004-2009 Analog Devices Inc.
 * Licensed under the GPL-2 or later.
 */

/* This file should be up to date with:
 *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
 */

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

/* We do not support 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
# error will not work on BF537 silicon version 0.0 or 0.1
#endif

#if defined(__ADSPBF534__)
# define ANOMALY_BF534 1
#else
# define ANOMALY_BF534 0
#endif
#if defined(__ADSPBF536__)
# define ANOMALY_BF536 1
#else
# define ANOMALY_BF536 0
#endif
#if defined(__ADSPBF537__)
# define ANOMALY_BF537 1
#else
# define ANOMALY_BF537 0
#endif

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Buffered CLKIN Output Is Disabled by Default */
#define ANOMALY_05000247 (1)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC TX DMA Error After an Early Frame Abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
/* EMAC MDIO Input Latched on Wrong MDC Edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
/* ICPLB_STATUS MMR Register May Be Corrupted */
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* Stores To Data Cache May Be Lost */
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
#define ANOMALY_05000280 (1)
/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* UART Gets Disabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000359 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)

/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)

#endif
Commit	Line	Data
	1	/*
	2	* File: include/asm-blackfin/mach-bf537/anomaly.h
	3	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	4	*
	5	* Copyright (C) 2004-2009 Analog Devices Inc.
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	/* This file should be up to date with:
	10	* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
	11	*/
	12
	13	#ifndef _MACH_ANOMALY_H_
	14	#define _MACH_ANOMALY_H_
	15
	16	/* We do not support 0.1 silicon - sorry */
	17	#if __SILICON_REVISION__ < 2
	18	# error will not work on BF537 silicon version 0.0 or 0.1
	19	#endif
	20
	21	#if defined(__ADSPBF534__)
	22	# define ANOMALY_BF534 1
	23	#else
	24	# define ANOMALY_BF534 0
	25	#endif
	26	#if defined(__ADSPBF536__)
	27	# define ANOMALY_BF536 1
	28	#else
	29	# define ANOMALY_BF536 0
	30	#endif
	31	#if defined(__ADSPBF537__)
	32	# define ANOMALY_BF537 1
	33	#else
	34	# define ANOMALY_BF537 0
	35	#endif
	36
	37	/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
	38	#define ANOMALY_05000074 (1)
	39	/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
	40	#define ANOMALY_05000119 (1)
	41	/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
	42	#define ANOMALY_05000122 (1)
	43	/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
	44	#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
	45	/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
	46	#define ANOMALY_05000180 (1)
	47	/* Instruction Cache Is Not Functional */
	48	#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
	49	/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
	50	#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
	51	/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
	52	#define ANOMALY_05000245 (1)
	53	/* Buffered CLKIN Output Is Disabled by Default */
	54	#define ANOMALY_05000247 (1)
	55	/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
	56	#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
	57	/* EMAC TX DMA Error After an Early Frame Abort */
	58	#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
	59	/* Maximum External Clock Speed for Timers */
	60	#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
	61	/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
	62	#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
	63	/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
	64	#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
	65	/* EMAC MDIO Input Latched on Wrong MDC Edge */
	66	#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
	67	/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
	68	#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
	69	/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
	70	#define ANOMALY_05000258 (((ANOMALY_BF536 \|\| ANOMALY_BF537) && __SILICON_REVISION__ == 1) \|\| __SILICON_REVISION__ == 2)
	71	/* ICPLB_STATUS MMR Register May Be Corrupted */
	72	#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
	73	/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
	74	#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
	75	/* Stores To Data Cache May Be Lost */
	76	#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
	77	/* Hardware Loop Corrupted When Taking an ICPLB Exception */
	78	#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
	79	/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
	80	#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
	81	/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
	82	#define ANOMALY_05000265 (1)
	83	/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
	84	#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
	85	/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
	86	#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
	87	/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
	88	#define ANOMALY_05000272 (1)
	89	/* Writes to Synchronous SDRAM Memory May Be Lost */
	90	#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
	91	/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
	92	#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
	93	/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
	94	#define ANOMALY_05000278 (((ANOMALY_BF536 \|\| ANOMALY_BF537) && __SILICON_REVISION__ < 3) \|\| (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
	95	/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
	96	#define ANOMALY_05000280 (1)
	97	/* False Hardware Error Exception when ISR Context Is Not Restored */
	98	#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
	99	/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
	100	#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
	101	/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
	102	#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
	103	/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
	104	#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
	105	/* SPORTs May Receive Bad Data If FIFOs Fill Up */
	106	#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
	107	/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
	108	#define ANOMALY_05000301 (1)
	109	/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
	110	#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
	111	/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
	112	#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
	113	/* SCKELOW Bit Does Not Maintain State Through Hibernate */
	114	#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
	115	/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
	116	#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
	117	/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
	118	#define ANOMALY_05000310 (1)
	119	/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
	120	#define ANOMALY_05000312 (1)
	121	/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
	122	#define ANOMALY_05000313 (1)
	123	/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
	124	#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
	125	/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
	126	#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
	127	/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
	128	#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
	129	/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
	130	#define ANOMALY_05000322 (1)
	131	/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
	132	#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
	133	/* UART Gets Disabled after UART Boot */
	134	#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
	135	/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
	136	#define ANOMALY_05000355 (1)
	137	/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
	138	#define ANOMALY_05000357 (1)
	139	/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
	140	#define ANOMALY_05000359 (1)
	141	/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
	142	#define ANOMALY_05000366 (1)
	143	/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
	144	#define ANOMALY_05000371 (1)
	145	/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
	146	#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
	147	/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
	148	#define ANOMALY_05000403 (1)
	149	/* Speculative Fetches Can Cause Undesired External FIFO Operations */
	150	#define ANOMALY_05000416 (1)
	151	/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
	152	#define ANOMALY_05000425 (1)
	153	/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
	154	#define ANOMALY_05000426 (1)
	155	/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
	156	#define ANOMALY_05000443 (1)
	157	/* False Hardware Error when RETI Points to Invalid Memory */
	158	#define ANOMALY_05000461 (1)
	159
	160	/* Anomalies that don't exist on this proc */
	161	#define ANOMALY_05000099 (0)
	162	#define ANOMALY_05000120 (0)
	163	#define ANOMALY_05000125 (0)
	164	#define ANOMALY_05000149 (0)
	165	#define ANOMALY_05000158 (0)
	166	#define ANOMALY_05000171 (0)
	167	#define ANOMALY_05000179 (0)
	168	#define ANOMALY_05000182 (0)
	169	#define ANOMALY_05000183 (0)
	170	#define ANOMALY_05000189 (0)
	171	#define ANOMALY_05000198 (0)
	172	#define ANOMALY_05000202 (0)
	173	#define ANOMALY_05000215 (0)
	174	#define ANOMALY_05000220 (0)
	175	#define ANOMALY_05000227 (0)
	176	#define ANOMALY_05000230 (0)
	177	#define ANOMALY_05000231 (0)
	178	#define ANOMALY_05000233 (0)
	179	#define ANOMALY_05000234 (0)
	180	#define ANOMALY_05000242 (0)
	181	#define ANOMALY_05000248 (0)
	182	#define ANOMALY_05000266 (0)
	183	#define ANOMALY_05000274 (0)
	184	#define ANOMALY_05000287 (0)
	185	#define ANOMALY_05000311 (0)
	186	#define ANOMALY_05000323 (0)
	187	#define ANOMALY_05000353 (1)
	188	#define ANOMALY_05000362 (1)
	189	#define ANOMALY_05000363 (0)
	190	#define ANOMALY_05000364 (0)
	191	#define ANOMALY_05000380 (0)
	192	#define ANOMALY_05000386 (1)
	193	#define ANOMALY_05000389 (0)
	194	#define ANOMALY_05000400 (0)
	195	#define ANOMALY_05000412 (0)
	196	#define ANOMALY_05000430 (0)
	197	#define ANOMALY_05000432 (0)
	198	#define ANOMALY_05000435 (0)
	199	#define ANOMALY_05000447 (0)
	200	#define ANOMALY_05000448 (0)
	201	#define ANOMALY_05000456 (0)
	202	#define ANOMALY_05000450 (0)
	203	#define ANOMALY_05000465 (0)
	204	#define ANOMALY_05000467 (0)
	205
	206	#endif