| 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
| 4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> |
| 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/config.h> |
| 18 | #include <linux/init.h> |
| 19 | |
| 20 | #include <linux/mm.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/bootmem.h> |
| 23 | #include <linux/smp_lock.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/mc146818rtc.h> |
| 26 | #include <linux/kernel_stat.h> |
| 27 | #include <linux/sysdev.h> |
| 28 | #include <linux/cpu.h> |
| 29 | #include <linux/module.h> |
| 30 | |
| 31 | #include <asm/atomic.h> |
| 32 | #include <asm/smp.h> |
| 33 | #include <asm/mtrr.h> |
| 34 | #include <asm/mpspec.h> |
| 35 | #include <asm/desc.h> |
| 36 | #include <asm/arch_hooks.h> |
| 37 | #include <asm/hpet.h> |
| 38 | #include <asm/i8253.h> |
| 39 | |
| 40 | #include <mach_apic.h> |
| 41 | #include <mach_apicdef.h> |
| 42 | #include <mach_ipi.h> |
| 43 | |
| 44 | #include "io_ports.h" |
| 45 | |
| 46 | /* |
| 47 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as |
| 48 | * IPIs in place of local APIC timers |
| 49 | */ |
| 50 | static cpumask_t timer_bcast_ipi; |
| 51 | |
| 52 | /* |
| 53 | * Knob to control our willingness to enable the local APIC. |
| 54 | */ |
| 55 | int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */ |
| 56 | |
| 57 | /* |
| 58 | * Debug level |
| 59 | */ |
| 60 | int apic_verbosity; |
| 61 | |
| 62 | |
| 63 | static void apic_pm_activate(void); |
| 64 | |
| 65 | int modern_apic(void) |
| 66 | { |
| 67 | unsigned int lvr, version; |
| 68 | /* AMD systems use old APIC versions, so check the CPU */ |
| 69 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 70 | boot_cpu_data.x86 >= 0xf) |
| 71 | return 1; |
| 72 | lvr = apic_read(APIC_LVR); |
| 73 | version = GET_APIC_VERSION(lvr); |
| 74 | return version >= 0x14; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * 'what should we do if we get a hw irq event on an illegal vector'. |
| 79 | * each architecture has to answer this themselves. |
| 80 | */ |
| 81 | void ack_bad_irq(unsigned int irq) |
| 82 | { |
| 83 | printk("unexpected IRQ trap at vector %02x\n", irq); |
| 84 | /* |
| 85 | * Currently unexpected vectors happen only on SMP and APIC. |
| 86 | * We _must_ ack these because every local APIC has only N |
| 87 | * irq slots per priority level, and a 'hanging, unacked' IRQ |
| 88 | * holds up an irq slot - in excessive cases (when multiple |
| 89 | * unexpected vectors occur) that might lock up the APIC |
| 90 | * completely. |
| 91 | * But only ack when the APIC is enabled -AK |
| 92 | */ |
| 93 | if (cpu_has_apic) |
| 94 | ack_APIC_irq(); |
| 95 | } |
| 96 | |
| 97 | void __init apic_intr_init(void) |
| 98 | { |
| 99 | #ifdef CONFIG_SMP |
| 100 | smp_intr_init(); |
| 101 | #endif |
| 102 | /* self generated IPI for local APIC timer */ |
| 103 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
| 104 | |
| 105 | /* IPI vectors for APIC spurious and error interrupts */ |
| 106 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
| 107 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); |
| 108 | |
| 109 | /* thermal monitor LVT interrupt */ |
| 110 | #ifdef CONFIG_X86_MCE_P4THERMAL |
| 111 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
| 112 | #endif |
| 113 | } |
| 114 | |
| 115 | /* Using APIC to generate smp_local_timer_interrupt? */ |
| 116 | int using_apic_timer = 0; |
| 117 | |
| 118 | static int enabled_via_apicbase; |
| 119 | |
| 120 | void enable_NMI_through_LVT0 (void * dummy) |
| 121 | { |
| 122 | unsigned int v, ver; |
| 123 | |
| 124 | ver = apic_read(APIC_LVR); |
| 125 | ver = GET_APIC_VERSION(ver); |
| 126 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
| 127 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ |
| 128 | v |= APIC_LVT_LEVEL_TRIGGER; |
| 129 | apic_write_around(APIC_LVT0, v); |
| 130 | } |
| 131 | |
| 132 | int get_physical_broadcast(void) |
| 133 | { |
| 134 | if (modern_apic()) |
| 135 | return 0xff; |
| 136 | else |
| 137 | return 0xf; |
| 138 | } |
| 139 | |
| 140 | int get_maxlvt(void) |
| 141 | { |
| 142 | unsigned int v, ver, maxlvt; |
| 143 | |
| 144 | v = apic_read(APIC_LVR); |
| 145 | ver = GET_APIC_VERSION(v); |
| 146 | /* 82489DXs do not report # of LVT entries. */ |
| 147 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; |
| 148 | return maxlvt; |
| 149 | } |
| 150 | |
| 151 | void clear_local_APIC(void) |
| 152 | { |
| 153 | int maxlvt; |
| 154 | unsigned long v; |
| 155 | |
| 156 | maxlvt = get_maxlvt(); |
| 157 | |
| 158 | /* |
| 159 | * Masking an LVT entry on a P6 can trigger a local APIC error |
| 160 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 161 | */ |
| 162 | if (maxlvt >= 3) { |
| 163 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
| 164 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); |
| 165 | } |
| 166 | /* |
| 167 | * Careful: we have to set masks only first to deassert |
| 168 | * any level-triggered sources. |
| 169 | */ |
| 170 | v = apic_read(APIC_LVTT); |
| 171 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); |
| 172 | v = apic_read(APIC_LVT0); |
| 173 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); |
| 174 | v = apic_read(APIC_LVT1); |
| 175 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); |
| 176 | if (maxlvt >= 4) { |
| 177 | v = apic_read(APIC_LVTPC); |
| 178 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); |
| 179 | } |
| 180 | |
| 181 | /* lets not touch this if we didn't frob it */ |
| 182 | #ifdef CONFIG_X86_MCE_P4THERMAL |
| 183 | if (maxlvt >= 5) { |
| 184 | v = apic_read(APIC_LVTTHMR); |
| 185 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
| 186 | } |
| 187 | #endif |
| 188 | /* |
| 189 | * Clean APIC state for other OSs: |
| 190 | */ |
| 191 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
| 192 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); |
| 193 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); |
| 194 | if (maxlvt >= 3) |
| 195 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); |
| 196 | if (maxlvt >= 4) |
| 197 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); |
| 198 | |
| 199 | #ifdef CONFIG_X86_MCE_P4THERMAL |
| 200 | if (maxlvt >= 5) |
| 201 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); |
| 202 | #endif |
| 203 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 204 | if (APIC_INTEGRATED(v)) { /* !82489DX */ |
| 205 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ |
| 206 | apic_write(APIC_ESR, 0); |
| 207 | apic_read(APIC_ESR); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | void __init connect_bsp_APIC(void) |
| 212 | { |
| 213 | if (pic_mode) { |
| 214 | /* |
| 215 | * Do not trust the local APIC being empty at bootup. |
| 216 | */ |
| 217 | clear_local_APIC(); |
| 218 | /* |
| 219 | * PIC mode, enable APIC mode in the IMCR, i.e. |
| 220 | * connect BSP's local APIC to INT and NMI lines. |
| 221 | */ |
| 222 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " |
| 223 | "enabling APIC mode.\n"); |
| 224 | outb(0x70, 0x22); |
| 225 | outb(0x01, 0x23); |
| 226 | } |
| 227 | enable_apic_mode(); |
| 228 | } |
| 229 | |
| 230 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 231 | { |
| 232 | if (pic_mode) { |
| 233 | /* |
| 234 | * Put the board back into PIC mode (has an effect |
| 235 | * only on certain older boards). Note that APIC |
| 236 | * interrupts, including IPIs, won't work beyond |
| 237 | * this point! The only exception are INIT IPIs. |
| 238 | */ |
| 239 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " |
| 240 | "entering PIC mode.\n"); |
| 241 | outb(0x70, 0x22); |
| 242 | outb(0x00, 0x23); |
| 243 | } |
| 244 | else { |
| 245 | /* Go back to Virtual Wire compatibility mode */ |
| 246 | unsigned long value; |
| 247 | |
| 248 | /* For the spurious interrupt use vector F, and enable it */ |
| 249 | value = apic_read(APIC_SPIV); |
| 250 | value &= ~APIC_VECTOR_MASK; |
| 251 | value |= APIC_SPIV_APIC_ENABLED; |
| 252 | value |= 0xf; |
| 253 | apic_write_around(APIC_SPIV, value); |
| 254 | |
| 255 | if (!virt_wire_setup) { |
| 256 | /* For LVT0 make it edge triggered, active high, external and enabled */ |
| 257 | value = apic_read(APIC_LVT0); |
| 258 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 259 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 260 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
| 261 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 262 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 263 | apic_write_around(APIC_LVT0, value); |
| 264 | } |
| 265 | else { |
| 266 | /* Disable LVT0 */ |
| 267 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); |
| 268 | } |
| 269 | |
| 270 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
| 271 | value = apic_read(APIC_LVT1); |
| 272 | value &= ~( |
| 273 | APIC_MODE_MASK | APIC_SEND_PENDING | |
| 274 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 275 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 276 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 277 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 278 | apic_write_around(APIC_LVT1, value); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | void disable_local_APIC(void) |
| 283 | { |
| 284 | unsigned long value; |
| 285 | |
| 286 | clear_local_APIC(); |
| 287 | |
| 288 | /* |
| 289 | * Disable APIC (implies clearing of registers |
| 290 | * for 82489DX!). |
| 291 | */ |
| 292 | value = apic_read(APIC_SPIV); |
| 293 | value &= ~APIC_SPIV_APIC_ENABLED; |
| 294 | apic_write_around(APIC_SPIV, value); |
| 295 | |
| 296 | if (enabled_via_apicbase) { |
| 297 | unsigned int l, h; |
| 298 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 299 | l &= ~MSR_IA32_APICBASE_ENABLE; |
| 300 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 301 | } |
| 302 | } |
| 303 | |
| 304 | /* |
| 305 | * This is to verify that we're looking at a real local APIC. |
| 306 | * Check these against your board if the CPUs aren't getting |
| 307 | * started for no apparent reason. |
| 308 | */ |
| 309 | int __init verify_local_APIC(void) |
| 310 | { |
| 311 | unsigned int reg0, reg1; |
| 312 | |
| 313 | /* |
| 314 | * The version register is read-only in a real APIC. |
| 315 | */ |
| 316 | reg0 = apic_read(APIC_LVR); |
| 317 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); |
| 318 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); |
| 319 | reg1 = apic_read(APIC_LVR); |
| 320 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); |
| 321 | |
| 322 | /* |
| 323 | * The two version reads above should print the same |
| 324 | * numbers. If the second one is different, then we |
| 325 | * poke at a non-APIC. |
| 326 | */ |
| 327 | if (reg1 != reg0) |
| 328 | return 0; |
| 329 | |
| 330 | /* |
| 331 | * Check if the version looks reasonably. |
| 332 | */ |
| 333 | reg1 = GET_APIC_VERSION(reg0); |
| 334 | if (reg1 == 0x00 || reg1 == 0xff) |
| 335 | return 0; |
| 336 | reg1 = get_maxlvt(); |
| 337 | if (reg1 < 0x02 || reg1 == 0xff) |
| 338 | return 0; |
| 339 | |
| 340 | /* |
| 341 | * The ID register is read/write in a real APIC. |
| 342 | */ |
| 343 | reg0 = apic_read(APIC_ID); |
| 344 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
| 345 | |
| 346 | /* |
| 347 | * The next two are just to see if we have sane values. |
| 348 | * They're only really relevant if we're in Virtual Wire |
| 349 | * compatibility mode, but most boxes are anymore. |
| 350 | */ |
| 351 | reg0 = apic_read(APIC_LVT0); |
| 352 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
| 353 | reg1 = apic_read(APIC_LVT1); |
| 354 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); |
| 355 | |
| 356 | return 1; |
| 357 | } |
| 358 | |
| 359 | void __init sync_Arb_IDs(void) |
| 360 | { |
| 361 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 |
| 362 | And not needed on AMD */ |
| 363 | if (modern_apic()) |
| 364 | return; |
| 365 | /* |
| 366 | * Wait for idle. |
| 367 | */ |
| 368 | apic_wait_icr_idle(); |
| 369 | |
| 370 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
| 371 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
| 372 | | APIC_DM_INIT); |
| 373 | } |
| 374 | |
| 375 | extern void __error_in_apic_c (void); |
| 376 | |
| 377 | /* |
| 378 | * An initial setup of the virtual wire mode. |
| 379 | */ |
| 380 | void __init init_bsp_APIC(void) |
| 381 | { |
| 382 | unsigned long value, ver; |
| 383 | |
| 384 | /* |
| 385 | * Don't do the setup now if we have a SMP BIOS as the |
| 386 | * through-I/O-APIC virtual wire mode might be active. |
| 387 | */ |
| 388 | if (smp_found_config || !cpu_has_apic) |
| 389 | return; |
| 390 | |
| 391 | value = apic_read(APIC_LVR); |
| 392 | ver = GET_APIC_VERSION(value); |
| 393 | |
| 394 | /* |
| 395 | * Do not trust the local APIC being empty at bootup. |
| 396 | */ |
| 397 | clear_local_APIC(); |
| 398 | |
| 399 | /* |
| 400 | * Enable APIC. |
| 401 | */ |
| 402 | value = apic_read(APIC_SPIV); |
| 403 | value &= ~APIC_VECTOR_MASK; |
| 404 | value |= APIC_SPIV_APIC_ENABLED; |
| 405 | |
| 406 | /* This bit is reserved on P4/Xeon and should be cleared */ |
| 407 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15)) |
| 408 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 409 | else |
| 410 | value |= APIC_SPIV_FOCUS_DISABLED; |
| 411 | value |= SPURIOUS_APIC_VECTOR; |
| 412 | apic_write_around(APIC_SPIV, value); |
| 413 | |
| 414 | /* |
| 415 | * Set up the virtual wire mode. |
| 416 | */ |
| 417 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); |
| 418 | value = APIC_DM_NMI; |
| 419 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ |
| 420 | value |= APIC_LVT_LEVEL_TRIGGER; |
| 421 | apic_write_around(APIC_LVT1, value); |
| 422 | } |
| 423 | |
| 424 | void __devinit setup_local_APIC(void) |
| 425 | { |
| 426 | unsigned long oldvalue, value, ver, maxlvt; |
| 427 | int i, j; |
| 428 | |
| 429 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
| 430 | if (esr_disable) { |
| 431 | apic_write(APIC_ESR, 0); |
| 432 | apic_write(APIC_ESR, 0); |
| 433 | apic_write(APIC_ESR, 0); |
| 434 | apic_write(APIC_ESR, 0); |
| 435 | } |
| 436 | |
| 437 | value = apic_read(APIC_LVR); |
| 438 | ver = GET_APIC_VERSION(value); |
| 439 | |
| 440 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) |
| 441 | __error_in_apic_c(); |
| 442 | |
| 443 | /* |
| 444 | * Double-check whether this APIC is really registered. |
| 445 | */ |
| 446 | if (!apic_id_registered()) |
| 447 | BUG(); |
| 448 | |
| 449 | /* |
| 450 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 451 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 452 | * document number 292116). So here it goes... |
| 453 | */ |
| 454 | init_apic_ldr(); |
| 455 | |
| 456 | /* |
| 457 | * Set Task Priority to 'accept all'. We never change this |
| 458 | * later on. |
| 459 | */ |
| 460 | value = apic_read(APIC_TASKPRI); |
| 461 | value &= ~APIC_TPRI_MASK; |
| 462 | apic_write_around(APIC_TASKPRI, value); |
| 463 | |
| 464 | /* |
| 465 | * After a crash, we no longer service the interrupts and a pending |
| 466 | * interrupt from previous kernel might still have ISR bit set. |
| 467 | * |
| 468 | * Most probably by now CPU has serviced that pending interrupt and |
| 469 | * it might not have done the ack_APIC_irq() because it thought, |
| 470 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 471 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 472 | * the interrupt. Hence a vector might get locked. It was noticed |
| 473 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 474 | */ |
| 475 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 476 | value = apic_read(APIC_ISR + i*0x10); |
| 477 | for (j = 31; j >= 0; j--) { |
| 478 | if (value & (1<<j)) |
| 479 | ack_APIC_irq(); |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | /* |
| 484 | * Now that we are all set up, enable the APIC |
| 485 | */ |
| 486 | value = apic_read(APIC_SPIV); |
| 487 | value &= ~APIC_VECTOR_MASK; |
| 488 | /* |
| 489 | * Enable APIC |
| 490 | */ |
| 491 | value |= APIC_SPIV_APIC_ENABLED; |
| 492 | |
| 493 | /* |
| 494 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 495 | * certain networking cards. If high frequency interrupts are |
| 496 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 497 | * entry is masked/unmasked at a high rate as well then sooner or |
| 498 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 499 | * from the device. If focus CPU is disabled then the hang goes |
| 500 | * away, oh well :-( |
| 501 | * |
| 502 | * [ This bug can be reproduced easily with a level-triggered |
| 503 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 504 | * BX chipset. ] |
| 505 | */ |
| 506 | /* |
| 507 | * Actually disabling the focus CPU check just makes the hang less |
| 508 | * frequent as it makes the interrupt distributon model be more |
| 509 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 510 | * See also the comment in end_level_ioapic_irq(). --macro |
| 511 | */ |
| 512 | #if 1 |
| 513 | /* Enable focus processor (bit==0) */ |
| 514 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 515 | #else |
| 516 | /* Disable focus processor (bit==1) */ |
| 517 | value |= APIC_SPIV_FOCUS_DISABLED; |
| 518 | #endif |
| 519 | /* |
| 520 | * Set spurious IRQ vector |
| 521 | */ |
| 522 | value |= SPURIOUS_APIC_VECTOR; |
| 523 | apic_write_around(APIC_SPIV, value); |
| 524 | |
| 525 | /* |
| 526 | * Set up LVT0, LVT1: |
| 527 | * |
| 528 | * set up through-local-APIC on the BP's LINT0. This is not |
| 529 | * strictly necessery in pure symmetric-IO mode, but sometimes |
| 530 | * we delegate interrupts to the 8259A. |
| 531 | */ |
| 532 | /* |
| 533 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 534 | */ |
| 535 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
| 536 | if (!smp_processor_id() && (pic_mode || !value)) { |
| 537 | value = APIC_DM_EXTINT; |
| 538 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
| 539 | smp_processor_id()); |
| 540 | } else { |
| 541 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
| 542 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
| 543 | smp_processor_id()); |
| 544 | } |
| 545 | apic_write_around(APIC_LVT0, value); |
| 546 | |
| 547 | /* |
| 548 | * only the BP should see the LINT1 NMI signal, obviously. |
| 549 | */ |
| 550 | if (!smp_processor_id()) |
| 551 | value = APIC_DM_NMI; |
| 552 | else |
| 553 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
| 554 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ |
| 555 | value |= APIC_LVT_LEVEL_TRIGGER; |
| 556 | apic_write_around(APIC_LVT1, value); |
| 557 | |
| 558 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ |
| 559 | maxlvt = get_maxlvt(); |
| 560 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 561 | apic_write(APIC_ESR, 0); |
| 562 | oldvalue = apic_read(APIC_ESR); |
| 563 | |
| 564 | value = ERROR_APIC_VECTOR; // enables sending errors |
| 565 | apic_write_around(APIC_LVTERR, value); |
| 566 | /* |
| 567 | * spec says clear errors after enabling vector. |
| 568 | */ |
| 569 | if (maxlvt > 3) |
| 570 | apic_write(APIC_ESR, 0); |
| 571 | value = apic_read(APIC_ESR); |
| 572 | if (value != oldvalue) |
| 573 | apic_printk(APIC_VERBOSE, "ESR value before enabling " |
| 574 | "vector: 0x%08lx after: 0x%08lx\n", |
| 575 | oldvalue, value); |
| 576 | } else { |
| 577 | if (esr_disable) |
| 578 | /* |
| 579 | * Something untraceble is creating bad interrupts on |
| 580 | * secondary quads ... for the moment, just leave the |
| 581 | * ESR disabled - we can't do anything useful with the |
| 582 | * errors anyway - mbligh |
| 583 | */ |
| 584 | printk("Leaving ESR disabled.\n"); |
| 585 | else |
| 586 | printk("No ESR for 82489DX.\n"); |
| 587 | } |
| 588 | |
| 589 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 590 | setup_apic_nmi_watchdog(); |
| 591 | apic_pm_activate(); |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * If Linux enabled the LAPIC against the BIOS default |
| 596 | * disable it down before re-entering the BIOS on shutdown. |
| 597 | * Otherwise the BIOS may get confused and not power-off. |
| 598 | * Additionally clear all LVT entries before disable_local_APIC |
| 599 | * for the case where Linux didn't enable the LAPIC. |
| 600 | */ |
| 601 | void lapic_shutdown(void) |
| 602 | { |
| 603 | unsigned long flags; |
| 604 | |
| 605 | if (!cpu_has_apic) |
| 606 | return; |
| 607 | |
| 608 | local_irq_save(flags); |
| 609 | clear_local_APIC(); |
| 610 | |
| 611 | if (enabled_via_apicbase) |
| 612 | disable_local_APIC(); |
| 613 | |
| 614 | local_irq_restore(flags); |
| 615 | } |
| 616 | |
| 617 | #ifdef CONFIG_PM |
| 618 | |
| 619 | static struct { |
| 620 | int active; |
| 621 | /* r/w apic fields */ |
| 622 | unsigned int apic_id; |
| 623 | unsigned int apic_taskpri; |
| 624 | unsigned int apic_ldr; |
| 625 | unsigned int apic_dfr; |
| 626 | unsigned int apic_spiv; |
| 627 | unsigned int apic_lvtt; |
| 628 | unsigned int apic_lvtpc; |
| 629 | unsigned int apic_lvt0; |
| 630 | unsigned int apic_lvt1; |
| 631 | unsigned int apic_lvterr; |
| 632 | unsigned int apic_tmict; |
| 633 | unsigned int apic_tdcr; |
| 634 | unsigned int apic_thmr; |
| 635 | } apic_pm_state; |
| 636 | |
| 637 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
| 638 | { |
| 639 | unsigned long flags; |
| 640 | |
| 641 | if (!apic_pm_state.active) |
| 642 | return 0; |
| 643 | |
| 644 | apic_pm_state.apic_id = apic_read(APIC_ID); |
| 645 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 646 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 647 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 648 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 649 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
| 650 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
| 651 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 652 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 653 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 654 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 655 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
| 656 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 657 | |
| 658 | local_irq_save(flags); |
| 659 | disable_local_APIC(); |
| 660 | local_irq_restore(flags); |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | static int lapic_resume(struct sys_device *dev) |
| 665 | { |
| 666 | unsigned int l, h; |
| 667 | unsigned long flags; |
| 668 | |
| 669 | if (!apic_pm_state.active) |
| 670 | return 0; |
| 671 | |
| 672 | local_irq_save(flags); |
| 673 | |
| 674 | /* |
| 675 | * Make sure the APICBASE points to the right address |
| 676 | * |
| 677 | * FIXME! This will be wrong if we ever support suspend on |
| 678 | * SMP! We'll need to do this as part of the CPU restore! |
| 679 | */ |
| 680 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 681 | l &= ~MSR_IA32_APICBASE_BASE; |
| 682 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 683 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 684 | |
| 685 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 686 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 687 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 688 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 689 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 690 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 691 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 692 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
| 693 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 694 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
| 695 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 696 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 697 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 698 | apic_write(APIC_ESR, 0); |
| 699 | apic_read(APIC_ESR); |
| 700 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 701 | apic_write(APIC_ESR, 0); |
| 702 | apic_read(APIC_ESR); |
| 703 | local_irq_restore(flags); |
| 704 | return 0; |
| 705 | } |
| 706 | |
| 707 | /* |
| 708 | * This device has no shutdown method - fully functioning local APICs |
| 709 | * are needed on every CPU up until machine_halt/restart/poweroff. |
| 710 | */ |
| 711 | |
| 712 | static struct sysdev_class lapic_sysclass = { |
| 713 | set_kset_name("lapic"), |
| 714 | .resume = lapic_resume, |
| 715 | .suspend = lapic_suspend, |
| 716 | }; |
| 717 | |
| 718 | static struct sys_device device_lapic = { |
| 719 | .id = 0, |
| 720 | .cls = &lapic_sysclass, |
| 721 | }; |
| 722 | |
| 723 | static void __devinit apic_pm_activate(void) |
| 724 | { |
| 725 | apic_pm_state.active = 1; |
| 726 | } |
| 727 | |
| 728 | static int __init init_lapic_sysfs(void) |
| 729 | { |
| 730 | int error; |
| 731 | |
| 732 | if (!cpu_has_apic) |
| 733 | return 0; |
| 734 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
| 735 | |
| 736 | error = sysdev_class_register(&lapic_sysclass); |
| 737 | if (!error) |
| 738 | error = sysdev_register(&device_lapic); |
| 739 | return error; |
| 740 | } |
| 741 | device_initcall(init_lapic_sysfs); |
| 742 | |
| 743 | #else /* CONFIG_PM */ |
| 744 | |
| 745 | static void apic_pm_activate(void) { } |
| 746 | |
| 747 | #endif /* CONFIG_PM */ |
| 748 | |
| 749 | /* |
| 750 | * Detect and enable local APICs on non-SMP boards. |
| 751 | * Original code written by Keir Fraser. |
| 752 | */ |
| 753 | |
| 754 | static int __init apic_set_verbosity(char *str) |
| 755 | { |
| 756 | if (strcmp("debug", str) == 0) |
| 757 | apic_verbosity = APIC_DEBUG; |
| 758 | else if (strcmp("verbose", str) == 0) |
| 759 | apic_verbosity = APIC_VERBOSE; |
| 760 | else |
| 761 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" |
| 762 | " use apic=verbose or apic=debug\n", str); |
| 763 | |
| 764 | return 1; |
| 765 | } |
| 766 | |
| 767 | __setup("apic=", apic_set_verbosity); |
| 768 | |
| 769 | static int __init detect_init_APIC (void) |
| 770 | { |
| 771 | u32 h, l, features; |
| 772 | |
| 773 | /* Disabled by kernel option? */ |
| 774 | if (enable_local_apic < 0) |
| 775 | return -1; |
| 776 | |
| 777 | switch (boot_cpu_data.x86_vendor) { |
| 778 | case X86_VENDOR_AMD: |
| 779 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
| 780 | (boot_cpu_data.x86 == 15)) |
| 781 | break; |
| 782 | goto no_apic; |
| 783 | case X86_VENDOR_INTEL: |
| 784 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || |
| 785 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) |
| 786 | break; |
| 787 | goto no_apic; |
| 788 | default: |
| 789 | goto no_apic; |
| 790 | } |
| 791 | |
| 792 | if (!cpu_has_apic) { |
| 793 | /* |
| 794 | * Over-ride BIOS and try to enable the local |
| 795 | * APIC only if "lapic" specified. |
| 796 | */ |
| 797 | if (enable_local_apic <= 0) { |
| 798 | printk("Local APIC disabled by BIOS -- " |
| 799 | "you can enable it with \"lapic\"\n"); |
| 800 | return -1; |
| 801 | } |
| 802 | /* |
| 803 | * Some BIOSes disable the local APIC in the |
| 804 | * APIC_BASE MSR. This can only be done in |
| 805 | * software for Intel P6 or later and AMD K7 |
| 806 | * (Model > 1) or later. |
| 807 | */ |
| 808 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 809 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
| 810 | printk("Local APIC disabled by BIOS -- reenabling.\n"); |
| 811 | l &= ~MSR_IA32_APICBASE_BASE; |
| 812 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; |
| 813 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 814 | enabled_via_apicbase = 1; |
| 815 | } |
| 816 | } |
| 817 | /* |
| 818 | * The APIC feature bit should now be enabled |
| 819 | * in `cpuid' |
| 820 | */ |
| 821 | features = cpuid_edx(1); |
| 822 | if (!(features & (1 << X86_FEATURE_APIC))) { |
| 823 | printk("Could not enable APIC!\n"); |
| 824 | return -1; |
| 825 | } |
| 826 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); |
| 827 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 828 | |
| 829 | /* The BIOS may have set up the APIC at some other address */ |
| 830 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 831 | if (l & MSR_IA32_APICBASE_ENABLE) |
| 832 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
| 833 | |
| 834 | if (nmi_watchdog != NMI_NONE) |
| 835 | nmi_watchdog = NMI_LOCAL_APIC; |
| 836 | |
| 837 | printk("Found and enabled local APIC!\n"); |
| 838 | |
| 839 | apic_pm_activate(); |
| 840 | |
| 841 | return 0; |
| 842 | |
| 843 | no_apic: |
| 844 | printk("No local APIC present or hardware disabled\n"); |
| 845 | return -1; |
| 846 | } |
| 847 | |
| 848 | void __init init_apic_mappings(void) |
| 849 | { |
| 850 | unsigned long apic_phys; |
| 851 | |
| 852 | /* |
| 853 | * If no local APIC can be found then set up a fake all |
| 854 | * zeroes page to simulate the local APIC and another |
| 855 | * one for the IO-APIC. |
| 856 | */ |
| 857 | if (!smp_found_config && detect_init_APIC()) { |
| 858 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); |
| 859 | apic_phys = __pa(apic_phys); |
| 860 | } else |
| 861 | apic_phys = mp_lapic_addr; |
| 862 | |
| 863 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
| 864 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, |
| 865 | apic_phys); |
| 866 | |
| 867 | /* |
| 868 | * Fetch the APIC ID of the BSP in case we have a |
| 869 | * default configuration (or the MP table is broken). |
| 870 | */ |
| 871 | if (boot_cpu_physical_apicid == -1U) |
| 872 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
| 873 | |
| 874 | #ifdef CONFIG_X86_IO_APIC |
| 875 | { |
| 876 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; |
| 877 | int i; |
| 878 | |
| 879 | for (i = 0; i < nr_ioapics; i++) { |
| 880 | if (smp_found_config) { |
| 881 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; |
| 882 | if (!ioapic_phys) { |
| 883 | printk(KERN_ERR |
| 884 | "WARNING: bogus zero IO-APIC " |
| 885 | "address found in MPTABLE, " |
| 886 | "disabling IO/APIC support!\n"); |
| 887 | smp_found_config = 0; |
| 888 | skip_ioapic_setup = 1; |
| 889 | goto fake_ioapic_page; |
| 890 | } |
| 891 | } else { |
| 892 | fake_ioapic_page: |
| 893 | ioapic_phys = (unsigned long) |
| 894 | alloc_bootmem_pages(PAGE_SIZE); |
| 895 | ioapic_phys = __pa(ioapic_phys); |
| 896 | } |
| 897 | set_fixmap_nocache(idx, ioapic_phys); |
| 898 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", |
| 899 | __fix_to_virt(idx), ioapic_phys); |
| 900 | idx++; |
| 901 | } |
| 902 | } |
| 903 | #endif |
| 904 | } |
| 905 | |
| 906 | /* |
| 907 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts |
| 908 | * per second. We assume that the caller has already set up the local |
| 909 | * APIC. |
| 910 | * |
| 911 | * The APIC timer is not exactly sync with the external timer chip, it |
| 912 | * closely follows bus clocks. |
| 913 | */ |
| 914 | |
| 915 | /* |
| 916 | * The timer chip is already set up at HZ interrupts per second here, |
| 917 | * but we do not accept timer interrupts yet. We only allow the BP |
| 918 | * to calibrate. |
| 919 | */ |
| 920 | static unsigned int __devinit get_8254_timer_count(void) |
| 921 | { |
| 922 | unsigned long flags; |
| 923 | |
| 924 | unsigned int count; |
| 925 | |
| 926 | spin_lock_irqsave(&i8253_lock, flags); |
| 927 | |
| 928 | outb_p(0x00, PIT_MODE); |
| 929 | count = inb_p(PIT_CH0); |
| 930 | count |= inb_p(PIT_CH0) << 8; |
| 931 | |
| 932 | spin_unlock_irqrestore(&i8253_lock, flags); |
| 933 | |
| 934 | return count; |
| 935 | } |
| 936 | |
| 937 | /* next tick in 8254 can be caught by catching timer wraparound */ |
| 938 | static void __devinit wait_8254_wraparound(void) |
| 939 | { |
| 940 | unsigned int curr_count, prev_count; |
| 941 | |
| 942 | curr_count = get_8254_timer_count(); |
| 943 | do { |
| 944 | prev_count = curr_count; |
| 945 | curr_count = get_8254_timer_count(); |
| 946 | |
| 947 | /* workaround for broken Mercury/Neptune */ |
| 948 | if (prev_count >= curr_count + 0x100) |
| 949 | curr_count = get_8254_timer_count(); |
| 950 | |
| 951 | } while (prev_count >= curr_count); |
| 952 | } |
| 953 | |
| 954 | /* |
| 955 | * Default initialization for 8254 timers. If we use other timers like HPET, |
| 956 | * we override this later |
| 957 | */ |
| 958 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; |
| 959 | |
| 960 | /* |
| 961 | * This function sets up the local APIC timer, with a timeout of |
| 962 | * 'clocks' APIC bus clock. During calibration we actually call |
| 963 | * this function twice on the boot CPU, once with a bogus timeout |
| 964 | * value, second time for real. The other (noncalibrating) CPUs |
| 965 | * call this function only once, with the real, calibrated value. |
| 966 | * |
| 967 | * We do reads before writes even if unnecessary, to get around the |
| 968 | * P5 APIC double write bug. |
| 969 | */ |
| 970 | |
| 971 | #define APIC_DIVISOR 16 |
| 972 | |
| 973 | static void __setup_APIC_LVTT(unsigned int clocks) |
| 974 | { |
| 975 | unsigned int lvtt_value, tmp_value, ver; |
| 976 | int cpu = smp_processor_id(); |
| 977 | |
| 978 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 979 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; |
| 980 | if (!APIC_INTEGRATED(ver)) |
| 981 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); |
| 982 | |
| 983 | if (cpu_isset(cpu, timer_bcast_ipi)) |
| 984 | lvtt_value |= APIC_LVT_MASKED; |
| 985 | |
| 986 | apic_write_around(APIC_LVTT, lvtt_value); |
| 987 | |
| 988 | /* |
| 989 | * Divide PICLK by 16 |
| 990 | */ |
| 991 | tmp_value = apic_read(APIC_TDCR); |
| 992 | apic_write_around(APIC_TDCR, (tmp_value |
| 993 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
| 994 | | APIC_TDR_DIV_16); |
| 995 | |
| 996 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); |
| 997 | } |
| 998 | |
| 999 | static void __devinit setup_APIC_timer(unsigned int clocks) |
| 1000 | { |
| 1001 | unsigned long flags; |
| 1002 | |
| 1003 | local_irq_save(flags); |
| 1004 | |
| 1005 | /* |
| 1006 | * Wait for IRQ0's slice: |
| 1007 | */ |
| 1008 | wait_timer_tick(); |
| 1009 | |
| 1010 | __setup_APIC_LVTT(clocks); |
| 1011 | |
| 1012 | local_irq_restore(flags); |
| 1013 | } |
| 1014 | |
| 1015 | /* |
| 1016 | * In this function we calibrate APIC bus clocks to the external |
| 1017 | * timer. Unfortunately we cannot use jiffies and the timer irq |
| 1018 | * to calibrate, since some later bootup code depends on getting |
| 1019 | * the first irq? Ugh. |
| 1020 | * |
| 1021 | * We want to do the calibration only once since we |
| 1022 | * want to have local timer irqs syncron. CPUs connected |
| 1023 | * by the same APIC bus have the very same bus frequency. |
| 1024 | * And we want to have irqs off anyways, no accidental |
| 1025 | * APIC irq that way. |
| 1026 | */ |
| 1027 | |
| 1028 | static int __init calibrate_APIC_clock(void) |
| 1029 | { |
| 1030 | unsigned long long t1 = 0, t2 = 0; |
| 1031 | long tt1, tt2; |
| 1032 | long result; |
| 1033 | int i; |
| 1034 | const int LOOPS = HZ/10; |
| 1035 | |
| 1036 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); |
| 1037 | |
| 1038 | /* |
| 1039 | * Put whatever arbitrary (but long enough) timeout |
| 1040 | * value into the APIC clock, we just want to get the |
| 1041 | * counter running for calibration. |
| 1042 | */ |
| 1043 | __setup_APIC_LVTT(1000000000); |
| 1044 | |
| 1045 | /* |
| 1046 | * The timer chip counts down to zero. Let's wait |
| 1047 | * for a wraparound to start exact measurement: |
| 1048 | * (the current tick might have been already half done) |
| 1049 | */ |
| 1050 | |
| 1051 | wait_timer_tick(); |
| 1052 | |
| 1053 | /* |
| 1054 | * We wrapped around just now. Let's start: |
| 1055 | */ |
| 1056 | if (cpu_has_tsc) |
| 1057 | rdtscll(t1); |
| 1058 | tt1 = apic_read(APIC_TMCCT); |
| 1059 | |
| 1060 | /* |
| 1061 | * Let's wait LOOPS wraprounds: |
| 1062 | */ |
| 1063 | for (i = 0; i < LOOPS; i++) |
| 1064 | wait_timer_tick(); |
| 1065 | |
| 1066 | tt2 = apic_read(APIC_TMCCT); |
| 1067 | if (cpu_has_tsc) |
| 1068 | rdtscll(t2); |
| 1069 | |
| 1070 | /* |
| 1071 | * The APIC bus clock counter is 32 bits only, it |
| 1072 | * might have overflown, but note that we use signed |
| 1073 | * longs, thus no extra care needed. |
| 1074 | * |
| 1075 | * underflown to be exact, as the timer counts down ;) |
| 1076 | */ |
| 1077 | |
| 1078 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; |
| 1079 | |
| 1080 | if (cpu_has_tsc) |
| 1081 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
| 1082 | "%ld.%04ld MHz.\n", |
| 1083 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), |
| 1084 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); |
| 1085 | |
| 1086 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " |
| 1087 | "%ld.%04ld MHz.\n", |
| 1088 | result/(1000000/HZ), |
| 1089 | result%(1000000/HZ)); |
| 1090 | |
| 1091 | return result; |
| 1092 | } |
| 1093 | |
| 1094 | static unsigned int calibration_result; |
| 1095 | |
| 1096 | void __init setup_boot_APIC_clock(void) |
| 1097 | { |
| 1098 | unsigned long flags; |
| 1099 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); |
| 1100 | using_apic_timer = 1; |
| 1101 | |
| 1102 | local_irq_save(flags); |
| 1103 | |
| 1104 | calibration_result = calibrate_APIC_clock(); |
| 1105 | /* |
| 1106 | * Now set up the timer for real. |
| 1107 | */ |
| 1108 | setup_APIC_timer(calibration_result); |
| 1109 | |
| 1110 | local_irq_restore(flags); |
| 1111 | } |
| 1112 | |
| 1113 | void __devinit setup_secondary_APIC_clock(void) |
| 1114 | { |
| 1115 | setup_APIC_timer(calibration_result); |
| 1116 | } |
| 1117 | |
| 1118 | void disable_APIC_timer(void) |
| 1119 | { |
| 1120 | if (using_apic_timer) { |
| 1121 | unsigned long v; |
| 1122 | |
| 1123 | v = apic_read(APIC_LVTT); |
| 1124 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); |
| 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | void enable_APIC_timer(void) |
| 1129 | { |
| 1130 | int cpu = smp_processor_id(); |
| 1131 | |
| 1132 | if (using_apic_timer && |
| 1133 | !cpu_isset(cpu, timer_bcast_ipi)) { |
| 1134 | unsigned long v; |
| 1135 | |
| 1136 | v = apic_read(APIC_LVTT); |
| 1137 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | void switch_APIC_timer_to_ipi(void *cpumask) |
| 1142 | { |
| 1143 | cpumask_t mask = *(cpumask_t *)cpumask; |
| 1144 | int cpu = smp_processor_id(); |
| 1145 | |
| 1146 | if (cpu_isset(cpu, mask) && |
| 1147 | !cpu_isset(cpu, timer_bcast_ipi)) { |
| 1148 | disable_APIC_timer(); |
| 1149 | cpu_set(cpu, timer_bcast_ipi); |
| 1150 | } |
| 1151 | } |
| 1152 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); |
| 1153 | |
| 1154 | void switch_ipi_to_APIC_timer(void *cpumask) |
| 1155 | { |
| 1156 | cpumask_t mask = *(cpumask_t *)cpumask; |
| 1157 | int cpu = smp_processor_id(); |
| 1158 | |
| 1159 | if (cpu_isset(cpu, mask) && |
| 1160 | cpu_isset(cpu, timer_bcast_ipi)) { |
| 1161 | cpu_clear(cpu, timer_bcast_ipi); |
| 1162 | enable_APIC_timer(); |
| 1163 | } |
| 1164 | } |
| 1165 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); |
| 1166 | |
| 1167 | #undef APIC_DIVISOR |
| 1168 | |
| 1169 | /* |
| 1170 | * Local timer interrupt handler. It does both profiling and |
| 1171 | * process statistics/rescheduling. |
| 1172 | * |
| 1173 | * We do profiling in every local tick, statistics/rescheduling |
| 1174 | * happen only every 'profiling multiplier' ticks. The default |
| 1175 | * multiplier is 1 and it can be changed by writing the new multiplier |
| 1176 | * value into /proc/profile. |
| 1177 | */ |
| 1178 | |
| 1179 | inline void smp_local_timer_interrupt(struct pt_regs * regs) |
| 1180 | { |
| 1181 | profile_tick(CPU_PROFILING, regs); |
| 1182 | #ifdef CONFIG_SMP |
| 1183 | update_process_times(user_mode_vm(regs)); |
| 1184 | #endif |
| 1185 | |
| 1186 | /* |
| 1187 | * We take the 'long' return path, and there every subsystem |
| 1188 | * grabs the apropriate locks (kernel lock/ irq lock). |
| 1189 | * |
| 1190 | * we might want to decouple profiling from the 'long path', |
| 1191 | * and do the profiling totally in assembly. |
| 1192 | * |
| 1193 | * Currently this isn't too much of an issue (performance wise), |
| 1194 | * we can take more than 100K local irqs per second on a 100 MHz P5. |
| 1195 | */ |
| 1196 | } |
| 1197 | |
| 1198 | /* |
| 1199 | * Local APIC timer interrupt. This is the most natural way for doing |
| 1200 | * local interrupts, but local timer interrupts can be emulated by |
| 1201 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 1202 | * |
| 1203 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 1204 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 1205 | */ |
| 1206 | |
| 1207 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) |
| 1208 | { |
| 1209 | int cpu = smp_processor_id(); |
| 1210 | |
| 1211 | /* |
| 1212 | * the NMI deadlock-detector uses this. |
| 1213 | */ |
| 1214 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
| 1215 | |
| 1216 | /* |
| 1217 | * NOTE! We'd better ACK the irq immediately, |
| 1218 | * because timer handling can be slow. |
| 1219 | */ |
| 1220 | ack_APIC_irq(); |
| 1221 | /* |
| 1222 | * update_process_times() expects us to have done irq_enter(). |
| 1223 | * Besides, if we don't timer interrupts ignore the global |
| 1224 | * interrupt lock, which is the WrongThing (tm) to do. |
| 1225 | */ |
| 1226 | irq_enter(); |
| 1227 | smp_local_timer_interrupt(regs); |
| 1228 | irq_exit(); |
| 1229 | } |
| 1230 | |
| 1231 | #ifndef CONFIG_SMP |
| 1232 | static void up_apic_timer_interrupt_call(struct pt_regs *regs) |
| 1233 | { |
| 1234 | int cpu = smp_processor_id(); |
| 1235 | |
| 1236 | /* |
| 1237 | * the NMI deadlock-detector uses this. |
| 1238 | */ |
| 1239 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
| 1240 | |
| 1241 | smp_local_timer_interrupt(regs); |
| 1242 | } |
| 1243 | #endif |
| 1244 | |
| 1245 | void smp_send_timer_broadcast_ipi(struct pt_regs *regs) |
| 1246 | { |
| 1247 | cpumask_t mask; |
| 1248 | |
| 1249 | cpus_and(mask, cpu_online_map, timer_bcast_ipi); |
| 1250 | if (!cpus_empty(mask)) { |
| 1251 | #ifdef CONFIG_SMP |
| 1252 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
| 1253 | #else |
| 1254 | /* |
| 1255 | * We can directly call the apic timer interrupt handler |
| 1256 | * in UP case. Minus all irq related functions |
| 1257 | */ |
| 1258 | up_apic_timer_interrupt_call(regs); |
| 1259 | #endif |
| 1260 | } |
| 1261 | } |
| 1262 | |
| 1263 | int setup_profiling_timer(unsigned int multiplier) |
| 1264 | { |
| 1265 | return -EINVAL; |
| 1266 | } |
| 1267 | |
| 1268 | /* |
| 1269 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1270 | */ |
| 1271 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) |
| 1272 | { |
| 1273 | unsigned long v; |
| 1274 | |
| 1275 | irq_enter(); |
| 1276 | /* |
| 1277 | * Check if this really is a spurious interrupt and ACK it |
| 1278 | * if it is a vectored one. Just in case... |
| 1279 | * Spurious interrupts should not be ACKed. |
| 1280 | */ |
| 1281 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
| 1282 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) |
| 1283 | ack_APIC_irq(); |
| 1284 | |
| 1285 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
| 1286 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n", |
| 1287 | smp_processor_id()); |
| 1288 | irq_exit(); |
| 1289 | } |
| 1290 | |
| 1291 | /* |
| 1292 | * This interrupt should never happen with our APIC/SMP architecture |
| 1293 | */ |
| 1294 | |
| 1295 | fastcall void smp_error_interrupt(struct pt_regs *regs) |
| 1296 | { |
| 1297 | unsigned long v, v1; |
| 1298 | |
| 1299 | irq_enter(); |
| 1300 | /* First tickle the hardware, only then report what went on. -- REW */ |
| 1301 | v = apic_read(APIC_ESR); |
| 1302 | apic_write(APIC_ESR, 0); |
| 1303 | v1 = apic_read(APIC_ESR); |
| 1304 | ack_APIC_irq(); |
| 1305 | atomic_inc(&irq_err_count); |
| 1306 | |
| 1307 | /* Here is what the APIC error bits mean: |
| 1308 | 0: Send CS error |
| 1309 | 1: Receive CS error |
| 1310 | 2: Send accept error |
| 1311 | 3: Receive accept error |
| 1312 | 4: Reserved |
| 1313 | 5: Send illegal vector |
| 1314 | 6: Received illegal vector |
| 1315 | 7: Illegal register address |
| 1316 | */ |
| 1317 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
| 1318 | smp_processor_id(), v , v1); |
| 1319 | irq_exit(); |
| 1320 | } |
| 1321 | |
| 1322 | /* |
| 1323 | * This initializes the IO-APIC and APIC hardware if this is |
| 1324 | * a UP kernel. |
| 1325 | */ |
| 1326 | int __init APIC_init_uniprocessor (void) |
| 1327 | { |
| 1328 | if (enable_local_apic < 0) |
| 1329 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); |
| 1330 | |
| 1331 | if (!smp_found_config && !cpu_has_apic) |
| 1332 | return -1; |
| 1333 | |
| 1334 | /* |
| 1335 | * Complain if the BIOS pretends there is one. |
| 1336 | */ |
| 1337 | if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 1338 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
| 1339 | boot_cpu_physical_apicid); |
| 1340 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); |
| 1341 | return -1; |
| 1342 | } |
| 1343 | |
| 1344 | verify_local_APIC(); |
| 1345 | |
| 1346 | connect_bsp_APIC(); |
| 1347 | |
| 1348 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
| 1349 | |
| 1350 | setup_local_APIC(); |
| 1351 | |
| 1352 | #ifdef CONFIG_X86_IO_APIC |
| 1353 | if (smp_found_config) |
| 1354 | if (!skip_ioapic_setup && nr_ioapics) |
| 1355 | setup_IO_APIC(); |
| 1356 | #endif |
| 1357 | setup_boot_APIC_clock(); |
| 1358 | |
| 1359 | return 0; |
| 1360 | } |