[deliverable/linux.git] / arch / microblaze / kernel / intc.c

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <asm/page.h>
#include <linux/io.h>
#include <linux/bug.h>

#include <asm/prom.h>
#include <asm/irq.h>

#ifdef CONFIG_SELFMOD_INTC
#include <asm/selfmod.h>
#define INTC_BASE	BARRIER_BASE_ADDR
#else
static unsigned int intc_baseaddr;
#define INTC_BASE	intc_baseaddr
#endif

unsigned int nr_irq;

/* No one else should require these constants, so define them locally here. */
#define ISR 0x00			/* Interrupt Status Register */
#define IPR 0x04			/* Interrupt Pending Register */
#define IER 0x08			/* Interrupt Enable Register */
#define IAR 0x0c			/* Interrupt Acknowledge Register */
#define SIE 0x10			/* Set Interrupt Enable bits */
#define CIE 0x14			/* Clear Interrupt Enable bits */
#define IVR 0x18			/* Interrupt Vector Register */
#define MER 0x1c			/* Master Enable Register */

#define MER_ME (1<<0)
#define MER_HIE (1<<1)

static void intc_enable_or_unmask(struct irq_data *d)
{
	unsigned long mask = 1 << d->irq;
	pr_debug("enable_or_unmask: %d\n", d->irq);
	out_be32(INTC_BASE + SIE, mask);

	/* ack level irqs because they can't be acked during
	 * ack function since the handle_level_irq function
	 * acks the irq before calling the interrupt handler
	 */
	if (irqd_is_level_type(d))
		out_be32(INTC_BASE + IAR, mask);
}

static void intc_disable_or_mask(struct irq_data *d)
{
	pr_debug("disable: %d\n", d->irq);
	out_be32(INTC_BASE + CIE, 1 << d->irq);
}

static void intc_ack(struct irq_data *d)
{
	pr_debug("ack: %d\n", d->irq);
	out_be32(INTC_BASE + IAR, 1 << d->irq);
}

static void intc_mask_ack(struct irq_data *d)
{
	unsigned long mask = 1 << d->irq;
	pr_debug("disable_and_ack: %d\n", d->irq);
	out_be32(INTC_BASE + CIE, mask);
	out_be32(INTC_BASE + IAR, mask);
}

static struct irq_chip intc_dev = {
	.name = "Xilinx INTC",
	.irq_unmask = intc_enable_or_unmask,
	.irq_mask = intc_disable_or_mask,
	.irq_ack = intc_ack,
	.irq_mask_ack = intc_mask_ack,
};

unsigned int get_irq(struct pt_regs *regs)
{
	int irq;

	/*
	 * NOTE: This function is the one that needs to be improved in
	 * order to handle multiple interrupt controllers. It currently
	 * is hardcoded to check for interrupts only on the first INTC.
	 */
	irq = in_be32(INTC_BASE + IVR);
	pr_debug("get_irq: %d\n", irq);

	return irq;
}

void __init init_IRQ(void)
{
	u32 i, intr_type;
	struct device_node *intc = NULL;
#ifdef CONFIG_SELFMOD_INTC
	unsigned int intc_baseaddr = 0;
	static int arr_func[] = {
				(int)&get_irq,
				(int)&intc_enable_or_unmask,
				(int)&intc_disable_or_mask,
				(int)&intc_mask_ack,
				(int)&intc_ack,
				(int)&intc_end,
				0
			};
#endif
	intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
	BUG_ON(!intc);

	intc_baseaddr = be32_to_cpup(of_get_property(intc,
								"reg", NULL));
	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
	nr_irq = be32_to_cpup(of_get_property(intc,
						"xlnx,num-intr-inputs", NULL));

	intr_type =
		be32_to_cpup(of_get_property(intc,
						"xlnx,kind-of-intr", NULL));
	if (intr_type > (u32)((1ULL << nr_irq) - 1))
		printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");

#ifdef CONFIG_SELFMOD_INTC
	selfmod_function((int *) arr_func, intc_baseaddr);
#endif
	printk(KERN_INFO "XPS intc #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
		intc_baseaddr, nr_irq, intr_mask);

	/*
	 * Disable all external interrupts until they are
	 * explicity requested.
	 */
	out_be32(intc_baseaddr + IER, 0);

	/* Acknowledge any pending interrupts just in case. */
	out_be32(intc_baseaddr + IAR, 0xffffffff);

	/* Turn on the Master Enable. */
	out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);

	for (i = 0; i < nr_irq; ++i) {
		if (intr_type & (0x00000001 << i)) {
			irq_set_chip_and_handler_name(i, &intc_dev,
				handle_edge_irq, "edge");
			irq_clear_status_flags(i, IRQ_LEVEL);
		} else {
			irq_set_chip_and_handler_name(i, &intc_dev,
				handle_level_irq, "level");
			irq_set_status_flags(i, IRQ_LEVEL);
		}
	}
}
Commit	Line	Data
	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/irq.h>
	13	#include <asm/page.h>
	14	#include <linux/io.h>
	15	#include <linux/bug.h>
	16
	17	#include <asm/prom.h>
	18	#include <asm/irq.h>
	19
	20	#ifdef CONFIG_SELFMOD_INTC
	21	#include <asm/selfmod.h>
	22	#define INTC_BASE BARRIER_BASE_ADDR
	23	#else
	24	static unsigned int intc_baseaddr;
	25	#define INTC_BASE intc_baseaddr
	26	#endif
	27
	28	unsigned int nr_irq;
	29
	30	/* No one else should require these constants, so define them locally here. */
	31	#define ISR 0x00 /* Interrupt Status Register */
	32	#define IPR 0x04 /* Interrupt Pending Register */
	33	#define IER 0x08 /* Interrupt Enable Register */
	34	#define IAR 0x0c /* Interrupt Acknowledge Register */
	35	#define SIE 0x10 /* Set Interrupt Enable bits */
	36	#define CIE 0x14 /* Clear Interrupt Enable bits */
	37	#define IVR 0x18 /* Interrupt Vector Register */
	38	#define MER 0x1c /* Master Enable Register */
	39
	40	#define MER_ME (1<<0)
	41	#define MER_HIE (1<<1)
	42
	43	static void intc_enable_or_unmask(struct irq_data *d)
	44	{
	45	unsigned long mask = 1 << d->irq;
	46	pr_debug("enable_or_unmask: %d\n", d->irq);
	47	out_be32(INTC_BASE + SIE, mask);
	48
	49	/* ack level irqs because they can't be acked during
	50	* ack function since the handle_level_irq function
	51	* acks the irq before calling the interrupt handler
	52	*/
	53	if (irqd_is_level_type(d))
	54	out_be32(INTC_BASE + IAR, mask);
	55	}
	56
	57	static void intc_disable_or_mask(struct irq_data *d)
	58	{
	59	pr_debug("disable: %d\n", d->irq);
	60	out_be32(INTC_BASE + CIE, 1 << d->irq);
	61	}
	62
	63	static void intc_ack(struct irq_data *d)
	64	{
	65	pr_debug("ack: %d\n", d->irq);
	66	out_be32(INTC_BASE + IAR, 1 << d->irq);
	67	}
	68
	69	static void intc_mask_ack(struct irq_data *d)
	70	{
	71	unsigned long mask = 1 << d->irq;
	72	pr_debug("disable_and_ack: %d\n", d->irq);
	73	out_be32(INTC_BASE + CIE, mask);
	74	out_be32(INTC_BASE + IAR, mask);
	75	}
	76
	77	static struct irq_chip intc_dev = {
	78	.name = "Xilinx INTC",
	79	.irq_unmask = intc_enable_or_unmask,
	80	.irq_mask = intc_disable_or_mask,
	81	.irq_ack = intc_ack,
	82	.irq_mask_ack = intc_mask_ack,
	83	};
	84
	85	unsigned int get_irq(struct pt_regs *regs)
	86	{
	87	int irq;
	88
	89	/*
	90	* NOTE: This function is the one that needs to be improved in
	91	* order to handle multiple interrupt controllers. It currently
	92	* is hardcoded to check for interrupts only on the first INTC.
	93	*/
	94	irq = in_be32(INTC_BASE + IVR);
	95	pr_debug("get_irq: %d\n", irq);
	96
	97	return irq;
	98	}
	99
	100	void __init init_IRQ(void)
	101	{
	102	u32 i, intr_type;
	103	struct device_node *intc = NULL;
	104	#ifdef CONFIG_SELFMOD_INTC
	105	unsigned int intc_baseaddr = 0;
	106	static int arr_func[] = {
	107	(int)&get_irq,
	108	(int)&intc_enable_or_unmask,
	109	(int)&intc_disable_or_mask,
	110	(int)&intc_mask_ack,
	111	(int)&intc_ack,
	112	(int)&intc_end,
	113	0
	114	};
	115	#endif
	116	intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
	117	BUG_ON(!intc);
	118
	119	intc_baseaddr = be32_to_cpup(of_get_property(intc,
	120	"reg", NULL));
	121	intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
	122	nr_irq = be32_to_cpup(of_get_property(intc,
	123	"xlnx,num-intr-inputs", NULL));
	124
	125	intr_type =
	126	be32_to_cpup(of_get_property(intc,
	127	"xlnx,kind-of-intr", NULL));
	128	if (intr_type > (u32)((1ULL << nr_irq) - 1))
	129	printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
	130
	131	#ifdef CONFIG_SELFMOD_INTC
	132	selfmod_function((int *) arr_func, intc_baseaddr);
	133	#endif
	134	printk(KERN_INFO "XPS intc #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
	135	intc_baseaddr, nr_irq, intr_mask);
	136
	137	/*
	138	* Disable all external interrupts until they are
	139	* explicity requested.
	140	*/
	141	out_be32(intc_baseaddr + IER, 0);
	142
	143	/* Acknowledge any pending interrupts just in case. */
	144	out_be32(intc_baseaddr + IAR, 0xffffffff);
	145
	146	/* Turn on the Master Enable. */
	147	out_be32(intc_baseaddr + MER, MER_HIE \| MER_ME);
	148
	149	for (i = 0; i < nr_irq; ++i) {
	150	if (intr_type & (0x00000001 << i)) {
	151	irq_set_chip_and_handler_name(i, &intc_dev,
	152	handle_edge_irq, "edge");
	153	irq_clear_status_flags(i, IRQ_LEVEL);
	154	} else {
	155	irq_set_chip_and_handler_name(i, &intc_dev,
	156	handle_level_irq, "level");
	157	irq_set_status_flags(i, IRQ_LEVEL);
	158	}
	159	}
	160	}