| 1 | /* |
| 2 | * Copyright (C) 2010, 2011, 2012, Lemote, Inc. |
| 3 | * Author: Chen Huacai, chenhc@lemote.com |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/cpu.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/smp.h> |
| 21 | #include <linux/cpufreq.h> |
| 22 | #include <asm/processor.h> |
| 23 | #include <asm/time.h> |
| 24 | #include <asm/clock.h> |
| 25 | #include <asm/tlbflush.h> |
| 26 | #include <asm/cacheflush.h> |
| 27 | #include <loongson.h> |
| 28 | |
| 29 | #include "smp.h" |
| 30 | |
| 31 | DEFINE_PER_CPU(int, cpu_state); |
| 32 | DEFINE_PER_CPU(uint32_t, core0_c0count); |
| 33 | |
| 34 | static void *ipi_set0_regs[16]; |
| 35 | static void *ipi_clear0_regs[16]; |
| 36 | static void *ipi_status0_regs[16]; |
| 37 | static void *ipi_en0_regs[16]; |
| 38 | static void *ipi_mailbox_buf[16]; |
| 39 | |
| 40 | /* read a 32bit value from ipi register */ |
| 41 | #define loongson3_ipi_read32(addr) readl(addr) |
| 42 | /* read a 64bit value from ipi register */ |
| 43 | #define loongson3_ipi_read64(addr) readq(addr) |
| 44 | /* write a 32bit value to ipi register */ |
| 45 | #define loongson3_ipi_write32(action, addr) \ |
| 46 | do { \ |
| 47 | writel(action, addr); \ |
| 48 | __wbflush(); \ |
| 49 | } while (0) |
| 50 | /* write a 64bit value to ipi register */ |
| 51 | #define loongson3_ipi_write64(action, addr) \ |
| 52 | do { \ |
| 53 | writeq(action, addr); \ |
| 54 | __wbflush(); \ |
| 55 | } while (0) |
| 56 | |
| 57 | static void ipi_set0_regs_init(void) |
| 58 | { |
| 59 | ipi_set0_regs[0] = (void *) |
| 60 | (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); |
| 61 | ipi_set0_regs[1] = (void *) |
| 62 | (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); |
| 63 | ipi_set0_regs[2] = (void *) |
| 64 | (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); |
| 65 | ipi_set0_regs[3] = (void *) |
| 66 | (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); |
| 67 | ipi_set0_regs[4] = (void *) |
| 68 | (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); |
| 69 | ipi_set0_regs[5] = (void *) |
| 70 | (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); |
| 71 | ipi_set0_regs[6] = (void *) |
| 72 | (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); |
| 73 | ipi_set0_regs[7] = (void *) |
| 74 | (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); |
| 75 | ipi_set0_regs[8] = (void *) |
| 76 | (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); |
| 77 | ipi_set0_regs[9] = (void *) |
| 78 | (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); |
| 79 | ipi_set0_regs[10] = (void *) |
| 80 | (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0); |
| 81 | ipi_set0_regs[11] = (void *) |
| 82 | (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0); |
| 83 | ipi_set0_regs[12] = (void *) |
| 84 | (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0); |
| 85 | ipi_set0_regs[13] = (void *) |
| 86 | (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0); |
| 87 | ipi_set0_regs[14] = (void *) |
| 88 | (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0); |
| 89 | ipi_set0_regs[15] = (void *) |
| 90 | (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0); |
| 91 | } |
| 92 | |
| 93 | static void ipi_clear0_regs_init(void) |
| 94 | { |
| 95 | ipi_clear0_regs[0] = (void *) |
| 96 | (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); |
| 97 | ipi_clear0_regs[1] = (void *) |
| 98 | (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); |
| 99 | ipi_clear0_regs[2] = (void *) |
| 100 | (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); |
| 101 | ipi_clear0_regs[3] = (void *) |
| 102 | (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); |
| 103 | ipi_clear0_regs[4] = (void *) |
| 104 | (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); |
| 105 | ipi_clear0_regs[5] = (void *) |
| 106 | (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); |
| 107 | ipi_clear0_regs[6] = (void *) |
| 108 | (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); |
| 109 | ipi_clear0_regs[7] = (void *) |
| 110 | (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); |
| 111 | ipi_clear0_regs[8] = (void *) |
| 112 | (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); |
| 113 | ipi_clear0_regs[9] = (void *) |
| 114 | (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); |
| 115 | ipi_clear0_regs[10] = (void *) |
| 116 | (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0); |
| 117 | ipi_clear0_regs[11] = (void *) |
| 118 | (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0); |
| 119 | ipi_clear0_regs[12] = (void *) |
| 120 | (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0); |
| 121 | ipi_clear0_regs[13] = (void *) |
| 122 | (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0); |
| 123 | ipi_clear0_regs[14] = (void *) |
| 124 | (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0); |
| 125 | ipi_clear0_regs[15] = (void *) |
| 126 | (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0); |
| 127 | } |
| 128 | |
| 129 | static void ipi_status0_regs_init(void) |
| 130 | { |
| 131 | ipi_status0_regs[0] = (void *) |
| 132 | (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); |
| 133 | ipi_status0_regs[1] = (void *) |
| 134 | (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); |
| 135 | ipi_status0_regs[2] = (void *) |
| 136 | (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); |
| 137 | ipi_status0_regs[3] = (void *) |
| 138 | (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); |
| 139 | ipi_status0_regs[4] = (void *) |
| 140 | (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); |
| 141 | ipi_status0_regs[5] = (void *) |
| 142 | (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); |
| 143 | ipi_status0_regs[6] = (void *) |
| 144 | (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); |
| 145 | ipi_status0_regs[7] = (void *) |
| 146 | (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); |
| 147 | ipi_status0_regs[8] = (void *) |
| 148 | (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); |
| 149 | ipi_status0_regs[9] = (void *) |
| 150 | (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); |
| 151 | ipi_status0_regs[10] = (void *) |
| 152 | (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0); |
| 153 | ipi_status0_regs[11] = (void *) |
| 154 | (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0); |
| 155 | ipi_status0_regs[12] = (void *) |
| 156 | (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0); |
| 157 | ipi_status0_regs[13] = (void *) |
| 158 | (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0); |
| 159 | ipi_status0_regs[14] = (void *) |
| 160 | (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0); |
| 161 | ipi_status0_regs[15] = (void *) |
| 162 | (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0); |
| 163 | } |
| 164 | |
| 165 | static void ipi_en0_regs_init(void) |
| 166 | { |
| 167 | ipi_en0_regs[0] = (void *) |
| 168 | (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); |
| 169 | ipi_en0_regs[1] = (void *) |
| 170 | (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); |
| 171 | ipi_en0_regs[2] = (void *) |
| 172 | (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); |
| 173 | ipi_en0_regs[3] = (void *) |
| 174 | (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); |
| 175 | ipi_en0_regs[4] = (void *) |
| 176 | (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); |
| 177 | ipi_en0_regs[5] = (void *) |
| 178 | (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); |
| 179 | ipi_en0_regs[6] = (void *) |
| 180 | (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); |
| 181 | ipi_en0_regs[7] = (void *) |
| 182 | (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); |
| 183 | ipi_en0_regs[8] = (void *) |
| 184 | (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); |
| 185 | ipi_en0_regs[9] = (void *) |
| 186 | (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); |
| 187 | ipi_en0_regs[10] = (void *) |
| 188 | (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0); |
| 189 | ipi_en0_regs[11] = (void *) |
| 190 | (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0); |
| 191 | ipi_en0_regs[12] = (void *) |
| 192 | (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0); |
| 193 | ipi_en0_regs[13] = (void *) |
| 194 | (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0); |
| 195 | ipi_en0_regs[14] = (void *) |
| 196 | (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0); |
| 197 | ipi_en0_regs[15] = (void *) |
| 198 | (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0); |
| 199 | } |
| 200 | |
| 201 | static void ipi_mailbox_buf_init(void) |
| 202 | { |
| 203 | ipi_mailbox_buf[0] = (void *) |
| 204 | (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF); |
| 205 | ipi_mailbox_buf[1] = (void *) |
| 206 | (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF); |
| 207 | ipi_mailbox_buf[2] = (void *) |
| 208 | (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF); |
| 209 | ipi_mailbox_buf[3] = (void *) |
| 210 | (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF); |
| 211 | ipi_mailbox_buf[4] = (void *) |
| 212 | (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF); |
| 213 | ipi_mailbox_buf[5] = (void *) |
| 214 | (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF); |
| 215 | ipi_mailbox_buf[6] = (void *) |
| 216 | (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF); |
| 217 | ipi_mailbox_buf[7] = (void *) |
| 218 | (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF); |
| 219 | ipi_mailbox_buf[8] = (void *) |
| 220 | (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF); |
| 221 | ipi_mailbox_buf[9] = (void *) |
| 222 | (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF); |
| 223 | ipi_mailbox_buf[10] = (void *) |
| 224 | (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF); |
| 225 | ipi_mailbox_buf[11] = (void *) |
| 226 | (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF); |
| 227 | ipi_mailbox_buf[12] = (void *) |
| 228 | (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF); |
| 229 | ipi_mailbox_buf[13] = (void *) |
| 230 | (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF); |
| 231 | ipi_mailbox_buf[14] = (void *) |
| 232 | (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF); |
| 233 | ipi_mailbox_buf[15] = (void *) |
| 234 | (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF); |
| 235 | } |
| 236 | |
| 237 | /* |
| 238 | * Simple enough, just poke the appropriate ipi register |
| 239 | */ |
| 240 | static void loongson3_send_ipi_single(int cpu, unsigned int action) |
| 241 | { |
| 242 | loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(cpu)]); |
| 243 | } |
| 244 | |
| 245 | static void |
| 246 | loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) |
| 247 | { |
| 248 | unsigned int i; |
| 249 | |
| 250 | for_each_cpu(i, mask) |
| 251 | loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]); |
| 252 | } |
| 253 | |
| 254 | void loongson3_ipi_interrupt(struct pt_regs *regs) |
| 255 | { |
| 256 | int i, cpu = smp_processor_id(); |
| 257 | unsigned int action, c0count; |
| 258 | |
| 259 | /* Load the ipi register to figure out what we're supposed to do */ |
| 260 | action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); |
| 261 | |
| 262 | /* Clear the ipi register to clear the interrupt */ |
| 263 | loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]); |
| 264 | |
| 265 | if (action & SMP_RESCHEDULE_YOURSELF) |
| 266 | scheduler_ipi(); |
| 267 | |
| 268 | if (action & SMP_CALL_FUNCTION) |
| 269 | smp_call_function_interrupt(); |
| 270 | |
| 271 | if (action & SMP_ASK_C0COUNT) { |
| 272 | BUG_ON(cpu != 0); |
| 273 | c0count = read_c0_count(); |
| 274 | for (i = 1; i < loongson_sysconf.nr_cpus; i++) |
| 275 | per_cpu(core0_c0count, i) = c0count; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | #define MAX_LOOPS 1111 |
| 280 | /* |
| 281 | * SMP init and finish on secondary CPUs |
| 282 | */ |
| 283 | static void loongson3_init_secondary(void) |
| 284 | { |
| 285 | int i; |
| 286 | uint32_t initcount; |
| 287 | unsigned int cpu = smp_processor_id(); |
| 288 | unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | |
| 289 | STATUSF_IP3 | STATUSF_IP2; |
| 290 | |
| 291 | /* Set interrupt mask, but don't enable */ |
| 292 | change_c0_status(ST0_IM, imask); |
| 293 | |
| 294 | for (i = 0; i < num_possible_cpus(); i++) |
| 295 | loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]); |
| 296 | |
| 297 | per_cpu(cpu_state, cpu) = CPU_ONLINE; |
| 298 | cpu_data[cpu].core = |
| 299 | cpu_logical_map(cpu) % loongson_sysconf.cores_per_package; |
| 300 | cpu_data[cpu].package = |
| 301 | cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; |
| 302 | |
| 303 | i = 0; |
| 304 | __this_cpu_write(core0_c0count, 0); |
| 305 | loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); |
| 306 | while (!__this_cpu_read(core0_c0count)) { |
| 307 | i++; |
| 308 | cpu_relax(); |
| 309 | } |
| 310 | |
| 311 | if (i > MAX_LOOPS) |
| 312 | i = MAX_LOOPS; |
| 313 | initcount = __this_cpu_read(core0_c0count) + i; |
| 314 | write_c0_count(initcount); |
| 315 | } |
| 316 | |
| 317 | static void loongson3_smp_finish(void) |
| 318 | { |
| 319 | int cpu = smp_processor_id(); |
| 320 | |
| 321 | write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); |
| 322 | local_irq_enable(); |
| 323 | loongson3_ipi_write64(0, |
| 324 | (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0)); |
| 325 | pr_info("CPU#%d finished, CP0_ST=%x\n", |
| 326 | smp_processor_id(), read_c0_status()); |
| 327 | } |
| 328 | |
| 329 | static void __init loongson3_smp_setup(void) |
| 330 | { |
| 331 | int i = 0, num = 0; /* i: physical id, num: logical id */ |
| 332 | |
| 333 | init_cpu_possible(cpu_none_mask); |
| 334 | |
| 335 | /* For unified kernel, NR_CPUS is the maximum possible value, |
| 336 | * loongson_sysconf.nr_cpus is the really present value */ |
| 337 | while (i < loongson_sysconf.nr_cpus) { |
| 338 | if (loongson_sysconf.reserved_cpus_mask & (1<<i)) { |
| 339 | /* Reserved physical CPU cores */ |
| 340 | __cpu_number_map[i] = -1; |
| 341 | } else { |
| 342 | __cpu_number_map[i] = num; |
| 343 | __cpu_logical_map[num] = i; |
| 344 | set_cpu_possible(num, true); |
| 345 | num++; |
| 346 | } |
| 347 | i++; |
| 348 | } |
| 349 | pr_info("Detected %i available CPU(s)\n", num); |
| 350 | |
| 351 | while (num < loongson_sysconf.nr_cpus) { |
| 352 | __cpu_logical_map[num] = -1; |
| 353 | num++; |
| 354 | } |
| 355 | |
| 356 | ipi_set0_regs_init(); |
| 357 | ipi_clear0_regs_init(); |
| 358 | ipi_status0_regs_init(); |
| 359 | ipi_en0_regs_init(); |
| 360 | ipi_mailbox_buf_init(); |
| 361 | cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package; |
| 362 | cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; |
| 363 | } |
| 364 | |
| 365 | static void __init loongson3_prepare_cpus(unsigned int max_cpus) |
| 366 | { |
| 367 | init_cpu_present(cpu_possible_mask); |
| 368 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
| 369 | } |
| 370 | |
| 371 | /* |
| 372 | * Setup the PC, SP, and GP of a secondary processor and start it runing! |
| 373 | */ |
| 374 | static void loongson3_boot_secondary(int cpu, struct task_struct *idle) |
| 375 | { |
| 376 | unsigned long startargs[4]; |
| 377 | |
| 378 | pr_info("Booting CPU#%d...\n", cpu); |
| 379 | |
| 380 | /* startargs[] are initial PC, SP and GP for secondary CPU */ |
| 381 | startargs[0] = (unsigned long)&smp_bootstrap; |
| 382 | startargs[1] = (unsigned long)__KSTK_TOS(idle); |
| 383 | startargs[2] = (unsigned long)task_thread_info(idle); |
| 384 | startargs[3] = 0; |
| 385 | |
| 386 | pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", |
| 387 | cpu, startargs[0], startargs[1], startargs[2]); |
| 388 | |
| 389 | loongson3_ipi_write64(startargs[3], |
| 390 | (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x18)); |
| 391 | loongson3_ipi_write64(startargs[2], |
| 392 | (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x10)); |
| 393 | loongson3_ipi_write64(startargs[1], |
| 394 | (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x8)); |
| 395 | loongson3_ipi_write64(startargs[0], |
| 396 | (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0)); |
| 397 | } |
| 398 | |
| 399 | #ifdef CONFIG_HOTPLUG_CPU |
| 400 | |
| 401 | static int loongson3_cpu_disable(void) |
| 402 | { |
| 403 | unsigned long flags; |
| 404 | unsigned int cpu = smp_processor_id(); |
| 405 | |
| 406 | if (cpu == 0) |
| 407 | return -EBUSY; |
| 408 | |
| 409 | set_cpu_online(cpu, false); |
| 410 | cpu_clear(cpu, cpu_callin_map); |
| 411 | local_irq_save(flags); |
| 412 | fixup_irqs(); |
| 413 | local_irq_restore(flags); |
| 414 | flush_cache_all(); |
| 415 | local_flush_tlb_all(); |
| 416 | |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | |
| 421 | static void loongson3_cpu_die(unsigned int cpu) |
| 422 | { |
| 423 | while (per_cpu(cpu_state, cpu) != CPU_DEAD) |
| 424 | cpu_relax(); |
| 425 | |
| 426 | mb(); |
| 427 | } |
| 428 | |
| 429 | /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and |
| 430 | * flush all L1 entries at first. Then, another core (usually Core 0) can |
| 431 | * safely disable the clock of the target core. loongson3_play_dead() is |
| 432 | * called via CKSEG1 (uncached and unmmaped) */ |
| 433 | static void loongson3a_play_dead(int *state_addr) |
| 434 | { |
| 435 | register int val; |
| 436 | register long cpuid, core, node, count; |
| 437 | register void *addr, *base, *initfunc; |
| 438 | |
| 439 | __asm__ __volatile__( |
| 440 | " .set push \n" |
| 441 | " .set noreorder \n" |
| 442 | " li %[addr], 0x80000000 \n" /* KSEG0 */ |
| 443 | "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ |
| 444 | " cache 0, 1(%[addr]) \n" |
| 445 | " cache 0, 2(%[addr]) \n" |
| 446 | " cache 0, 3(%[addr]) \n" |
| 447 | " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ |
| 448 | " cache 1, 1(%[addr]) \n" |
| 449 | " cache 1, 2(%[addr]) \n" |
| 450 | " cache 1, 3(%[addr]) \n" |
| 451 | " addiu %[sets], %[sets], -1 \n" |
| 452 | " bnez %[sets], 1b \n" |
| 453 | " addiu %[addr], %[addr], 0x20 \n" |
| 454 | " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ |
| 455 | " sw %[val], (%[state_addr]) \n" |
| 456 | " sync \n" |
| 457 | " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ |
| 458 | " .set pop \n" |
| 459 | : [addr] "=&r" (addr), [val] "=&r" (val) |
| 460 | : [state_addr] "r" (state_addr), |
| 461 | [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); |
| 462 | |
| 463 | __asm__ __volatile__( |
| 464 | " .set push \n" |
| 465 | " .set noreorder \n" |
| 466 | " .set mips64 \n" |
| 467 | " mfc0 %[cpuid], $15, 1 \n" |
| 468 | " andi %[cpuid], 0x3ff \n" |
| 469 | " dli %[base], 0x900000003ff01000 \n" |
| 470 | " andi %[core], %[cpuid], 0x3 \n" |
| 471 | " sll %[core], 8 \n" /* get core id */ |
| 472 | " or %[base], %[base], %[core] \n" |
| 473 | " andi %[node], %[cpuid], 0xc \n" |
| 474 | " dsll %[node], 42 \n" /* get node id */ |
| 475 | " or %[base], %[base], %[node] \n" |
| 476 | "1: li %[count], 0x100 \n" /* wait for init loop */ |
| 477 | "2: bnez %[count], 2b \n" /* limit mailbox access */ |
| 478 | " addiu %[count], -1 \n" |
| 479 | " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ |
| 480 | " beqz %[initfunc], 1b \n" |
| 481 | " nop \n" |
| 482 | " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ |
| 483 | " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ |
| 484 | " ld $a1, 0x38(%[base]) \n" |
| 485 | " jr %[initfunc] \n" /* jump to initial PC */ |
| 486 | " nop \n" |
| 487 | " .set pop \n" |
| 488 | : [core] "=&r" (core), [node] "=&r" (node), |
| 489 | [base] "=&r" (base), [cpuid] "=&r" (cpuid), |
| 490 | [count] "=&r" (count), [initfunc] "=&r" (initfunc) |
| 491 | : /* No Input */ |
| 492 | : "a1"); |
| 493 | } |
| 494 | |
| 495 | static void loongson3b_play_dead(int *state_addr) |
| 496 | { |
| 497 | register int val; |
| 498 | register long cpuid, core, node, count; |
| 499 | register void *addr, *base, *initfunc; |
| 500 | |
| 501 | __asm__ __volatile__( |
| 502 | " .set push \n" |
| 503 | " .set noreorder \n" |
| 504 | " li %[addr], 0x80000000 \n" /* KSEG0 */ |
| 505 | "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ |
| 506 | " cache 0, 1(%[addr]) \n" |
| 507 | " cache 0, 2(%[addr]) \n" |
| 508 | " cache 0, 3(%[addr]) \n" |
| 509 | " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ |
| 510 | " cache 1, 1(%[addr]) \n" |
| 511 | " cache 1, 2(%[addr]) \n" |
| 512 | " cache 1, 3(%[addr]) \n" |
| 513 | " addiu %[sets], %[sets], -1 \n" |
| 514 | " bnez %[sets], 1b \n" |
| 515 | " addiu %[addr], %[addr], 0x20 \n" |
| 516 | " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ |
| 517 | " sw %[val], (%[state_addr]) \n" |
| 518 | " sync \n" |
| 519 | " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ |
| 520 | " .set pop \n" |
| 521 | : [addr] "=&r" (addr), [val] "=&r" (val) |
| 522 | : [state_addr] "r" (state_addr), |
| 523 | [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); |
| 524 | |
| 525 | __asm__ __volatile__( |
| 526 | " .set push \n" |
| 527 | " .set noreorder \n" |
| 528 | " .set mips64 \n" |
| 529 | " mfc0 %[cpuid], $15, 1 \n" |
| 530 | " andi %[cpuid], 0x3ff \n" |
| 531 | " dli %[base], 0x900000003ff01000 \n" |
| 532 | " andi %[core], %[cpuid], 0x3 \n" |
| 533 | " sll %[core], 8 \n" /* get core id */ |
| 534 | " or %[base], %[base], %[core] \n" |
| 535 | " andi %[node], %[cpuid], 0xc \n" |
| 536 | " dsll %[node], 42 \n" /* get node id */ |
| 537 | " or %[base], %[base], %[node] \n" |
| 538 | " dsrl %[node], 30 \n" /* 15:14 */ |
| 539 | " or %[base], %[base], %[node] \n" |
| 540 | "1: li %[count], 0x100 \n" /* wait for init loop */ |
| 541 | "2: bnez %[count], 2b \n" /* limit mailbox access */ |
| 542 | " addiu %[count], -1 \n" |
| 543 | " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ |
| 544 | " beqz %[initfunc], 1b \n" |
| 545 | " nop \n" |
| 546 | " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ |
| 547 | " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ |
| 548 | " ld $a1, 0x38(%[base]) \n" |
| 549 | " jr %[initfunc] \n" /* jump to initial PC */ |
| 550 | " nop \n" |
| 551 | " .set pop \n" |
| 552 | : [core] "=&r" (core), [node] "=&r" (node), |
| 553 | [base] "=&r" (base), [cpuid] "=&r" (cpuid), |
| 554 | [count] "=&r" (count), [initfunc] "=&r" (initfunc) |
| 555 | : /* No Input */ |
| 556 | : "a1"); |
| 557 | } |
| 558 | |
| 559 | void play_dead(void) |
| 560 | { |
| 561 | int *state_addr; |
| 562 | unsigned int cpu = smp_processor_id(); |
| 563 | void (*play_dead_at_ckseg1)(int *); |
| 564 | |
| 565 | idle_task_exit(); |
| 566 | switch (loongson_sysconf.cputype) { |
| 567 | case Loongson_3A: |
| 568 | default: |
| 569 | play_dead_at_ckseg1 = |
| 570 | (void *)CKSEG1ADDR((unsigned long)loongson3a_play_dead); |
| 571 | break; |
| 572 | case Loongson_3B: |
| 573 | play_dead_at_ckseg1 = |
| 574 | (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead); |
| 575 | break; |
| 576 | } |
| 577 | state_addr = &per_cpu(cpu_state, cpu); |
| 578 | mb(); |
| 579 | play_dead_at_ckseg1(state_addr); |
| 580 | } |
| 581 | |
| 582 | void loongson3_disable_clock(int cpu) |
| 583 | { |
| 584 | uint64_t core_id = cpu_data[cpu].core; |
| 585 | uint64_t package_id = cpu_data[cpu].package; |
| 586 | |
| 587 | if (loongson_sysconf.cputype == Loongson_3A) { |
| 588 | LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); |
| 589 | } else if (loongson_sysconf.cputype == Loongson_3B) { |
| 590 | if (!cpuhotplug_workaround) |
| 591 | LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3)); |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | void loongson3_enable_clock(int cpu) |
| 596 | { |
| 597 | uint64_t core_id = cpu_data[cpu].core; |
| 598 | uint64_t package_id = cpu_data[cpu].package; |
| 599 | |
| 600 | if (loongson_sysconf.cputype == Loongson_3A) { |
| 601 | LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); |
| 602 | } else if (loongson_sysconf.cputype == Loongson_3B) { |
| 603 | if (!cpuhotplug_workaround) |
| 604 | LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | #define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN) |
| 609 | static int loongson3_cpu_callback(struct notifier_block *nfb, |
| 610 | unsigned long action, void *hcpu) |
| 611 | { |
| 612 | unsigned int cpu = (unsigned long)hcpu; |
| 613 | |
| 614 | switch (action) { |
| 615 | case CPU_POST_DEAD: |
| 616 | case CPU_POST_DEAD_FROZEN: |
| 617 | pr_info("Disable clock for CPU#%d\n", cpu); |
| 618 | loongson3_disable_clock(cpu); |
| 619 | break; |
| 620 | case CPU_UP_PREPARE: |
| 621 | case CPU_UP_PREPARE_FROZEN: |
| 622 | pr_info("Enable clock for CPU#%d\n", cpu); |
| 623 | loongson3_enable_clock(cpu); |
| 624 | break; |
| 625 | } |
| 626 | |
| 627 | return NOTIFY_OK; |
| 628 | } |
| 629 | |
| 630 | static int register_loongson3_notifier(void) |
| 631 | { |
| 632 | hotcpu_notifier(loongson3_cpu_callback, 0); |
| 633 | return 0; |
| 634 | } |
| 635 | early_initcall(register_loongson3_notifier); |
| 636 | |
| 637 | #endif |
| 638 | |
| 639 | struct plat_smp_ops loongson3_smp_ops = { |
| 640 | .send_ipi_single = loongson3_send_ipi_single, |
| 641 | .send_ipi_mask = loongson3_send_ipi_mask, |
| 642 | .init_secondary = loongson3_init_secondary, |
| 643 | .smp_finish = loongson3_smp_finish, |
| 644 | .boot_secondary = loongson3_boot_secondary, |
| 645 | .smp_setup = loongson3_smp_setup, |
| 646 | .prepare_cpus = loongson3_prepare_cpus, |
| 647 | #ifdef CONFIG_HOTPLUG_CPU |
| 648 | .cpu_disable = loongson3_cpu_disable, |
| 649 | .cpu_die = loongson3_cpu_die, |
| 650 | #endif |
| 651 | }; |