| 1 | /* MN10300 Arch-specific interrupt handling |
| 2 | * |
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public Licence |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the Licence, or (at your option) any later version. |
| 10 | */ |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/kernel_stat.h> |
| 14 | #include <linux/seq_file.h> |
| 15 | #include <linux/cpumask.h> |
| 16 | #include <asm/setup.h> |
| 17 | #include <asm/serial-regs.h> |
| 18 | |
| 19 | unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = { |
| 20 | [0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7 |
| 21 | }; |
| 22 | EXPORT_SYMBOL(__mn10300_irq_enabled_epsw); |
| 23 | |
| 24 | #ifdef CONFIG_SMP |
| 25 | static char irq_affinity_online[NR_IRQS] = { |
| 26 | [0 ... NR_IRQS - 1] = 0 |
| 27 | }; |
| 28 | |
| 29 | #define NR_IRQ_WORDS ((NR_IRQS + 31) / 32) |
| 30 | static unsigned long irq_affinity_request[NR_IRQ_WORDS] = { |
| 31 | [0 ... NR_IRQ_WORDS - 1] = 0 |
| 32 | }; |
| 33 | #endif /* CONFIG_SMP */ |
| 34 | |
| 35 | atomic_t irq_err_count; |
| 36 | |
| 37 | /* |
| 38 | * MN10300 interrupt controller operations |
| 39 | */ |
| 40 | static void mn10300_cpupic_ack(struct irq_data *d) |
| 41 | { |
| 42 | unsigned int irq = d->irq; |
| 43 | unsigned long flags; |
| 44 | u16 tmp; |
| 45 | |
| 46 | flags = arch_local_cli_save(); |
| 47 | GxICR_u8(irq) = GxICR_DETECT; |
| 48 | tmp = GxICR(irq); |
| 49 | arch_local_irq_restore(flags); |
| 50 | } |
| 51 | |
| 52 | static void __mask_and_set_icr(unsigned int irq, |
| 53 | unsigned int mask, unsigned int set) |
| 54 | { |
| 55 | unsigned long flags; |
| 56 | u16 tmp; |
| 57 | |
| 58 | flags = arch_local_cli_save(); |
| 59 | tmp = GxICR(irq); |
| 60 | GxICR(irq) = (tmp & mask) | set; |
| 61 | tmp = GxICR(irq); |
| 62 | arch_local_irq_restore(flags); |
| 63 | } |
| 64 | |
| 65 | static void mn10300_cpupic_mask(struct irq_data *d) |
| 66 | { |
| 67 | __mask_and_set_icr(d->irq, GxICR_LEVEL, 0); |
| 68 | } |
| 69 | |
| 70 | static void mn10300_cpupic_mask_ack(struct irq_data *d) |
| 71 | { |
| 72 | unsigned int irq = d->irq; |
| 73 | #ifdef CONFIG_SMP |
| 74 | unsigned long flags; |
| 75 | u16 tmp; |
| 76 | |
| 77 | flags = arch_local_cli_save(); |
| 78 | |
| 79 | if (!test_and_clear_bit(irq, irq_affinity_request)) { |
| 80 | tmp = GxICR(irq); |
| 81 | GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; |
| 82 | tmp = GxICR(irq); |
| 83 | } else { |
| 84 | u16 tmp2; |
| 85 | tmp = GxICR(irq); |
| 86 | GxICR(irq) = (tmp & GxICR_LEVEL); |
| 87 | tmp2 = GxICR(irq); |
| 88 | |
| 89 | irq_affinity_online[irq] = |
| 90 | cpumask_any_and(irq_data_get_affinity_mask(d), |
| 91 | cpu_online_mask); |
| 92 | CROSS_GxICR(irq, irq_affinity_online[irq]) = |
| 93 | (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT; |
| 94 | tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); |
| 95 | } |
| 96 | |
| 97 | arch_local_irq_restore(flags); |
| 98 | #else /* CONFIG_SMP */ |
| 99 | __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT); |
| 100 | #endif /* CONFIG_SMP */ |
| 101 | } |
| 102 | |
| 103 | static void mn10300_cpupic_unmask(struct irq_data *d) |
| 104 | { |
| 105 | __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE); |
| 106 | } |
| 107 | |
| 108 | static void mn10300_cpupic_unmask_clear(struct irq_data *d) |
| 109 | { |
| 110 | unsigned int irq = d->irq; |
| 111 | /* the MN10300 PIC latches its interrupt request bit, even after the |
| 112 | * device has ceased to assert its interrupt line and the interrupt |
| 113 | * channel has been disabled in the PIC, so for level-triggered |
| 114 | * interrupts we need to clear the request bit when we re-enable */ |
| 115 | #ifdef CONFIG_SMP |
| 116 | unsigned long flags; |
| 117 | u16 tmp; |
| 118 | |
| 119 | flags = arch_local_cli_save(); |
| 120 | |
| 121 | if (!test_and_clear_bit(irq, irq_affinity_request)) { |
| 122 | tmp = GxICR(irq); |
| 123 | GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; |
| 124 | tmp = GxICR(irq); |
| 125 | } else { |
| 126 | tmp = GxICR(irq); |
| 127 | |
| 128 | irq_affinity_online[irq] = cpumask_any_and(irq_data_get_affinity_mask(d), |
| 129 | cpu_online_mask); |
| 130 | CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT; |
| 131 | tmp = CROSS_GxICR(irq, irq_affinity_online[irq]); |
| 132 | } |
| 133 | |
| 134 | arch_local_irq_restore(flags); |
| 135 | #else /* CONFIG_SMP */ |
| 136 | __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT); |
| 137 | #endif /* CONFIG_SMP */ |
| 138 | } |
| 139 | |
| 140 | #ifdef CONFIG_SMP |
| 141 | static int |
| 142 | mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask, |
| 143 | bool force) |
| 144 | { |
| 145 | unsigned long flags; |
| 146 | |
| 147 | flags = arch_local_cli_save(); |
| 148 | set_bit(d->irq, irq_affinity_request); |
| 149 | arch_local_irq_restore(flags); |
| 150 | return 0; |
| 151 | } |
| 152 | #endif /* CONFIG_SMP */ |
| 153 | |
| 154 | /* |
| 155 | * MN10300 PIC level-triggered IRQ handling. |
| 156 | * |
| 157 | * The PIC has no 'ACK' function per se. It is possible to clear individual |
| 158 | * channel latches, but each latch relatches whether or not the channel is |
| 159 | * masked, so we need to clear the latch when we unmask the channel. |
| 160 | * |
| 161 | * Also for this reason, we don't supply an ack() op (it's unused anyway if |
| 162 | * mask_ack() is provided), and mask_ack() just masks. |
| 163 | */ |
| 164 | static struct irq_chip mn10300_cpu_pic_level = { |
| 165 | .name = "cpu_l", |
| 166 | .irq_disable = mn10300_cpupic_mask, |
| 167 | .irq_enable = mn10300_cpupic_unmask_clear, |
| 168 | .irq_ack = NULL, |
| 169 | .irq_mask = mn10300_cpupic_mask, |
| 170 | .irq_mask_ack = mn10300_cpupic_mask, |
| 171 | .irq_unmask = mn10300_cpupic_unmask_clear, |
| 172 | #ifdef CONFIG_SMP |
| 173 | .irq_set_affinity = mn10300_cpupic_setaffinity, |
| 174 | #endif |
| 175 | }; |
| 176 | |
| 177 | /* |
| 178 | * MN10300 PIC edge-triggered IRQ handling. |
| 179 | * |
| 180 | * We use the latch clearing function of the PIC as the 'ACK' function. |
| 181 | */ |
| 182 | static struct irq_chip mn10300_cpu_pic_edge = { |
| 183 | .name = "cpu_e", |
| 184 | .irq_disable = mn10300_cpupic_mask, |
| 185 | .irq_enable = mn10300_cpupic_unmask, |
| 186 | .irq_ack = mn10300_cpupic_ack, |
| 187 | .irq_mask = mn10300_cpupic_mask, |
| 188 | .irq_mask_ack = mn10300_cpupic_mask_ack, |
| 189 | .irq_unmask = mn10300_cpupic_unmask, |
| 190 | #ifdef CONFIG_SMP |
| 191 | .irq_set_affinity = mn10300_cpupic_setaffinity, |
| 192 | #endif |
| 193 | }; |
| 194 | |
| 195 | /* |
| 196 | * 'what should we do if we get a hw irq event on an illegal vector'. |
| 197 | * each architecture has to answer this themselves. |
| 198 | */ |
| 199 | void ack_bad_irq(int irq) |
| 200 | { |
| 201 | printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq); |
| 202 | } |
| 203 | |
| 204 | /* |
| 205 | * change the level at which an IRQ executes |
| 206 | * - must not be called whilst interrupts are being processed! |
| 207 | */ |
| 208 | void set_intr_level(int irq, u16 level) |
| 209 | { |
| 210 | BUG_ON(in_interrupt()); |
| 211 | |
| 212 | __mask_and_set_icr(irq, GxICR_ENABLE, level); |
| 213 | } |
| 214 | |
| 215 | /* |
| 216 | * mark an interrupt to be ACK'd after interrupt handlers have been run rather |
| 217 | * than before |
| 218 | */ |
| 219 | void mn10300_set_lateack_irq_type(int irq) |
| 220 | { |
| 221 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level, |
| 222 | handle_level_irq); |
| 223 | } |
| 224 | |
| 225 | /* |
| 226 | * initialise the interrupt system |
| 227 | */ |
| 228 | void __init init_IRQ(void) |
| 229 | { |
| 230 | int irq; |
| 231 | |
| 232 | for (irq = 0; irq < NR_IRQS; irq++) |
| 233 | if (irq_get_chip(irq) == &no_irq_chip) |
| 234 | /* due to the PIC latching interrupt requests, even |
| 235 | * when the IRQ is disabled, IRQ_PENDING is superfluous |
| 236 | * and we can use handle_level_irq() for edge-triggered |
| 237 | * interrupts */ |
| 238 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge, |
| 239 | handle_level_irq); |
| 240 | |
| 241 | unit_init_IRQ(); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * handle normal device IRQs |
| 246 | */ |
| 247 | asmlinkage void do_IRQ(void) |
| 248 | { |
| 249 | unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw; |
| 250 | unsigned int cpu_id = smp_processor_id(); |
| 251 | int irq; |
| 252 | |
| 253 | sp = current_stack_pointer(); |
| 254 | BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN); |
| 255 | |
| 256 | /* make sure local_irq_enable() doesn't muck up the interrupt priority |
| 257 | * setting in EPSW */ |
| 258 | old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id]; |
| 259 | local_save_flags(epsw); |
| 260 | __mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw); |
| 261 | irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL; |
| 262 | |
| 263 | #ifdef CONFIG_MN10300_WD_TIMER |
| 264 | __IRQ_STAT(cpu_id, __irq_count)++; |
| 265 | #endif |
| 266 | |
| 267 | irq_enter(); |
| 268 | |
| 269 | for (;;) { |
| 270 | /* ask the interrupt controller for the next IRQ to process |
| 271 | * - the result we get depends on EPSW.IM |
| 272 | */ |
| 273 | irq = IAGR & IAGR_GN; |
| 274 | if (!irq) |
| 275 | break; |
| 276 | |
| 277 | local_irq_restore(irq_disabled_epsw); |
| 278 | |
| 279 | generic_handle_irq(irq >> 2); |
| 280 | |
| 281 | /* restore IRQ controls for IAGR access */ |
| 282 | local_irq_restore(epsw); |
| 283 | } |
| 284 | |
| 285 | __mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw; |
| 286 | |
| 287 | irq_exit(); |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * Display interrupt management information through /proc/interrupts |
| 292 | */ |
| 293 | int arch_show_interrupts(struct seq_file *p, int prec) |
| 294 | { |
| 295 | #ifdef CONFIG_MN10300_WD_TIMER |
| 296 | int j; |
| 297 | |
| 298 | seq_printf(p, "%*s: ", prec, "NMI"); |
| 299 | for (j = 0; j < NR_CPUS; j++) |
| 300 | if (cpu_online(j)) |
| 301 | seq_printf(p, "%10u ", nmi_count(j)); |
| 302 | seq_putc(p, '\n'); |
| 303 | #endif |
| 304 | |
| 305 | seq_printf(p, "%*s: ", prec, "ERR"); |
| 306 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | #ifdef CONFIG_HOTPLUG_CPU |
| 311 | void migrate_irqs(void) |
| 312 | { |
| 313 | int irq; |
| 314 | unsigned int self, new; |
| 315 | unsigned long flags; |
| 316 | |
| 317 | self = smp_processor_id(); |
| 318 | for (irq = 0; irq < NR_IRQS; irq++) { |
| 319 | struct irq_data *data = irq_get_irq_data(irq); |
| 320 | struct cpumask *mask = irq_data_get_affinity_mask(data); |
| 321 | |
| 322 | if (irqd_is_per_cpu(data)) |
| 323 | continue; |
| 324 | |
| 325 | if (cpumask_test_cpu(self, mask) && |
| 326 | !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) { |
| 327 | int cpu_id; |
| 328 | cpu_id = cpumask_first(cpu_online_mask); |
| 329 | cpumask_set_cpu(cpu_id, mask); |
| 330 | } |
| 331 | /* We need to operate irq_affinity_online atomically. */ |
| 332 | arch_local_cli_save(flags); |
| 333 | if (irq_affinity_online[irq] == self) { |
| 334 | u16 x, tmp; |
| 335 | |
| 336 | x = GxICR(irq); |
| 337 | GxICR(irq) = x & GxICR_LEVEL; |
| 338 | tmp = GxICR(irq); |
| 339 | |
| 340 | new = cpumask_any_and(mask, cpu_online_mask); |
| 341 | irq_affinity_online[irq] = new; |
| 342 | |
| 343 | CROSS_GxICR(irq, new) = |
| 344 | (x & GxICR_LEVEL) | GxICR_DETECT; |
| 345 | tmp = CROSS_GxICR(irq, new); |
| 346 | |
| 347 | x &= GxICR_LEVEL | GxICR_ENABLE; |
| 348 | if (GxICR(irq) & GxICR_REQUEST) |
| 349 | x |= GxICR_REQUEST | GxICR_DETECT; |
| 350 | CROSS_GxICR(irq, new) = x; |
| 351 | tmp = CROSS_GxICR(irq, new); |
| 352 | } |
| 353 | arch_local_irq_restore(flags); |
| 354 | } |
| 355 | } |
| 356 | #endif /* CONFIG_HOTPLUG_CPU */ |