| | 1 | /* |
| | 2 | * This file contains low level CPU setup functions. |
| | 3 | * Valentine Barshak <vbarshak@ru.mvista.com> |
| | 4 | * MontaVista Software, Inc (c) 2007 |
| | 5 | * |
| | 6 | * Based on cpu_setup_6xx code by |
| | 7 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| | 8 | * |
| | 9 | * This program is free software; you can redistribute it and/or |
| | 10 | * modify it under the terms of the GNU General Public License |
| | 11 | * as published by the Free Software Foundation; either version |
| | 12 | * 2 of the License, or (at your option) any later version. |
| | 13 | * |
| | 14 | */ |
| | 15 | |
| | 16 | #include <asm/processor.h> |
| | 17 | #include <asm/cputable.h> |
| | 18 | #include <asm/ppc_asm.h> |
| | 19 | |
| | 20 | _GLOBAL(__setup_cpu_440ep) |
| | 21 | b __init_fpu_44x |
| | 22 | _GLOBAL(__setup_cpu_440epx) |
| | 23 | mflr r4 |
| | 24 | bl __init_fpu_44x |
| | 25 | bl __plb_disable_wrp |
| | 26 | bl __fixup_440A_mcheck |
| | 27 | mtlr r4 |
| | 28 | blr |
| | 29 | _GLOBAL(__setup_cpu_440grx) |
| | 30 | mflr r4 |
| | 31 | bl __plb_disable_wrp |
| | 32 | bl __fixup_440A_mcheck |
| | 33 | mtlr r4 |
| | 34 | blr |
| | 35 | _GLOBAL(__setup_cpu_460ex) |
| | 36 | _GLOBAL(__setup_cpu_460gt) |
| | 37 | _GLOBAL(__setup_cpu_460sx) |
| | 38 | _GLOBAL(__setup_cpu_apm821xx) |
| | 39 | mflr r4 |
| | 40 | bl __init_fpu_44x |
| | 41 | bl __fixup_440A_mcheck |
| | 42 | mtlr r4 |
| | 43 | blr |
| | 44 | |
| | 45 | _GLOBAL(__setup_cpu_440x5) |
| | 46 | _GLOBAL(__setup_cpu_440gx) |
| | 47 | _GLOBAL(__setup_cpu_440spe) |
| | 48 | b __fixup_440A_mcheck |
| | 49 | |
| | 50 | /* enable APU between CPU and FPU */ |
| | 51 | _GLOBAL(__init_fpu_44x) |
| | 52 | mfspr r3,SPRN_CCR0 |
| | 53 | /* Clear DAPUIB flag in CCR0 */ |
| | 54 | rlwinm r3,r3,0,12,10 |
| | 55 | mtspr SPRN_CCR0,r3 |
| | 56 | isync |
| | 57 | blr |
| | 58 | |
| | 59 | /* |
| | 60 | * Workaround for the incorrect write to DDR SDRAM errata. |
| | 61 | * The write address can be corrupted during writes to |
| | 62 | * DDR SDRAM when write pipelining is enabled on PLB0. |
| | 63 | * Disable write pipelining here. |
| | 64 | */ |
| | 65 | #define DCRN_PLB4A0_ACR 0x81 |
| | 66 | |
| | 67 | _GLOBAL(__plb_disable_wrp) |
| | 68 | mfdcr r3,DCRN_PLB4A0_ACR |
| | 69 | /* clear WRP bit in PLB4A0_ACR */ |
| | 70 | rlwinm r3,r3,0,8,6 |
| | 71 | mtdcr DCRN_PLB4A0_ACR,r3 |
| | 72 | isync |
| | 73 | blr |
| | 74 | |
projects / deliverable / linux.git / blame_incremental