| 1 | /* |
| 2 | * Performance counter support - powerpc architecture code |
| 3 | * |
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/sched.h> |
| 13 | #include <linux/perf_counter.h> |
| 14 | #include <linux/percpu.h> |
| 15 | #include <linux/hardirq.h> |
| 16 | #include <asm/reg.h> |
| 17 | #include <asm/pmc.h> |
| 18 | #include <asm/machdep.h> |
| 19 | #include <asm/firmware.h> |
| 20 | #include <asm/ptrace.h> |
| 21 | |
| 22 | struct cpu_hw_counters { |
| 23 | int n_counters; |
| 24 | int n_percpu; |
| 25 | int disabled; |
| 26 | int n_added; |
| 27 | int n_limited; |
| 28 | u8 pmcs_enabled; |
| 29 | struct perf_counter *counter[MAX_HWCOUNTERS]; |
| 30 | u64 events[MAX_HWCOUNTERS]; |
| 31 | unsigned int flags[MAX_HWCOUNTERS]; |
| 32 | u64 mmcr[3]; |
| 33 | struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
| 34 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; |
| 35 | }; |
| 36 | DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); |
| 37 | |
| 38 | struct power_pmu *ppmu; |
| 39 | |
| 40 | /* |
| 41 | * Normally, to ignore kernel events we set the FCS (freeze counters |
| 42 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
| 43 | * hypervisor bit set in the MSR, or if we are running on a processor |
| 44 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), |
| 45 | * then we need to use the FCHV bit to ignore kernel events. |
| 46 | */ |
| 47 | static unsigned int freeze_counters_kernel = MMCR0_FCS; |
| 48 | |
| 49 | static void perf_counter_interrupt(struct pt_regs *regs); |
| 50 | |
| 51 | void perf_counter_print_debug(void) |
| 52 | { |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Read one performance monitor counter (PMC). |
| 57 | */ |
| 58 | static unsigned long read_pmc(int idx) |
| 59 | { |
| 60 | unsigned long val; |
| 61 | |
| 62 | switch (idx) { |
| 63 | case 1: |
| 64 | val = mfspr(SPRN_PMC1); |
| 65 | break; |
| 66 | case 2: |
| 67 | val = mfspr(SPRN_PMC2); |
| 68 | break; |
| 69 | case 3: |
| 70 | val = mfspr(SPRN_PMC3); |
| 71 | break; |
| 72 | case 4: |
| 73 | val = mfspr(SPRN_PMC4); |
| 74 | break; |
| 75 | case 5: |
| 76 | val = mfspr(SPRN_PMC5); |
| 77 | break; |
| 78 | case 6: |
| 79 | val = mfspr(SPRN_PMC6); |
| 80 | break; |
| 81 | case 7: |
| 82 | val = mfspr(SPRN_PMC7); |
| 83 | break; |
| 84 | case 8: |
| 85 | val = mfspr(SPRN_PMC8); |
| 86 | break; |
| 87 | default: |
| 88 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); |
| 89 | val = 0; |
| 90 | } |
| 91 | return val; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Write one PMC. |
| 96 | */ |
| 97 | static void write_pmc(int idx, unsigned long val) |
| 98 | { |
| 99 | switch (idx) { |
| 100 | case 1: |
| 101 | mtspr(SPRN_PMC1, val); |
| 102 | break; |
| 103 | case 2: |
| 104 | mtspr(SPRN_PMC2, val); |
| 105 | break; |
| 106 | case 3: |
| 107 | mtspr(SPRN_PMC3, val); |
| 108 | break; |
| 109 | case 4: |
| 110 | mtspr(SPRN_PMC4, val); |
| 111 | break; |
| 112 | case 5: |
| 113 | mtspr(SPRN_PMC5, val); |
| 114 | break; |
| 115 | case 6: |
| 116 | mtspr(SPRN_PMC6, val); |
| 117 | break; |
| 118 | case 7: |
| 119 | mtspr(SPRN_PMC7, val); |
| 120 | break; |
| 121 | case 8: |
| 122 | mtspr(SPRN_PMC8, val); |
| 123 | break; |
| 124 | default: |
| 125 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | /* |
| 130 | * Check if a set of events can all go on the PMU at once. |
| 131 | * If they can't, this will look at alternative codes for the events |
| 132 | * and see if any combination of alternative codes is feasible. |
| 133 | * The feasible set is returned in event[]. |
| 134 | */ |
| 135 | static int power_check_constraints(u64 event[], unsigned int cflags[], |
| 136 | int n_ev) |
| 137 | { |
| 138 | u64 mask, value, nv; |
| 139 | u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; |
| 140 | u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; |
| 141 | u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; |
| 142 | u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; |
| 143 | int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; |
| 144 | int i, j; |
| 145 | u64 addf = ppmu->add_fields; |
| 146 | u64 tadd = ppmu->test_adder; |
| 147 | |
| 148 | if (n_ev > ppmu->n_counter) |
| 149 | return -1; |
| 150 | |
| 151 | /* First see if the events will go on as-is */ |
| 152 | for (i = 0; i < n_ev; ++i) { |
| 153 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
| 154 | && !ppmu->limited_pmc_event(event[i])) { |
| 155 | ppmu->get_alternatives(event[i], cflags[i], |
| 156 | alternatives[i]); |
| 157 | event[i] = alternatives[i][0]; |
| 158 | } |
| 159 | if (ppmu->get_constraint(event[i], &amasks[i][0], |
| 160 | &avalues[i][0])) |
| 161 | return -1; |
| 162 | } |
| 163 | value = mask = 0; |
| 164 | for (i = 0; i < n_ev; ++i) { |
| 165 | nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf); |
| 166 | if ((((nv + tadd) ^ value) & mask) != 0 || |
| 167 | (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0) |
| 168 | break; |
| 169 | value = nv; |
| 170 | mask |= amasks[i][0]; |
| 171 | } |
| 172 | if (i == n_ev) |
| 173 | return 0; /* all OK */ |
| 174 | |
| 175 | /* doesn't work, gather alternatives... */ |
| 176 | if (!ppmu->get_alternatives) |
| 177 | return -1; |
| 178 | for (i = 0; i < n_ev; ++i) { |
| 179 | choice[i] = 0; |
| 180 | n_alt[i] = ppmu->get_alternatives(event[i], cflags[i], |
| 181 | alternatives[i]); |
| 182 | for (j = 1; j < n_alt[i]; ++j) |
| 183 | ppmu->get_constraint(alternatives[i][j], |
| 184 | &amasks[i][j], &avalues[i][j]); |
| 185 | } |
| 186 | |
| 187 | /* enumerate all possibilities and see if any will work */ |
| 188 | i = 0; |
| 189 | j = -1; |
| 190 | value = mask = nv = 0; |
| 191 | while (i < n_ev) { |
| 192 | if (j >= 0) { |
| 193 | /* we're backtracking, restore context */ |
| 194 | value = svalues[i]; |
| 195 | mask = smasks[i]; |
| 196 | j = choice[i]; |
| 197 | } |
| 198 | /* |
| 199 | * See if any alternative k for event i, |
| 200 | * where k > j, will satisfy the constraints. |
| 201 | */ |
| 202 | while (++j < n_alt[i]) { |
| 203 | nv = (value | avalues[i][j]) + |
| 204 | (value & avalues[i][j] & addf); |
| 205 | if ((((nv + tadd) ^ value) & mask) == 0 && |
| 206 | (((nv + tadd) ^ avalues[i][j]) |
| 207 | & amasks[i][j]) == 0) |
| 208 | break; |
| 209 | } |
| 210 | if (j >= n_alt[i]) { |
| 211 | /* |
| 212 | * No feasible alternative, backtrack |
| 213 | * to event i-1 and continue enumerating its |
| 214 | * alternatives from where we got up to. |
| 215 | */ |
| 216 | if (--i < 0) |
| 217 | return -1; |
| 218 | } else { |
| 219 | /* |
| 220 | * Found a feasible alternative for event i, |
| 221 | * remember where we got up to with this event, |
| 222 | * go on to the next event, and start with |
| 223 | * the first alternative for it. |
| 224 | */ |
| 225 | choice[i] = j; |
| 226 | svalues[i] = value; |
| 227 | smasks[i] = mask; |
| 228 | value = nv; |
| 229 | mask |= amasks[i][j]; |
| 230 | ++i; |
| 231 | j = -1; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | /* OK, we have a feasible combination, tell the caller the solution */ |
| 236 | for (i = 0; i < n_ev; ++i) |
| 237 | event[i] = alternatives[i][choice[i]]; |
| 238 | return 0; |
| 239 | } |
| 240 | |
| 241 | /* |
| 242 | * Check if newly-added counters have consistent settings for |
| 243 | * exclude_{user,kernel,hv} with each other and any previously |
| 244 | * added counters. |
| 245 | */ |
| 246 | static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[], |
| 247 | int n_prev, int n_new) |
| 248 | { |
| 249 | int eu = 0, ek = 0, eh = 0; |
| 250 | int i, n, first; |
| 251 | struct perf_counter *counter; |
| 252 | |
| 253 | n = n_prev + n_new; |
| 254 | if (n <= 1) |
| 255 | return 0; |
| 256 | |
| 257 | first = 1; |
| 258 | for (i = 0; i < n; ++i) { |
| 259 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { |
| 260 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; |
| 261 | continue; |
| 262 | } |
| 263 | counter = ctrs[i]; |
| 264 | if (first) { |
| 265 | eu = counter->attr.exclude_user; |
| 266 | ek = counter->attr.exclude_kernel; |
| 267 | eh = counter->attr.exclude_hv; |
| 268 | first = 0; |
| 269 | } else if (counter->attr.exclude_user != eu || |
| 270 | counter->attr.exclude_kernel != ek || |
| 271 | counter->attr.exclude_hv != eh) { |
| 272 | return -EAGAIN; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | if (eu || ek || eh) |
| 277 | for (i = 0; i < n; ++i) |
| 278 | if (cflags[i] & PPMU_LIMITED_PMC_OK) |
| 279 | cflags[i] |= PPMU_LIMITED_PMC_REQD; |
| 280 | |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | static void power_pmu_read(struct perf_counter *counter) |
| 285 | { |
| 286 | long val, delta, prev; |
| 287 | |
| 288 | if (!counter->hw.idx) |
| 289 | return; |
| 290 | /* |
| 291 | * Performance monitor interrupts come even when interrupts |
| 292 | * are soft-disabled, as long as interrupts are hard-enabled. |
| 293 | * Therefore we treat them like NMIs. |
| 294 | */ |
| 295 | do { |
| 296 | prev = atomic64_read(&counter->hw.prev_count); |
| 297 | barrier(); |
| 298 | val = read_pmc(counter->hw.idx); |
| 299 | } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev); |
| 300 | |
| 301 | /* The counters are only 32 bits wide */ |
| 302 | delta = (val - prev) & 0xfffffffful; |
| 303 | atomic64_add(delta, &counter->count); |
| 304 | atomic64_sub(delta, &counter->hw.period_left); |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * On some machines, PMC5 and PMC6 can't be written, don't respect |
| 309 | * the freeze conditions, and don't generate interrupts. This tells |
| 310 | * us if `counter' is using such a PMC. |
| 311 | */ |
| 312 | static int is_limited_pmc(int pmcnum) |
| 313 | { |
| 314 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
| 315 | && (pmcnum == 5 || pmcnum == 6); |
| 316 | } |
| 317 | |
| 318 | static void freeze_limited_counters(struct cpu_hw_counters *cpuhw, |
| 319 | unsigned long pmc5, unsigned long pmc6) |
| 320 | { |
| 321 | struct perf_counter *counter; |
| 322 | u64 val, prev, delta; |
| 323 | int i; |
| 324 | |
| 325 | for (i = 0; i < cpuhw->n_limited; ++i) { |
| 326 | counter = cpuhw->limited_counter[i]; |
| 327 | if (!counter->hw.idx) |
| 328 | continue; |
| 329 | val = (counter->hw.idx == 5) ? pmc5 : pmc6; |
| 330 | prev = atomic64_read(&counter->hw.prev_count); |
| 331 | counter->hw.idx = 0; |
| 332 | delta = (val - prev) & 0xfffffffful; |
| 333 | atomic64_add(delta, &counter->count); |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | static void thaw_limited_counters(struct cpu_hw_counters *cpuhw, |
| 338 | unsigned long pmc5, unsigned long pmc6) |
| 339 | { |
| 340 | struct perf_counter *counter; |
| 341 | u64 val; |
| 342 | int i; |
| 343 | |
| 344 | for (i = 0; i < cpuhw->n_limited; ++i) { |
| 345 | counter = cpuhw->limited_counter[i]; |
| 346 | counter->hw.idx = cpuhw->limited_hwidx[i]; |
| 347 | val = (counter->hw.idx == 5) ? pmc5 : pmc6; |
| 348 | atomic64_set(&counter->hw.prev_count, val); |
| 349 | perf_counter_update_userpage(counter); |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | /* |
| 354 | * Since limited counters don't respect the freeze conditions, we |
| 355 | * have to read them immediately after freezing or unfreezing the |
| 356 | * other counters. We try to keep the values from the limited |
| 357 | * counters as consistent as possible by keeping the delay (in |
| 358 | * cycles and instructions) between freezing/unfreezing and reading |
| 359 | * the limited counters as small and consistent as possible. |
| 360 | * Therefore, if any limited counters are in use, we read them |
| 361 | * both, and always in the same order, to minimize variability, |
| 362 | * and do it inside the same asm that writes MMCR0. |
| 363 | */ |
| 364 | static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) |
| 365 | { |
| 366 | unsigned long pmc5, pmc6; |
| 367 | |
| 368 | if (!cpuhw->n_limited) { |
| 369 | mtspr(SPRN_MMCR0, mmcr0); |
| 370 | return; |
| 371 | } |
| 372 | |
| 373 | /* |
| 374 | * Write MMCR0, then read PMC5 and PMC6 immediately. |
| 375 | * To ensure we don't get a performance monitor interrupt |
| 376 | * between writing MMCR0 and freezing/thawing the limited |
| 377 | * counters, we first write MMCR0 with the counter overflow |
| 378 | * interrupt enable bits turned off. |
| 379 | */ |
| 380 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" |
| 381 | : "=&r" (pmc5), "=&r" (pmc6) |
| 382 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
| 383 | "i" (SPRN_MMCR0), |
| 384 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
| 385 | |
| 386 | if (mmcr0 & MMCR0_FC) |
| 387 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
| 388 | else |
| 389 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
| 390 | |
| 391 | /* |
| 392 | * Write the full MMCR0 including the counter overflow interrupt |
| 393 | * enable bits, if necessary. |
| 394 | */ |
| 395 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) |
| 396 | mtspr(SPRN_MMCR0, mmcr0); |
| 397 | } |
| 398 | |
| 399 | /* |
| 400 | * Disable all counters to prevent PMU interrupts and to allow |
| 401 | * counters to be added or removed. |
| 402 | */ |
| 403 | void hw_perf_disable(void) |
| 404 | { |
| 405 | struct cpu_hw_counters *cpuhw; |
| 406 | unsigned long ret; |
| 407 | unsigned long flags; |
| 408 | |
| 409 | local_irq_save(flags); |
| 410 | cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 411 | |
| 412 | ret = cpuhw->disabled; |
| 413 | if (!ret) { |
| 414 | cpuhw->disabled = 1; |
| 415 | cpuhw->n_added = 0; |
| 416 | |
| 417 | /* |
| 418 | * Check if we ever enabled the PMU on this cpu. |
| 419 | */ |
| 420 | if (!cpuhw->pmcs_enabled) { |
| 421 | if (ppc_md.enable_pmcs) |
| 422 | ppc_md.enable_pmcs(); |
| 423 | cpuhw->pmcs_enabled = 1; |
| 424 | } |
| 425 | |
| 426 | /* |
| 427 | * Disable instruction sampling if it was enabled |
| 428 | */ |
| 429 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { |
| 430 | mtspr(SPRN_MMCRA, |
| 431 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
| 432 | mb(); |
| 433 | } |
| 434 | |
| 435 | /* |
| 436 | * Set the 'freeze counters' bit. |
| 437 | * The barrier is to make sure the mtspr has been |
| 438 | * executed and the PMU has frozen the counters |
| 439 | * before we return. |
| 440 | */ |
| 441 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
| 442 | mb(); |
| 443 | } |
| 444 | local_irq_restore(flags); |
| 445 | } |
| 446 | |
| 447 | /* |
| 448 | * Re-enable all counters if disable == 0. |
| 449 | * If we were previously disabled and counters were added, then |
| 450 | * put the new config on the PMU. |
| 451 | */ |
| 452 | void hw_perf_enable(void) |
| 453 | { |
| 454 | struct perf_counter *counter; |
| 455 | struct cpu_hw_counters *cpuhw; |
| 456 | unsigned long flags; |
| 457 | long i; |
| 458 | unsigned long val; |
| 459 | s64 left; |
| 460 | unsigned int hwc_index[MAX_HWCOUNTERS]; |
| 461 | int n_lim; |
| 462 | int idx; |
| 463 | |
| 464 | local_irq_save(flags); |
| 465 | cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 466 | if (!cpuhw->disabled) { |
| 467 | local_irq_restore(flags); |
| 468 | return; |
| 469 | } |
| 470 | cpuhw->disabled = 0; |
| 471 | |
| 472 | /* |
| 473 | * If we didn't change anything, or only removed counters, |
| 474 | * no need to recalculate MMCR* settings and reset the PMCs. |
| 475 | * Just reenable the PMU with the current MMCR* settings |
| 476 | * (possibly updated for removal of counters). |
| 477 | */ |
| 478 | if (!cpuhw->n_added) { |
| 479 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
| 480 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
| 481 | if (cpuhw->n_counters == 0) |
| 482 | get_lppaca()->pmcregs_in_use = 0; |
| 483 | goto out_enable; |
| 484 | } |
| 485 | |
| 486 | /* |
| 487 | * Compute MMCR* values for the new set of counters |
| 488 | */ |
| 489 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index, |
| 490 | cpuhw->mmcr)) { |
| 491 | /* shouldn't ever get here */ |
| 492 | printk(KERN_ERR "oops compute_mmcr failed\n"); |
| 493 | goto out; |
| 494 | } |
| 495 | |
| 496 | /* |
| 497 | * Add in MMCR0 freeze bits corresponding to the |
| 498 | * attr.exclude_* bits for the first counter. |
| 499 | * We have already checked that all counters have the |
| 500 | * same values for these bits as the first counter. |
| 501 | */ |
| 502 | counter = cpuhw->counter[0]; |
| 503 | if (counter->attr.exclude_user) |
| 504 | cpuhw->mmcr[0] |= MMCR0_FCP; |
| 505 | if (counter->attr.exclude_kernel) |
| 506 | cpuhw->mmcr[0] |= freeze_counters_kernel; |
| 507 | if (counter->attr.exclude_hv) |
| 508 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
| 509 | |
| 510 | /* |
| 511 | * Write the new configuration to MMCR* with the freeze |
| 512 | * bit set and set the hardware counters to their initial values. |
| 513 | * Then unfreeze the counters. |
| 514 | */ |
| 515 | get_lppaca()->pmcregs_in_use = 1; |
| 516 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
| 517 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
| 518 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) |
| 519 | | MMCR0_FC); |
| 520 | |
| 521 | /* |
| 522 | * Read off any pre-existing counters that need to move |
| 523 | * to another PMC. |
| 524 | */ |
| 525 | for (i = 0; i < cpuhw->n_counters; ++i) { |
| 526 | counter = cpuhw->counter[i]; |
| 527 | if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) { |
| 528 | power_pmu_read(counter); |
| 529 | write_pmc(counter->hw.idx, 0); |
| 530 | counter->hw.idx = 0; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * Initialize the PMCs for all the new and moved counters. |
| 536 | */ |
| 537 | cpuhw->n_limited = n_lim = 0; |
| 538 | for (i = 0; i < cpuhw->n_counters; ++i) { |
| 539 | counter = cpuhw->counter[i]; |
| 540 | if (counter->hw.idx) |
| 541 | continue; |
| 542 | idx = hwc_index[i] + 1; |
| 543 | if (is_limited_pmc(idx)) { |
| 544 | cpuhw->limited_counter[n_lim] = counter; |
| 545 | cpuhw->limited_hwidx[n_lim] = idx; |
| 546 | ++n_lim; |
| 547 | continue; |
| 548 | } |
| 549 | val = 0; |
| 550 | if (counter->hw.sample_period) { |
| 551 | left = atomic64_read(&counter->hw.period_left); |
| 552 | if (left < 0x80000000L) |
| 553 | val = 0x80000000L - left; |
| 554 | } |
| 555 | atomic64_set(&counter->hw.prev_count, val); |
| 556 | counter->hw.idx = idx; |
| 557 | write_pmc(idx, val); |
| 558 | perf_counter_update_userpage(counter); |
| 559 | } |
| 560 | cpuhw->n_limited = n_lim; |
| 561 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
| 562 | |
| 563 | out_enable: |
| 564 | mb(); |
| 565 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
| 566 | |
| 567 | /* |
| 568 | * Enable instruction sampling if necessary |
| 569 | */ |
| 570 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { |
| 571 | mb(); |
| 572 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); |
| 573 | } |
| 574 | |
| 575 | out: |
| 576 | local_irq_restore(flags); |
| 577 | } |
| 578 | |
| 579 | static int collect_events(struct perf_counter *group, int max_count, |
| 580 | struct perf_counter *ctrs[], u64 *events, |
| 581 | unsigned int *flags) |
| 582 | { |
| 583 | int n = 0; |
| 584 | struct perf_counter *counter; |
| 585 | |
| 586 | if (!is_software_counter(group)) { |
| 587 | if (n >= max_count) |
| 588 | return -1; |
| 589 | ctrs[n] = group; |
| 590 | flags[n] = group->hw.counter_base; |
| 591 | events[n++] = group->hw.config; |
| 592 | } |
| 593 | list_for_each_entry(counter, &group->sibling_list, list_entry) { |
| 594 | if (!is_software_counter(counter) && |
| 595 | counter->state != PERF_COUNTER_STATE_OFF) { |
| 596 | if (n >= max_count) |
| 597 | return -1; |
| 598 | ctrs[n] = counter; |
| 599 | flags[n] = counter->hw.counter_base; |
| 600 | events[n++] = counter->hw.config; |
| 601 | } |
| 602 | } |
| 603 | return n; |
| 604 | } |
| 605 | |
| 606 | static void counter_sched_in(struct perf_counter *counter, int cpu) |
| 607 | { |
| 608 | counter->state = PERF_COUNTER_STATE_ACTIVE; |
| 609 | counter->oncpu = cpu; |
| 610 | counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped; |
| 611 | if (is_software_counter(counter)) |
| 612 | counter->pmu->enable(counter); |
| 613 | } |
| 614 | |
| 615 | /* |
| 616 | * Called to enable a whole group of counters. |
| 617 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. |
| 618 | * Assumes the caller has disabled interrupts and has |
| 619 | * frozen the PMU with hw_perf_save_disable. |
| 620 | */ |
| 621 | int hw_perf_group_sched_in(struct perf_counter *group_leader, |
| 622 | struct perf_cpu_context *cpuctx, |
| 623 | struct perf_counter_context *ctx, int cpu) |
| 624 | { |
| 625 | struct cpu_hw_counters *cpuhw; |
| 626 | long i, n, n0; |
| 627 | struct perf_counter *sub; |
| 628 | |
| 629 | cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 630 | n0 = cpuhw->n_counters; |
| 631 | n = collect_events(group_leader, ppmu->n_counter - n0, |
| 632 | &cpuhw->counter[n0], &cpuhw->events[n0], |
| 633 | &cpuhw->flags[n0]); |
| 634 | if (n < 0) |
| 635 | return -EAGAIN; |
| 636 | if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n)) |
| 637 | return -EAGAIN; |
| 638 | i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0); |
| 639 | if (i < 0) |
| 640 | return -EAGAIN; |
| 641 | cpuhw->n_counters = n0 + n; |
| 642 | cpuhw->n_added += n; |
| 643 | |
| 644 | /* |
| 645 | * OK, this group can go on; update counter states etc., |
| 646 | * and enable any software counters |
| 647 | */ |
| 648 | for (i = n0; i < n0 + n; ++i) |
| 649 | cpuhw->counter[i]->hw.config = cpuhw->events[i]; |
| 650 | cpuctx->active_oncpu += n; |
| 651 | n = 1; |
| 652 | counter_sched_in(group_leader, cpu); |
| 653 | list_for_each_entry(sub, &group_leader->sibling_list, list_entry) { |
| 654 | if (sub->state != PERF_COUNTER_STATE_OFF) { |
| 655 | counter_sched_in(sub, cpu); |
| 656 | ++n; |
| 657 | } |
| 658 | } |
| 659 | ctx->nr_active += n; |
| 660 | |
| 661 | return 1; |
| 662 | } |
| 663 | |
| 664 | /* |
| 665 | * Add a counter to the PMU. |
| 666 | * If all counters are not already frozen, then we disable and |
| 667 | * re-enable the PMU in order to get hw_perf_enable to do the |
| 668 | * actual work of reconfiguring the PMU. |
| 669 | */ |
| 670 | static int power_pmu_enable(struct perf_counter *counter) |
| 671 | { |
| 672 | struct cpu_hw_counters *cpuhw; |
| 673 | unsigned long flags; |
| 674 | int n0; |
| 675 | int ret = -EAGAIN; |
| 676 | |
| 677 | local_irq_save(flags); |
| 678 | perf_disable(); |
| 679 | |
| 680 | /* |
| 681 | * Add the counter to the list (if there is room) |
| 682 | * and check whether the total set is still feasible. |
| 683 | */ |
| 684 | cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 685 | n0 = cpuhw->n_counters; |
| 686 | if (n0 >= ppmu->n_counter) |
| 687 | goto out; |
| 688 | cpuhw->counter[n0] = counter; |
| 689 | cpuhw->events[n0] = counter->hw.config; |
| 690 | cpuhw->flags[n0] = counter->hw.counter_base; |
| 691 | if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1)) |
| 692 | goto out; |
| 693 | if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1)) |
| 694 | goto out; |
| 695 | |
| 696 | counter->hw.config = cpuhw->events[n0]; |
| 697 | ++cpuhw->n_counters; |
| 698 | ++cpuhw->n_added; |
| 699 | |
| 700 | ret = 0; |
| 701 | out: |
| 702 | perf_enable(); |
| 703 | local_irq_restore(flags); |
| 704 | return ret; |
| 705 | } |
| 706 | |
| 707 | /* |
| 708 | * Remove a counter from the PMU. |
| 709 | */ |
| 710 | static void power_pmu_disable(struct perf_counter *counter) |
| 711 | { |
| 712 | struct cpu_hw_counters *cpuhw; |
| 713 | long i; |
| 714 | unsigned long flags; |
| 715 | |
| 716 | local_irq_save(flags); |
| 717 | perf_disable(); |
| 718 | |
| 719 | power_pmu_read(counter); |
| 720 | |
| 721 | cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 722 | for (i = 0; i < cpuhw->n_counters; ++i) { |
| 723 | if (counter == cpuhw->counter[i]) { |
| 724 | while (++i < cpuhw->n_counters) |
| 725 | cpuhw->counter[i-1] = cpuhw->counter[i]; |
| 726 | --cpuhw->n_counters; |
| 727 | ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr); |
| 728 | if (counter->hw.idx) { |
| 729 | write_pmc(counter->hw.idx, 0); |
| 730 | counter->hw.idx = 0; |
| 731 | } |
| 732 | perf_counter_update_userpage(counter); |
| 733 | break; |
| 734 | } |
| 735 | } |
| 736 | for (i = 0; i < cpuhw->n_limited; ++i) |
| 737 | if (counter == cpuhw->limited_counter[i]) |
| 738 | break; |
| 739 | if (i < cpuhw->n_limited) { |
| 740 | while (++i < cpuhw->n_limited) { |
| 741 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
| 742 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
| 743 | } |
| 744 | --cpuhw->n_limited; |
| 745 | } |
| 746 | if (cpuhw->n_counters == 0) { |
| 747 | /* disable exceptions if no counters are running */ |
| 748 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
| 749 | } |
| 750 | |
| 751 | perf_enable(); |
| 752 | local_irq_restore(flags); |
| 753 | } |
| 754 | |
| 755 | /* |
| 756 | * Re-enable interrupts on a counter after they were throttled |
| 757 | * because they were coming too fast. |
| 758 | */ |
| 759 | static void power_pmu_unthrottle(struct perf_counter *counter) |
| 760 | { |
| 761 | s64 val, left; |
| 762 | unsigned long flags; |
| 763 | |
| 764 | if (!counter->hw.idx || !counter->hw.sample_period) |
| 765 | return; |
| 766 | local_irq_save(flags); |
| 767 | perf_disable(); |
| 768 | power_pmu_read(counter); |
| 769 | left = counter->hw.sample_period; |
| 770 | counter->hw.last_period = left; |
| 771 | val = 0; |
| 772 | if (left < 0x80000000L) |
| 773 | val = 0x80000000L - left; |
| 774 | write_pmc(counter->hw.idx, val); |
| 775 | atomic64_set(&counter->hw.prev_count, val); |
| 776 | atomic64_set(&counter->hw.period_left, left); |
| 777 | perf_counter_update_userpage(counter); |
| 778 | perf_enable(); |
| 779 | local_irq_restore(flags); |
| 780 | } |
| 781 | |
| 782 | struct pmu power_pmu = { |
| 783 | .enable = power_pmu_enable, |
| 784 | .disable = power_pmu_disable, |
| 785 | .read = power_pmu_read, |
| 786 | .unthrottle = power_pmu_unthrottle, |
| 787 | }; |
| 788 | |
| 789 | /* |
| 790 | * Return 1 if we might be able to put counter on a limited PMC, |
| 791 | * or 0 if not. |
| 792 | * A counter can only go on a limited PMC if it counts something |
| 793 | * that a limited PMC can count, doesn't require interrupts, and |
| 794 | * doesn't exclude any processor mode. |
| 795 | */ |
| 796 | static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev, |
| 797 | unsigned int flags) |
| 798 | { |
| 799 | int n; |
| 800 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
| 801 | |
| 802 | if (counter->attr.exclude_user |
| 803 | || counter->attr.exclude_kernel |
| 804 | || counter->attr.exclude_hv |
| 805 | || counter->attr.sample_period) |
| 806 | return 0; |
| 807 | |
| 808 | if (ppmu->limited_pmc_event(ev)) |
| 809 | return 1; |
| 810 | |
| 811 | /* |
| 812 | * The requested event isn't on a limited PMC already; |
| 813 | * see if any alternative code goes on a limited PMC. |
| 814 | */ |
| 815 | if (!ppmu->get_alternatives) |
| 816 | return 0; |
| 817 | |
| 818 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; |
| 819 | n = ppmu->get_alternatives(ev, flags, alt); |
| 820 | |
| 821 | return n > 0; |
| 822 | } |
| 823 | |
| 824 | /* |
| 825 | * Find an alternative event that goes on a normal PMC, if possible, |
| 826 | * and return the event code, or 0 if there is no such alternative. |
| 827 | * (Note: event code 0 is "don't count" on all machines.) |
| 828 | */ |
| 829 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
| 830 | { |
| 831 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
| 832 | int n; |
| 833 | |
| 834 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); |
| 835 | n = ppmu->get_alternatives(ev, flags, alt); |
| 836 | if (!n) |
| 837 | return 0; |
| 838 | return alt[0]; |
| 839 | } |
| 840 | |
| 841 | /* Number of perf_counters counting hardware events */ |
| 842 | static atomic_t num_counters; |
| 843 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
| 844 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 845 | |
| 846 | /* |
| 847 | * Release the PMU if this is the last perf_counter. |
| 848 | */ |
| 849 | static void hw_perf_counter_destroy(struct perf_counter *counter) |
| 850 | { |
| 851 | if (!atomic_add_unless(&num_counters, -1, 1)) { |
| 852 | mutex_lock(&pmc_reserve_mutex); |
| 853 | if (atomic_dec_return(&num_counters) == 0) |
| 854 | release_pmc_hardware(); |
| 855 | mutex_unlock(&pmc_reserve_mutex); |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | /* |
| 860 | * Translate a generic cache event config to a raw event code. |
| 861 | */ |
| 862 | static int hw_perf_cache_event(u64 config, u64 *eventp) |
| 863 | { |
| 864 | unsigned long type, op, result; |
| 865 | int ev; |
| 866 | |
| 867 | if (!ppmu->cache_events) |
| 868 | return -EINVAL; |
| 869 | |
| 870 | /* unpack config */ |
| 871 | type = config & 0xff; |
| 872 | op = (config >> 8) & 0xff; |
| 873 | result = (config >> 16) & 0xff; |
| 874 | |
| 875 | if (type >= PERF_COUNT_HW_CACHE_MAX || |
| 876 | op >= PERF_COUNT_HW_CACHE_OP_MAX || |
| 877 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 878 | return -EINVAL; |
| 879 | |
| 880 | ev = (*ppmu->cache_events)[type][op][result]; |
| 881 | if (ev == 0) |
| 882 | return -EOPNOTSUPP; |
| 883 | if (ev == -1) |
| 884 | return -EINVAL; |
| 885 | *eventp = ev; |
| 886 | return 0; |
| 887 | } |
| 888 | |
| 889 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
| 890 | { |
| 891 | u64 ev; |
| 892 | unsigned long flags; |
| 893 | struct perf_counter *ctrs[MAX_HWCOUNTERS]; |
| 894 | u64 events[MAX_HWCOUNTERS]; |
| 895 | unsigned int cflags[MAX_HWCOUNTERS]; |
| 896 | int n; |
| 897 | int err; |
| 898 | |
| 899 | if (!ppmu) |
| 900 | return ERR_PTR(-ENXIO); |
| 901 | switch (counter->attr.type) { |
| 902 | case PERF_TYPE_HARDWARE: |
| 903 | ev = counter->attr.config; |
| 904 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
| 905 | return ERR_PTR(-EOPNOTSUPP); |
| 906 | ev = ppmu->generic_events[ev]; |
| 907 | break; |
| 908 | case PERF_TYPE_HW_CACHE: |
| 909 | err = hw_perf_cache_event(counter->attr.config, &ev); |
| 910 | if (err) |
| 911 | return ERR_PTR(err); |
| 912 | break; |
| 913 | case PERF_TYPE_RAW: |
| 914 | ev = counter->attr.config; |
| 915 | break; |
| 916 | } |
| 917 | counter->hw.config_base = ev; |
| 918 | counter->hw.idx = 0; |
| 919 | |
| 920 | /* |
| 921 | * If we are not running on a hypervisor, force the |
| 922 | * exclude_hv bit to 0 so that we don't care what |
| 923 | * the user set it to. |
| 924 | */ |
| 925 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
| 926 | counter->attr.exclude_hv = 0; |
| 927 | |
| 928 | /* |
| 929 | * If this is a per-task counter, then we can use |
| 930 | * PM_RUN_* events interchangeably with their non RUN_* |
| 931 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. |
| 932 | * XXX we should check if the task is an idle task. |
| 933 | */ |
| 934 | flags = 0; |
| 935 | if (counter->ctx->task) |
| 936 | flags |= PPMU_ONLY_COUNT_RUN; |
| 937 | |
| 938 | /* |
| 939 | * If this machine has limited counters, check whether this |
| 940 | * event could go on a limited counter. |
| 941 | */ |
| 942 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
| 943 | if (can_go_on_limited_pmc(counter, ev, flags)) { |
| 944 | flags |= PPMU_LIMITED_PMC_OK; |
| 945 | } else if (ppmu->limited_pmc_event(ev)) { |
| 946 | /* |
| 947 | * The requested event is on a limited PMC, |
| 948 | * but we can't use a limited PMC; see if any |
| 949 | * alternative goes on a normal PMC. |
| 950 | */ |
| 951 | ev = normal_pmc_alternative(ev, flags); |
| 952 | if (!ev) |
| 953 | return ERR_PTR(-EINVAL); |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | /* |
| 958 | * If this is in a group, check if it can go on with all the |
| 959 | * other hardware counters in the group. We assume the counter |
| 960 | * hasn't been linked into its leader's sibling list at this point. |
| 961 | */ |
| 962 | n = 0; |
| 963 | if (counter->group_leader != counter) { |
| 964 | n = collect_events(counter->group_leader, ppmu->n_counter - 1, |
| 965 | ctrs, events, cflags); |
| 966 | if (n < 0) |
| 967 | return ERR_PTR(-EINVAL); |
| 968 | } |
| 969 | events[n] = ev; |
| 970 | ctrs[n] = counter; |
| 971 | cflags[n] = flags; |
| 972 | if (check_excludes(ctrs, cflags, n, 1)) |
| 973 | return ERR_PTR(-EINVAL); |
| 974 | if (power_check_constraints(events, cflags, n + 1)) |
| 975 | return ERR_PTR(-EINVAL); |
| 976 | |
| 977 | counter->hw.config = events[n]; |
| 978 | counter->hw.counter_base = cflags[n]; |
| 979 | counter->hw.last_period = counter->hw.sample_period; |
| 980 | atomic64_set(&counter->hw.period_left, counter->hw.last_period); |
| 981 | |
| 982 | /* |
| 983 | * See if we need to reserve the PMU. |
| 984 | * If no counters are currently in use, then we have to take a |
| 985 | * mutex to ensure that we don't race with another task doing |
| 986 | * reserve_pmc_hardware or release_pmc_hardware. |
| 987 | */ |
| 988 | err = 0; |
| 989 | if (!atomic_inc_not_zero(&num_counters)) { |
| 990 | mutex_lock(&pmc_reserve_mutex); |
| 991 | if (atomic_read(&num_counters) == 0 && |
| 992 | reserve_pmc_hardware(perf_counter_interrupt)) |
| 993 | err = -EBUSY; |
| 994 | else |
| 995 | atomic_inc(&num_counters); |
| 996 | mutex_unlock(&pmc_reserve_mutex); |
| 997 | } |
| 998 | counter->destroy = hw_perf_counter_destroy; |
| 999 | |
| 1000 | if (err) |
| 1001 | return ERR_PTR(err); |
| 1002 | return &power_pmu; |
| 1003 | } |
| 1004 | |
| 1005 | /* |
| 1006 | * A counter has overflowed; update its count and record |
| 1007 | * things if requested. Note that interrupts are hard-disabled |
| 1008 | * here so there is no possibility of being interrupted. |
| 1009 | */ |
| 1010 | static void record_and_restart(struct perf_counter *counter, long val, |
| 1011 | struct pt_regs *regs, int nmi) |
| 1012 | { |
| 1013 | u64 period = counter->hw.sample_period; |
| 1014 | s64 prev, delta, left; |
| 1015 | int record = 0; |
| 1016 | u64 addr, mmcra, sdsync; |
| 1017 | |
| 1018 | /* we don't have to worry about interrupts here */ |
| 1019 | prev = atomic64_read(&counter->hw.prev_count); |
| 1020 | delta = (val - prev) & 0xfffffffful; |
| 1021 | atomic64_add(delta, &counter->count); |
| 1022 | |
| 1023 | /* |
| 1024 | * See if the total period for this counter has expired, |
| 1025 | * and update for the next period. |
| 1026 | */ |
| 1027 | val = 0; |
| 1028 | left = atomic64_read(&counter->hw.period_left) - delta; |
| 1029 | if (period) { |
| 1030 | if (left <= 0) { |
| 1031 | left += period; |
| 1032 | if (left <= 0) |
| 1033 | left = period; |
| 1034 | record = 1; |
| 1035 | } |
| 1036 | if (left < 0x80000000L) |
| 1037 | val = 0x80000000L - left; |
| 1038 | } |
| 1039 | |
| 1040 | /* |
| 1041 | * Finally record data if requested. |
| 1042 | */ |
| 1043 | if (record) { |
| 1044 | struct perf_sample_data data = { |
| 1045 | .regs = regs, |
| 1046 | .addr = 0, |
| 1047 | .period = counter->hw.last_period, |
| 1048 | }; |
| 1049 | |
| 1050 | if (counter->attr.sample_type & PERF_SAMPLE_ADDR) { |
| 1051 | /* |
| 1052 | * The user wants a data address recorded. |
| 1053 | * If we're not doing instruction sampling, |
| 1054 | * give them the SDAR (sampled data address). |
| 1055 | * If we are doing instruction sampling, then only |
| 1056 | * give them the SDAR if it corresponds to the |
| 1057 | * instruction pointed to by SIAR; this is indicated |
| 1058 | * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA. |
| 1059 | */ |
| 1060 | mmcra = regs->dsisr; |
| 1061 | sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? |
| 1062 | POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; |
| 1063 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) |
| 1064 | data.addr = mfspr(SPRN_SDAR); |
| 1065 | } |
| 1066 | if (perf_counter_overflow(counter, nmi, &data)) { |
| 1067 | /* |
| 1068 | * Interrupts are coming too fast - throttle them |
| 1069 | * by setting the counter to 0, so it will be |
| 1070 | * at least 2^30 cycles until the next interrupt |
| 1071 | * (assuming each counter counts at most 2 counts |
| 1072 | * per cycle). |
| 1073 | */ |
| 1074 | val = 0; |
| 1075 | left = ~0ULL >> 1; |
| 1076 | } |
| 1077 | } |
| 1078 | |
| 1079 | write_pmc(counter->hw.idx, val); |
| 1080 | atomic64_set(&counter->hw.prev_count, val); |
| 1081 | atomic64_set(&counter->hw.period_left, left); |
| 1082 | perf_counter_update_userpage(counter); |
| 1083 | } |
| 1084 | |
| 1085 | /* |
| 1086 | * Called from generic code to get the misc flags (i.e. processor mode) |
| 1087 | * for an event. |
| 1088 | */ |
| 1089 | unsigned long perf_misc_flags(struct pt_regs *regs) |
| 1090 | { |
| 1091 | unsigned long mmcra; |
| 1092 | |
| 1093 | if (TRAP(regs) != 0xf00) { |
| 1094 | /* not a PMU interrupt */ |
| 1095 | return user_mode(regs) ? PERF_EVENT_MISC_USER : |
| 1096 | PERF_EVENT_MISC_KERNEL; |
| 1097 | } |
| 1098 | |
| 1099 | mmcra = regs->dsisr; |
| 1100 | if (ppmu->flags & PPMU_ALT_SIPR) { |
| 1101 | if (mmcra & POWER6_MMCRA_SIHV) |
| 1102 | return PERF_EVENT_MISC_HYPERVISOR; |
| 1103 | return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER : |
| 1104 | PERF_EVENT_MISC_KERNEL; |
| 1105 | } |
| 1106 | if (mmcra & MMCRA_SIHV) |
| 1107 | return PERF_EVENT_MISC_HYPERVISOR; |
| 1108 | return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER : |
| 1109 | PERF_EVENT_MISC_KERNEL; |
| 1110 | } |
| 1111 | |
| 1112 | /* |
| 1113 | * Called from generic code to get the instruction pointer |
| 1114 | * for an event. |
| 1115 | */ |
| 1116 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
| 1117 | { |
| 1118 | unsigned long mmcra; |
| 1119 | unsigned long ip; |
| 1120 | unsigned long slot; |
| 1121 | |
| 1122 | if (TRAP(regs) != 0xf00) |
| 1123 | return regs->nip; /* not a PMU interrupt */ |
| 1124 | |
| 1125 | ip = mfspr(SPRN_SIAR); |
| 1126 | mmcra = regs->dsisr; |
| 1127 | if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { |
| 1128 | slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
| 1129 | if (slot > 1) |
| 1130 | ip += 4 * (slot - 1); |
| 1131 | } |
| 1132 | return ip; |
| 1133 | } |
| 1134 | |
| 1135 | /* |
| 1136 | * Performance monitor interrupt stuff |
| 1137 | */ |
| 1138 | static void perf_counter_interrupt(struct pt_regs *regs) |
| 1139 | { |
| 1140 | int i; |
| 1141 | struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters); |
| 1142 | struct perf_counter *counter; |
| 1143 | long val; |
| 1144 | int found = 0; |
| 1145 | int nmi; |
| 1146 | |
| 1147 | if (cpuhw->n_limited) |
| 1148 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
| 1149 | mfspr(SPRN_PMC6)); |
| 1150 | |
| 1151 | /* |
| 1152 | * Overload regs->dsisr to store MMCRA so we only need to read it once. |
| 1153 | */ |
| 1154 | regs->dsisr = mfspr(SPRN_MMCRA); |
| 1155 | |
| 1156 | /* |
| 1157 | * If interrupts were soft-disabled when this PMU interrupt |
| 1158 | * occurred, treat it as an NMI. |
| 1159 | */ |
| 1160 | nmi = !regs->softe; |
| 1161 | if (nmi) |
| 1162 | nmi_enter(); |
| 1163 | else |
| 1164 | irq_enter(); |
| 1165 | |
| 1166 | for (i = 0; i < cpuhw->n_counters; ++i) { |
| 1167 | counter = cpuhw->counter[i]; |
| 1168 | if (!counter->hw.idx || is_limited_pmc(counter->hw.idx)) |
| 1169 | continue; |
| 1170 | val = read_pmc(counter->hw.idx); |
| 1171 | if ((int)val < 0) { |
| 1172 | /* counter has overflowed */ |
| 1173 | found = 1; |
| 1174 | record_and_restart(counter, val, regs, nmi); |
| 1175 | } |
| 1176 | } |
| 1177 | |
| 1178 | /* |
| 1179 | * In case we didn't find and reset the counter that caused |
| 1180 | * the interrupt, scan all counters and reset any that are |
| 1181 | * negative, to avoid getting continual interrupts. |
| 1182 | * Any that we processed in the previous loop will not be negative. |
| 1183 | */ |
| 1184 | if (!found) { |
| 1185 | for (i = 0; i < ppmu->n_counter; ++i) { |
| 1186 | if (is_limited_pmc(i + 1)) |
| 1187 | continue; |
| 1188 | val = read_pmc(i + 1); |
| 1189 | if ((int)val < 0) |
| 1190 | write_pmc(i + 1, 0); |
| 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | /* |
| 1195 | * Reset MMCR0 to its normal value. This will set PMXE and |
| 1196 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
| 1197 | * and thus allow interrupts to occur again. |
| 1198 | * XXX might want to use MSR.PM to keep the counters frozen until |
| 1199 | * we get back out of this interrupt. |
| 1200 | */ |
| 1201 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
| 1202 | |
| 1203 | if (nmi) |
| 1204 | nmi_exit(); |
| 1205 | else |
| 1206 | irq_exit(); |
| 1207 | } |
| 1208 | |
| 1209 | void hw_perf_counter_setup(int cpu) |
| 1210 | { |
| 1211 | struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu); |
| 1212 | |
| 1213 | memset(cpuhw, 0, sizeof(*cpuhw)); |
| 1214 | cpuhw->mmcr[0] = MMCR0_FC; |
| 1215 | } |
| 1216 | |
| 1217 | extern struct power_pmu power4_pmu; |
| 1218 | extern struct power_pmu ppc970_pmu; |
| 1219 | extern struct power_pmu power5_pmu; |
| 1220 | extern struct power_pmu power5p_pmu; |
| 1221 | extern struct power_pmu power6_pmu; |
| 1222 | extern struct power_pmu power7_pmu; |
| 1223 | |
| 1224 | static int init_perf_counters(void) |
| 1225 | { |
| 1226 | unsigned long pvr; |
| 1227 | |
| 1228 | /* XXX should get this from cputable */ |
| 1229 | pvr = mfspr(SPRN_PVR); |
| 1230 | switch (PVR_VER(pvr)) { |
| 1231 | case PV_POWER4: |
| 1232 | case PV_POWER4p: |
| 1233 | ppmu = &power4_pmu; |
| 1234 | break; |
| 1235 | case PV_970: |
| 1236 | case PV_970FX: |
| 1237 | case PV_970MP: |
| 1238 | ppmu = &ppc970_pmu; |
| 1239 | break; |
| 1240 | case PV_POWER5: |
| 1241 | ppmu = &power5_pmu; |
| 1242 | break; |
| 1243 | case PV_POWER5p: |
| 1244 | ppmu = &power5p_pmu; |
| 1245 | break; |
| 1246 | case 0x3e: |
| 1247 | ppmu = &power6_pmu; |
| 1248 | break; |
| 1249 | case 0x3f: |
| 1250 | ppmu = &power7_pmu; |
| 1251 | break; |
| 1252 | } |
| 1253 | |
| 1254 | /* |
| 1255 | * Use FCHV to ignore kernel events if MSR.HV is set. |
| 1256 | */ |
| 1257 | if (mfmsr() & MSR_HV) |
| 1258 | freeze_counters_kernel = MMCR0_FCHV; |
| 1259 | |
| 1260 | return 0; |
| 1261 | } |
| 1262 | |
| 1263 | arch_initcall(init_perf_counters); |