| 1 | /* |
| 2 | * Performance counter support for POWER6 processors. |
| 3 | * |
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/perf_counter.h> |
| 13 | #include <asm/reg.h> |
| 14 | |
| 15 | /* |
| 16 | * Bits in event code for POWER6 |
| 17 | */ |
| 18 | #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */ |
| 19 | #define PM_PMC_MSK 0x7 |
| 20 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) |
| 21 | #define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */ |
| 22 | #define PM_UNIT_MSK 0xf |
| 23 | #define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH) |
| 24 | #define PM_LLAV 0x8000 /* Load lookahead match value */ |
| 25 | #define PM_LLA 0x4000 /* Load lookahead match enable */ |
| 26 | #define PM_BYTE_SH 12 /* Byte of event bus to use */ |
| 27 | #define PM_BYTE_MSK 3 |
| 28 | #define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */ |
| 29 | #define PM_SUBUNIT_MSK 7 |
| 30 | #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH) |
| 31 | #define PM_PMCSEL_MSK 0xff /* PMCxSEL value */ |
| 32 | #define PM_BUSEVENT_MSK 0xf3700 |
| 33 | |
| 34 | /* |
| 35 | * Bits in MMCR1 for POWER6 |
| 36 | */ |
| 37 | #define MMCR1_TTM0SEL_SH 60 |
| 38 | #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4) |
| 39 | #define MMCR1_TTMSEL_MSK 0xf |
| 40 | #define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK) |
| 41 | #define MMCR1_NESTSEL_SH 45 |
| 42 | #define MMCR1_NESTSEL_MSK 0x7 |
| 43 | #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) |
| 44 | #define MMCR1_PMC1_LLA ((u64)1 << 44) |
| 45 | #define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39) |
| 46 | #define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35) |
| 47 | #define MMCR1_PMC1SEL_SH 24 |
| 48 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) |
| 49 | #define MMCR1_PMCSEL_MSK 0xff |
| 50 | |
| 51 | /* |
| 52 | * Map of which direct events on which PMCs are marked instruction events. |
| 53 | * Indexed by PMCSEL value >> 1. |
| 54 | * Bottom 4 bits are a map of which PMCs are interesting, |
| 55 | * top 4 bits say what sort of event: |
| 56 | * 0 = direct marked event, |
| 57 | * 1 = byte decode event, |
| 58 | * 4 = add/and event (PMC1 -> bits 0 & 4), |
| 59 | * 5 = add/and event (PMC1 -> bits 1 & 5), |
| 60 | * 6 = add/and event (PMC1 -> bits 2 & 6), |
| 61 | * 7 = add/and event (PMC1 -> bits 3 & 7). |
| 62 | */ |
| 63 | static unsigned char direct_event_is_marked[0x60 >> 1] = { |
| 64 | 0, /* 00 */ |
| 65 | 0, /* 02 */ |
| 66 | 0, /* 04 */ |
| 67 | 0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */ |
| 68 | 0x04, /* 08 PM_MRK_DFU_FIN */ |
| 69 | 0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */ |
| 70 | 0, /* 0c */ |
| 71 | 0, /* 0e */ |
| 72 | 0x02, /* 10 PM_MRK_INST_DISP */ |
| 73 | 0x08, /* 12 PM_MRK_LSU_DERAT_MISS */ |
| 74 | 0, /* 14 */ |
| 75 | 0, /* 16 */ |
| 76 | 0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */ |
| 77 | 0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */ |
| 78 | 0x01, /* 1c PM_MRK_INST_ISSUED */ |
| 79 | 0, /* 1e */ |
| 80 | 0, /* 20 */ |
| 81 | 0, /* 22 */ |
| 82 | 0, /* 24 */ |
| 83 | 0, /* 26 */ |
| 84 | 0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */ |
| 85 | 0, /* 2a */ |
| 86 | 0, /* 2c */ |
| 87 | 0, /* 2e */ |
| 88 | 0x4f, /* 30 */ |
| 89 | 0x7f, /* 32 */ |
| 90 | 0x4f, /* 34 */ |
| 91 | 0x5f, /* 36 */ |
| 92 | 0x6f, /* 38 */ |
| 93 | 0x4f, /* 3a */ |
| 94 | 0, /* 3c */ |
| 95 | 0x08, /* 3e PM_MRK_INST_TIMEO */ |
| 96 | 0x1f, /* 40 */ |
| 97 | 0x1f, /* 42 */ |
| 98 | 0x1f, /* 44 */ |
| 99 | 0x1f, /* 46 */ |
| 100 | 0x1f, /* 48 */ |
| 101 | 0x1f, /* 4a */ |
| 102 | 0x1f, /* 4c */ |
| 103 | 0x1f, /* 4e */ |
| 104 | 0, /* 50 */ |
| 105 | 0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */ |
| 106 | 0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */ |
| 107 | 0x02, /* 56 PM_MRK_LD_MISS_L1 */ |
| 108 | 0, /* 58 */ |
| 109 | 0, /* 5a */ |
| 110 | 0, /* 5c */ |
| 111 | 0, /* 5e */ |
| 112 | }; |
| 113 | |
| 114 | /* |
| 115 | * Masks showing for each unit which bits are marked events. |
| 116 | * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0. |
| 117 | */ |
| 118 | static u32 marked_bus_events[16] = { |
| 119 | 0x01000000, /* direct events set 1: byte 3 bit 0 */ |
| 120 | 0x00010000, /* direct events set 2: byte 2 bit 0 */ |
| 121 | 0, 0, 0, 0, /* IDU, IFU, nest: nothing */ |
| 122 | 0x00000088, /* VMX set 1: byte 0 bits 3, 7 */ |
| 123 | 0x000000c0, /* VMX set 2: byte 0 bits 4-7 */ |
| 124 | 0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */ |
| 125 | 0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */ |
| 126 | 0, /* LSU set 3 */ |
| 127 | 0x00000010, /* VMX set 3: byte 0 bit 4 */ |
| 128 | 0, /* BFP set 1 */ |
| 129 | 0x00000022, /* BFP set 2: byte 0 bits 1, 5 */ |
| 130 | 0, 0 |
| 131 | }; |
| 132 | |
| 133 | /* |
| 134 | * Returns 1 if event counts things relating to marked instructions |
| 135 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. |
| 136 | */ |
| 137 | static int power6_marked_instr_event(u64 event) |
| 138 | { |
| 139 | int pmc, psel, ptype; |
| 140 | int bit, byte, unit; |
| 141 | u32 mask; |
| 142 | |
| 143 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; |
| 144 | psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */ |
| 145 | if (pmc >= 5) |
| 146 | return 0; |
| 147 | |
| 148 | bit = -1; |
| 149 | if (psel < sizeof(direct_event_is_marked)) { |
| 150 | ptype = direct_event_is_marked[psel]; |
| 151 | if (pmc == 0 || !(ptype & (1 << (pmc - 1)))) |
| 152 | return 0; |
| 153 | ptype >>= 4; |
| 154 | if (ptype == 0) |
| 155 | return 1; |
| 156 | if (ptype == 1) |
| 157 | bit = 0; |
| 158 | else |
| 159 | bit = ptype ^ (pmc - 1); |
| 160 | } else if ((psel & 0x48) == 0x40) |
| 161 | bit = psel & 7; |
| 162 | |
| 163 | if (!(event & PM_BUSEVENT_MSK) || bit == -1) |
| 164 | return 0; |
| 165 | |
| 166 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; |
| 167 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; |
| 168 | mask = marked_bus_events[unit]; |
| 169 | return (mask >> (byte * 8 + bit)) & 1; |
| 170 | } |
| 171 | |
| 172 | /* |
| 173 | * Assign PMC numbers and compute MMCR1 value for a set of events |
| 174 | */ |
| 175 | static int p6_compute_mmcr(u64 event[], int n_ev, |
| 176 | unsigned int hwc[], u64 mmcr[]) |
| 177 | { |
| 178 | u64 mmcr1 = 0; |
| 179 | u64 mmcra = 0; |
| 180 | int i; |
| 181 | unsigned int pmc, ev, b, u, s, psel; |
| 182 | unsigned int ttmset = 0; |
| 183 | unsigned int pmc_inuse = 0; |
| 184 | |
| 185 | if (n_ev > 6) |
| 186 | return -1; |
| 187 | for (i = 0; i < n_ev; ++i) { |
| 188 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; |
| 189 | if (pmc) { |
| 190 | if (pmc_inuse & (1 << (pmc - 1))) |
| 191 | return -1; /* collision! */ |
| 192 | pmc_inuse |= 1 << (pmc - 1); |
| 193 | } |
| 194 | } |
| 195 | for (i = 0; i < n_ev; ++i) { |
| 196 | ev = event[i]; |
| 197 | pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK; |
| 198 | if (pmc) { |
| 199 | --pmc; |
| 200 | } else { |
| 201 | /* can go on any PMC; find a free one */ |
| 202 | for (pmc = 0; pmc < 4; ++pmc) |
| 203 | if (!(pmc_inuse & (1 << pmc))) |
| 204 | break; |
| 205 | if (pmc >= 4) |
| 206 | return -1; |
| 207 | pmc_inuse |= 1 << pmc; |
| 208 | } |
| 209 | hwc[i] = pmc; |
| 210 | psel = ev & PM_PMCSEL_MSK; |
| 211 | if (ev & PM_BUSEVENT_MSK) { |
| 212 | /* this event uses the event bus */ |
| 213 | b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK; |
| 214 | u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK; |
| 215 | /* check for conflict on this byte of event bus */ |
| 216 | if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) |
| 217 | return -1; |
| 218 | mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b); |
| 219 | ttmset |= 1 << b; |
| 220 | if (u == 5) { |
| 221 | /* Nest events have a further mux */ |
| 222 | s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; |
| 223 | if ((ttmset & 0x10) && |
| 224 | MMCR1_NESTSEL(mmcr1) != s) |
| 225 | return -1; |
| 226 | ttmset |= 0x10; |
| 227 | mmcr1 |= (u64)s << MMCR1_NESTSEL_SH; |
| 228 | } |
| 229 | if (0x30 <= psel && psel <= 0x3d) { |
| 230 | /* these need the PMCx_ADDR_SEL bits */ |
| 231 | if (b >= 2) |
| 232 | mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc; |
| 233 | } |
| 234 | /* bus select values are different for PMC3/4 */ |
| 235 | if (pmc >= 2 && (psel & 0x90) == 0x80) |
| 236 | psel ^= 0x20; |
| 237 | } |
| 238 | if (ev & PM_LLA) { |
| 239 | mmcr1 |= MMCR1_PMC1_LLA >> pmc; |
| 240 | if (ev & PM_LLAV) |
| 241 | mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc; |
| 242 | } |
| 243 | if (power6_marked_instr_event(event[i])) |
| 244 | mmcra |= MMCRA_SAMPLE_ENABLE; |
| 245 | if (pmc < 4) |
| 246 | mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc); |
| 247 | } |
| 248 | mmcr[0] = 0; |
| 249 | if (pmc_inuse & 1) |
| 250 | mmcr[0] = MMCR0_PMC1CE; |
| 251 | if (pmc_inuse & 0xe) |
| 252 | mmcr[0] |= MMCR0_PMCjCE; |
| 253 | mmcr[1] = mmcr1; |
| 254 | mmcr[2] = mmcra; |
| 255 | return 0; |
| 256 | } |
| 257 | |
| 258 | /* |
| 259 | * Layout of constraint bits: |
| 260 | * |
| 261 | * 0-1 add field: number of uses of PMC1 (max 1) |
| 262 | * 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6 |
| 263 | * 12-15 add field: number of uses of PMC1-4 (max 4) |
| 264 | * 16-19 select field: unit on byte 0 of event bus |
| 265 | * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 |
| 266 | * 32-34 select field: nest (subunit) event selector |
| 267 | */ |
| 268 | static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) |
| 269 | { |
| 270 | int pmc, byte, sh, subunit; |
| 271 | u64 mask = 0, value = 0; |
| 272 | |
| 273 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; |
| 274 | if (pmc) { |
| 275 | if (pmc > 4 && !(event == 0x500009 || event == 0x600005)) |
| 276 | return -1; |
| 277 | sh = (pmc - 1) * 2; |
| 278 | mask |= 2 << sh; |
| 279 | value |= 1 << sh; |
| 280 | } |
| 281 | if (event & PM_BUSEVENT_MSK) { |
| 282 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; |
| 283 | sh = byte * 4 + (16 - PM_UNIT_SH); |
| 284 | mask |= PM_UNIT_MSKS << sh; |
| 285 | value |= (u64)(event & PM_UNIT_MSKS) << sh; |
| 286 | if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { |
| 287 | subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; |
| 288 | mask |= (u64)PM_SUBUNIT_MSK << 32; |
| 289 | value |= (u64)subunit << 32; |
| 290 | } |
| 291 | } |
| 292 | if (pmc <= 4) { |
| 293 | mask |= 0x8000; /* add field for count of PMC1-4 uses */ |
| 294 | value |= 0x1000; |
| 295 | } |
| 296 | *maskp = mask; |
| 297 | *valp = value; |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | static int p6_limited_pmc_event(u64 event) |
| 302 | { |
| 303 | int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; |
| 304 | |
| 305 | return pmc == 5 || pmc == 6; |
| 306 | } |
| 307 | |
| 308 | #define MAX_ALT 4 /* at most 4 alternatives for any event */ |
| 309 | |
| 310 | static const unsigned int event_alternatives[][MAX_ALT] = { |
| 311 | { 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */ |
| 312 | { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */ |
| 313 | { 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */ |
| 314 | { 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */ |
| 315 | { 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */ |
| 316 | { 0x10000e, 0x400010 }, /* PM_PURR */ |
| 317 | { 0x100010, 0x4000f8 }, /* PM_FLUSH */ |
| 318 | { 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */ |
| 319 | { 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */ |
| 320 | { 0x100054, 0x2000f0 }, /* PM_ST_FIN */ |
| 321 | { 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */ |
| 322 | { 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */ |
| 323 | { 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */ |
| 324 | { 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */ |
| 325 | { 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */ |
| 326 | { 0x200012, 0x300012 }, /* PM_INST_DISP */ |
| 327 | { 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */ |
| 328 | { 0x2000f8, 0x300010 }, /* PM_EXT_INT */ |
| 329 | { 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */ |
| 330 | { 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */ |
| 331 | { 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */ |
| 332 | { 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */ |
| 333 | { 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */ |
| 334 | }; |
| 335 | |
| 336 | /* |
| 337 | * This could be made more efficient with a binary search on |
| 338 | * a presorted list, if necessary |
| 339 | */ |
| 340 | static int find_alternatives_list(u64 event) |
| 341 | { |
| 342 | int i, j; |
| 343 | unsigned int alt; |
| 344 | |
| 345 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { |
| 346 | if (event < event_alternatives[i][0]) |
| 347 | return -1; |
| 348 | for (j = 0; j < MAX_ALT; ++j) { |
| 349 | alt = event_alternatives[i][j]; |
| 350 | if (!alt || event < alt) |
| 351 | break; |
| 352 | if (event == alt) |
| 353 | return i; |
| 354 | } |
| 355 | } |
| 356 | return -1; |
| 357 | } |
| 358 | |
| 359 | static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[]) |
| 360 | { |
| 361 | int i, j, nlim; |
| 362 | unsigned int psel, pmc; |
| 363 | unsigned int nalt = 1; |
| 364 | u64 aevent; |
| 365 | |
| 366 | alt[0] = event; |
| 367 | nlim = p6_limited_pmc_event(event); |
| 368 | |
| 369 | /* check the alternatives table */ |
| 370 | i = find_alternatives_list(event); |
| 371 | if (i >= 0) { |
| 372 | /* copy out alternatives from list */ |
| 373 | for (j = 0; j < MAX_ALT; ++j) { |
| 374 | aevent = event_alternatives[i][j]; |
| 375 | if (!aevent) |
| 376 | break; |
| 377 | if (aevent != event) |
| 378 | alt[nalt++] = aevent; |
| 379 | nlim += p6_limited_pmc_event(aevent); |
| 380 | } |
| 381 | |
| 382 | } else { |
| 383 | /* Check for alternative ways of computing sum events */ |
| 384 | /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */ |
| 385 | psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */ |
| 386 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; |
| 387 | if (pmc && (psel == 0x32 || psel == 0x34)) |
| 388 | alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) | |
| 389 | ((5 - pmc) << PM_PMC_SH); |
| 390 | |
| 391 | /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */ |
| 392 | if (pmc && (psel == 0x38 || psel == 0x3a)) |
| 393 | alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) | |
| 394 | ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH); |
| 395 | } |
| 396 | |
| 397 | if (flags & PPMU_ONLY_COUNT_RUN) { |
| 398 | /* |
| 399 | * We're only counting in RUN state, |
| 400 | * so PM_CYC is equivalent to PM_RUN_CYC, |
| 401 | * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR. |
| 402 | * This doesn't include alternatives that don't provide |
| 403 | * any extra flexibility in assigning PMCs (e.g. |
| 404 | * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC). |
| 405 | * Note that even with these additional alternatives |
| 406 | * we never end up with more than 4 alternatives for any event. |
| 407 | */ |
| 408 | j = nalt; |
| 409 | for (i = 0; i < nalt; ++i) { |
| 410 | switch (alt[i]) { |
| 411 | case 0x1e: /* PM_CYC */ |
| 412 | alt[j++] = 0x600005; /* PM_RUN_CYC */ |
| 413 | ++nlim; |
| 414 | break; |
| 415 | case 0x10000a: /* PM_RUN_CYC */ |
| 416 | alt[j++] = 0x1e; /* PM_CYC */ |
| 417 | break; |
| 418 | case 2: /* PM_INST_CMPL */ |
| 419 | alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */ |
| 420 | ++nlim; |
| 421 | break; |
| 422 | case 0x500009: /* PM_RUN_INST_CMPL */ |
| 423 | alt[j++] = 2; /* PM_INST_CMPL */ |
| 424 | break; |
| 425 | case 0x10000e: /* PM_PURR */ |
| 426 | alt[j++] = 0x4000f4; /* PM_RUN_PURR */ |
| 427 | break; |
| 428 | case 0x4000f4: /* PM_RUN_PURR */ |
| 429 | alt[j++] = 0x10000e; /* PM_PURR */ |
| 430 | break; |
| 431 | } |
| 432 | } |
| 433 | nalt = j; |
| 434 | } |
| 435 | |
| 436 | if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) { |
| 437 | /* remove the limited PMC events */ |
| 438 | j = 0; |
| 439 | for (i = 0; i < nalt; ++i) { |
| 440 | if (!p6_limited_pmc_event(alt[i])) { |
| 441 | alt[j] = alt[i]; |
| 442 | ++j; |
| 443 | } |
| 444 | } |
| 445 | nalt = j; |
| 446 | } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) { |
| 447 | /* remove all but the limited PMC events */ |
| 448 | j = 0; |
| 449 | for (i = 0; i < nalt; ++i) { |
| 450 | if (p6_limited_pmc_event(alt[i])) { |
| 451 | alt[j] = alt[i]; |
| 452 | ++j; |
| 453 | } |
| 454 | } |
| 455 | nalt = j; |
| 456 | } |
| 457 | |
| 458 | return nalt; |
| 459 | } |
| 460 | |
| 461 | static void p6_disable_pmc(unsigned int pmc, u64 mmcr[]) |
| 462 | { |
| 463 | /* Set PMCxSEL to 0 to disable PMCx */ |
| 464 | if (pmc <= 3) |
| 465 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); |
| 466 | } |
| 467 | |
| 468 | static int power6_generic_events[] = { |
| 469 | [PERF_COUNT_CPU_CYCLES] = 0x1e, |
| 470 | [PERF_COUNT_INSTRUCTIONS] = 2, |
| 471 | [PERF_COUNT_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */ |
| 472 | [PERF_COUNT_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */ |
| 473 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */ |
| 474 | [PERF_COUNT_BRANCH_MISSES] = 0x400052, /* BR_MPRED */ |
| 475 | }; |
| 476 | |
| 477 | struct power_pmu power6_pmu = { |
| 478 | .n_counter = 6, |
| 479 | .max_alternatives = MAX_ALT, |
| 480 | .add_fields = 0x1555, |
| 481 | .test_adder = 0x3000, |
| 482 | .compute_mmcr = p6_compute_mmcr, |
| 483 | .get_constraint = p6_get_constraint, |
| 484 | .get_alternatives = p6_get_alternatives, |
| 485 | .disable_pmc = p6_disable_pmc, |
| 486 | .n_generic = ARRAY_SIZE(power6_generic_events), |
| 487 | .generic_events = power6_generic_events, |
| 488 | .limited_pmc5_6 = 1, |
| 489 | .limited_pmc_event = p6_limited_pmc_event, |
| 490 | }; |