| 1 | /* |
| 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version |
| 8 | * 2 of the License, or (at your option) any later version. |
| 9 | * |
| 10 | * Modified by Cort Dougan (cort@cs.nmt.edu) |
| 11 | * and Paul Mackerras (paulus@samba.org) |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * This file handles the architecture-dependent parts of hardware exceptions |
| 16 | */ |
| 17 | |
| 18 | #include <linux/errno.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/mm.h> |
| 22 | #include <linux/stddef.h> |
| 23 | #include <linux/unistd.h> |
| 24 | #include <linux/ptrace.h> |
| 25 | #include <linux/user.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/prctl.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/kprobes.h> |
| 32 | #include <linux/kexec.h> |
| 33 | #include <linux/backlight.h> |
| 34 | #include <linux/bug.h> |
| 35 | #include <linux/kdebug.h> |
| 36 | #include <linux/debugfs.h> |
| 37 | #include <linux/ratelimit.h> |
| 38 | |
| 39 | #include <asm/emulated_ops.h> |
| 40 | #include <asm/pgtable.h> |
| 41 | #include <asm/uaccess.h> |
| 42 | #include <asm/system.h> |
| 43 | #include <asm/io.h> |
| 44 | #include <asm/machdep.h> |
| 45 | #include <asm/rtas.h> |
| 46 | #include <asm/pmc.h> |
| 47 | #ifdef CONFIG_PPC32 |
| 48 | #include <asm/reg.h> |
| 49 | #endif |
| 50 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 51 | #include <asm/backlight.h> |
| 52 | #endif |
| 53 | #ifdef CONFIG_PPC64 |
| 54 | #include <asm/firmware.h> |
| 55 | #include <asm/processor.h> |
| 56 | #endif |
| 57 | #include <asm/kexec.h> |
| 58 | #include <asm/ppc-opcode.h> |
| 59 | #include <asm/rio.h> |
| 60 | |
| 61 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
| 62 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
| 63 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; |
| 64 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; |
| 65 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; |
| 66 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; |
| 67 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; |
| 68 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
| 69 | |
| 70 | EXPORT_SYMBOL(__debugger); |
| 71 | EXPORT_SYMBOL(__debugger_ipi); |
| 72 | EXPORT_SYMBOL(__debugger_bpt); |
| 73 | EXPORT_SYMBOL(__debugger_sstep); |
| 74 | EXPORT_SYMBOL(__debugger_iabr_match); |
| 75 | EXPORT_SYMBOL(__debugger_dabr_match); |
| 76 | EXPORT_SYMBOL(__debugger_fault_handler); |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * Trap & Exception support |
| 81 | */ |
| 82 | |
| 83 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 84 | static void pmac_backlight_unblank(void) |
| 85 | { |
| 86 | mutex_lock(&pmac_backlight_mutex); |
| 87 | if (pmac_backlight) { |
| 88 | struct backlight_properties *props; |
| 89 | |
| 90 | props = &pmac_backlight->props; |
| 91 | props->brightness = props->max_brightness; |
| 92 | props->power = FB_BLANK_UNBLANK; |
| 93 | backlight_update_status(pmac_backlight); |
| 94 | } |
| 95 | mutex_unlock(&pmac_backlight_mutex); |
| 96 | } |
| 97 | #else |
| 98 | static inline void pmac_backlight_unblank(void) { } |
| 99 | #endif |
| 100 | |
| 101 | int die(const char *str, struct pt_regs *regs, long err) |
| 102 | { |
| 103 | static struct { |
| 104 | raw_spinlock_t lock; |
| 105 | u32 lock_owner; |
| 106 | int lock_owner_depth; |
| 107 | } die = { |
| 108 | .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock), |
| 109 | .lock_owner = -1, |
| 110 | .lock_owner_depth = 0 |
| 111 | }; |
| 112 | static int die_counter; |
| 113 | unsigned long flags; |
| 114 | |
| 115 | if (debugger(regs)) |
| 116 | return 1; |
| 117 | |
| 118 | oops_enter(); |
| 119 | |
| 120 | if (die.lock_owner != raw_smp_processor_id()) { |
| 121 | console_verbose(); |
| 122 | raw_spin_lock_irqsave(&die.lock, flags); |
| 123 | die.lock_owner = smp_processor_id(); |
| 124 | die.lock_owner_depth = 0; |
| 125 | bust_spinlocks(1); |
| 126 | if (machine_is(powermac)) |
| 127 | pmac_backlight_unblank(); |
| 128 | } else { |
| 129 | local_save_flags(flags); |
| 130 | } |
| 131 | |
| 132 | if (++die.lock_owner_depth < 3) { |
| 133 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); |
| 134 | #ifdef CONFIG_PREEMPT |
| 135 | printk("PREEMPT "); |
| 136 | #endif |
| 137 | #ifdef CONFIG_SMP |
| 138 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
| 139 | #endif |
| 140 | #ifdef CONFIG_DEBUG_PAGEALLOC |
| 141 | printk("DEBUG_PAGEALLOC "); |
| 142 | #endif |
| 143 | #ifdef CONFIG_NUMA |
| 144 | printk("NUMA "); |
| 145 | #endif |
| 146 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
| 147 | |
| 148 | if (notify_die(DIE_OOPS, str, regs, err, 255, |
| 149 | SIGSEGV) == NOTIFY_STOP) |
| 150 | return 1; |
| 151 | |
| 152 | print_modules(); |
| 153 | show_regs(regs); |
| 154 | } else { |
| 155 | printk("Recursive die() failure, output suppressed\n"); |
| 156 | } |
| 157 | |
| 158 | bust_spinlocks(0); |
| 159 | die.lock_owner = -1; |
| 160 | add_taint(TAINT_DIE); |
| 161 | raw_spin_unlock_irqrestore(&die.lock, flags); |
| 162 | |
| 163 | if (kexec_should_crash(current) || |
| 164 | kexec_sr_activated(smp_processor_id())) |
| 165 | crash_kexec(regs); |
| 166 | crash_kexec_secondary(regs); |
| 167 | |
| 168 | if (in_interrupt()) |
| 169 | panic("Fatal exception in interrupt"); |
| 170 | |
| 171 | if (panic_on_oops) |
| 172 | panic("Fatal exception"); |
| 173 | |
| 174 | oops_exit(); |
| 175 | do_exit(err); |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | void user_single_step_siginfo(struct task_struct *tsk, |
| 181 | struct pt_regs *regs, siginfo_t *info) |
| 182 | { |
| 183 | memset(info, 0, sizeof(*info)); |
| 184 | info->si_signo = SIGTRAP; |
| 185 | info->si_code = TRAP_TRACE; |
| 186 | info->si_addr = (void __user *)regs->nip; |
| 187 | } |
| 188 | |
| 189 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
| 190 | { |
| 191 | siginfo_t info; |
| 192 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
| 193 | "at %08lx nip %08lx lr %08lx code %x\n"; |
| 194 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
| 195 | "at %016lx nip %016lx lr %016lx code %x\n"; |
| 196 | |
| 197 | if (!user_mode(regs)) { |
| 198 | if (die("Exception in kernel mode", regs, signr)) |
| 199 | return; |
| 200 | } else if (show_unhandled_signals && |
| 201 | unhandled_signal(current, signr)) { |
| 202 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
| 203 | current->comm, current->pid, signr, |
| 204 | addr, regs->nip, regs->link, code); |
| 205 | } |
| 206 | |
| 207 | memset(&info, 0, sizeof(info)); |
| 208 | info.si_signo = signr; |
| 209 | info.si_code = code; |
| 210 | info.si_addr = (void __user *) addr; |
| 211 | force_sig_info(signr, &info, current); |
| 212 | } |
| 213 | |
| 214 | #ifdef CONFIG_PPC64 |
| 215 | void system_reset_exception(struct pt_regs *regs) |
| 216 | { |
| 217 | /* See if any machine dependent calls */ |
| 218 | if (ppc_md.system_reset_exception) { |
| 219 | if (ppc_md.system_reset_exception(regs)) |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | #ifdef CONFIG_KEXEC |
| 224 | cpumask_set_cpu(smp_processor_id(), &cpus_in_sr); |
| 225 | #endif |
| 226 | |
| 227 | die("System Reset", regs, SIGABRT); |
| 228 | |
| 229 | /* |
| 230 | * Some CPUs when released from the debugger will execute this path. |
| 231 | * These CPUs entered the debugger via a soft-reset. If the CPU was |
| 232 | * hung before entering the debugger it will return to the hung |
| 233 | * state when exiting this function. This causes a problem in |
| 234 | * kdump since the hung CPU(s) will not respond to the IPI sent |
| 235 | * from kdump. To prevent the problem we call crash_kexec_secondary() |
| 236 | * here. If a kdump had not been initiated or we exit the debugger |
| 237 | * with the "exit and recover" command (x) crash_kexec_secondary() |
| 238 | * will return after 5ms and the CPU returns to its previous state. |
| 239 | */ |
| 240 | crash_kexec_secondary(regs); |
| 241 | |
| 242 | /* Must die if the interrupt is not recoverable */ |
| 243 | if (!(regs->msr & MSR_RI)) |
| 244 | panic("Unrecoverable System Reset"); |
| 245 | |
| 246 | /* What should we do here? We could issue a shutdown or hard reset. */ |
| 247 | } |
| 248 | #endif |
| 249 | |
| 250 | /* |
| 251 | * I/O accesses can cause machine checks on powermacs. |
| 252 | * Check if the NIP corresponds to the address of a sync |
| 253 | * instruction for which there is an entry in the exception |
| 254 | * table. |
| 255 | * Note that the 601 only takes a machine check on TEA |
| 256 | * (transfer error ack) signal assertion, and does not |
| 257 | * set any of the top 16 bits of SRR1. |
| 258 | * -- paulus. |
| 259 | */ |
| 260 | static inline int check_io_access(struct pt_regs *regs) |
| 261 | { |
| 262 | #ifdef CONFIG_PPC32 |
| 263 | unsigned long msr = regs->msr; |
| 264 | const struct exception_table_entry *entry; |
| 265 | unsigned int *nip = (unsigned int *)regs->nip; |
| 266 | |
| 267 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) |
| 268 | && (entry = search_exception_tables(regs->nip)) != NULL) { |
| 269 | /* |
| 270 | * Check that it's a sync instruction, or somewhere |
| 271 | * in the twi; isync; nop sequence that inb/inw/inl uses. |
| 272 | * As the address is in the exception table |
| 273 | * we should be able to read the instr there. |
| 274 | * For the debug message, we look at the preceding |
| 275 | * load or store. |
| 276 | */ |
| 277 | if (*nip == 0x60000000) /* nop */ |
| 278 | nip -= 2; |
| 279 | else if (*nip == 0x4c00012c) /* isync */ |
| 280 | --nip; |
| 281 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { |
| 282 | /* sync or twi */ |
| 283 | unsigned int rb; |
| 284 | |
| 285 | --nip; |
| 286 | rb = (*nip >> 11) & 0x1f; |
| 287 | printk(KERN_DEBUG "%s bad port %lx at %p\n", |
| 288 | (*nip & 0x100)? "OUT to": "IN from", |
| 289 | regs->gpr[rb] - _IO_BASE, nip); |
| 290 | regs->msr |= MSR_RI; |
| 291 | regs->nip = entry->fixup; |
| 292 | return 1; |
| 293 | } |
| 294 | } |
| 295 | #endif /* CONFIG_PPC32 */ |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
| 300 | /* On 4xx, the reason for the machine check or program exception |
| 301 | is in the ESR. */ |
| 302 | #define get_reason(regs) ((regs)->dsisr) |
| 303 | #ifndef CONFIG_FSL_BOOKE |
| 304 | #define get_mc_reason(regs) ((regs)->dsisr) |
| 305 | #else |
| 306 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
| 307 | #endif |
| 308 | #define REASON_FP ESR_FP |
| 309 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) |
| 310 | #define REASON_PRIVILEGED ESR_PPR |
| 311 | #define REASON_TRAP ESR_PTR |
| 312 | |
| 313 | /* single-step stuff */ |
| 314 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) |
| 315 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) |
| 316 | |
| 317 | #else |
| 318 | /* On non-4xx, the reason for the machine check or program |
| 319 | exception is in the MSR. */ |
| 320 | #define get_reason(regs) ((regs)->msr) |
| 321 | #define get_mc_reason(regs) ((regs)->msr) |
| 322 | #define REASON_FP 0x100000 |
| 323 | #define REASON_ILLEGAL 0x80000 |
| 324 | #define REASON_PRIVILEGED 0x40000 |
| 325 | #define REASON_TRAP 0x20000 |
| 326 | |
| 327 | #define single_stepping(regs) ((regs)->msr & MSR_SE) |
| 328 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) |
| 329 | #endif |
| 330 | |
| 331 | #if defined(CONFIG_4xx) |
| 332 | int machine_check_4xx(struct pt_regs *regs) |
| 333 | { |
| 334 | unsigned long reason = get_mc_reason(regs); |
| 335 | |
| 336 | if (reason & ESR_IMCP) { |
| 337 | printk("Instruction"); |
| 338 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 339 | } else |
| 340 | printk("Data"); |
| 341 | printk(" machine check in kernel mode.\n"); |
| 342 | |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | int machine_check_440A(struct pt_regs *regs) |
| 347 | { |
| 348 | unsigned long reason = get_mc_reason(regs); |
| 349 | |
| 350 | printk("Machine check in kernel mode.\n"); |
| 351 | if (reason & ESR_IMCP){ |
| 352 | printk("Instruction Synchronous Machine Check exception\n"); |
| 353 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 354 | } |
| 355 | else { |
| 356 | u32 mcsr = mfspr(SPRN_MCSR); |
| 357 | if (mcsr & MCSR_IB) |
| 358 | printk("Instruction Read PLB Error\n"); |
| 359 | if (mcsr & MCSR_DRB) |
| 360 | printk("Data Read PLB Error\n"); |
| 361 | if (mcsr & MCSR_DWB) |
| 362 | printk("Data Write PLB Error\n"); |
| 363 | if (mcsr & MCSR_TLBP) |
| 364 | printk("TLB Parity Error\n"); |
| 365 | if (mcsr & MCSR_ICP){ |
| 366 | flush_instruction_cache(); |
| 367 | printk("I-Cache Parity Error\n"); |
| 368 | } |
| 369 | if (mcsr & MCSR_DCSP) |
| 370 | printk("D-Cache Search Parity Error\n"); |
| 371 | if (mcsr & MCSR_DCFP) |
| 372 | printk("D-Cache Flush Parity Error\n"); |
| 373 | if (mcsr & MCSR_IMPE) |
| 374 | printk("Machine Check exception is imprecise\n"); |
| 375 | |
| 376 | /* Clear MCSR */ |
| 377 | mtspr(SPRN_MCSR, mcsr); |
| 378 | } |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | int machine_check_47x(struct pt_regs *regs) |
| 383 | { |
| 384 | unsigned long reason = get_mc_reason(regs); |
| 385 | u32 mcsr; |
| 386 | |
| 387 | printk(KERN_ERR "Machine check in kernel mode.\n"); |
| 388 | if (reason & ESR_IMCP) { |
| 389 | printk(KERN_ERR |
| 390 | "Instruction Synchronous Machine Check exception\n"); |
| 391 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); |
| 392 | return 0; |
| 393 | } |
| 394 | mcsr = mfspr(SPRN_MCSR); |
| 395 | if (mcsr & MCSR_IB) |
| 396 | printk(KERN_ERR "Instruction Read PLB Error\n"); |
| 397 | if (mcsr & MCSR_DRB) |
| 398 | printk(KERN_ERR "Data Read PLB Error\n"); |
| 399 | if (mcsr & MCSR_DWB) |
| 400 | printk(KERN_ERR "Data Write PLB Error\n"); |
| 401 | if (mcsr & MCSR_TLBP) |
| 402 | printk(KERN_ERR "TLB Parity Error\n"); |
| 403 | if (mcsr & MCSR_ICP) { |
| 404 | flush_instruction_cache(); |
| 405 | printk(KERN_ERR "I-Cache Parity Error\n"); |
| 406 | } |
| 407 | if (mcsr & MCSR_DCSP) |
| 408 | printk(KERN_ERR "D-Cache Search Parity Error\n"); |
| 409 | if (mcsr & PPC47x_MCSR_GPR) |
| 410 | printk(KERN_ERR "GPR Parity Error\n"); |
| 411 | if (mcsr & PPC47x_MCSR_FPR) |
| 412 | printk(KERN_ERR "FPR Parity Error\n"); |
| 413 | if (mcsr & PPC47x_MCSR_IPR) |
| 414 | printk(KERN_ERR "Machine Check exception is imprecise\n"); |
| 415 | |
| 416 | /* Clear MCSR */ |
| 417 | mtspr(SPRN_MCSR, mcsr); |
| 418 | |
| 419 | return 0; |
| 420 | } |
| 421 | #elif defined(CONFIG_E500) |
| 422 | int machine_check_e500mc(struct pt_regs *regs) |
| 423 | { |
| 424 | unsigned long mcsr = mfspr(SPRN_MCSR); |
| 425 | unsigned long reason = mcsr; |
| 426 | int recoverable = 1; |
| 427 | |
| 428 | if (reason & MCSR_LD) { |
| 429 | recoverable = fsl_rio_mcheck_exception(regs); |
| 430 | if (recoverable == 1) |
| 431 | goto silent_out; |
| 432 | } |
| 433 | |
| 434 | printk("Machine check in kernel mode.\n"); |
| 435 | printk("Caused by (from MCSR=%lx): ", reason); |
| 436 | |
| 437 | if (reason & MCSR_MCP) |
| 438 | printk("Machine Check Signal\n"); |
| 439 | |
| 440 | if (reason & MCSR_ICPERR) { |
| 441 | printk("Instruction Cache Parity Error\n"); |
| 442 | |
| 443 | /* |
| 444 | * This is recoverable by invalidating the i-cache. |
| 445 | */ |
| 446 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); |
| 447 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) |
| 448 | ; |
| 449 | |
| 450 | /* |
| 451 | * This will generally be accompanied by an instruction |
| 452 | * fetch error report -- only treat MCSR_IF as fatal |
| 453 | * if it wasn't due to an L1 parity error. |
| 454 | */ |
| 455 | reason &= ~MCSR_IF; |
| 456 | } |
| 457 | |
| 458 | if (reason & MCSR_DCPERR_MC) { |
| 459 | printk("Data Cache Parity Error\n"); |
| 460 | |
| 461 | /* |
| 462 | * In write shadow mode we auto-recover from the error, but it |
| 463 | * may still get logged and cause a machine check. We should |
| 464 | * only treat the non-write shadow case as non-recoverable. |
| 465 | */ |
| 466 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) |
| 467 | recoverable = 0; |
| 468 | } |
| 469 | |
| 470 | if (reason & MCSR_L2MMU_MHIT) { |
| 471 | printk("Hit on multiple TLB entries\n"); |
| 472 | recoverable = 0; |
| 473 | } |
| 474 | |
| 475 | if (reason & MCSR_NMI) |
| 476 | printk("Non-maskable interrupt\n"); |
| 477 | |
| 478 | if (reason & MCSR_IF) { |
| 479 | printk("Instruction Fetch Error Report\n"); |
| 480 | recoverable = 0; |
| 481 | } |
| 482 | |
| 483 | if (reason & MCSR_LD) { |
| 484 | printk("Load Error Report\n"); |
| 485 | recoverable = 0; |
| 486 | } |
| 487 | |
| 488 | if (reason & MCSR_ST) { |
| 489 | printk("Store Error Report\n"); |
| 490 | recoverable = 0; |
| 491 | } |
| 492 | |
| 493 | if (reason & MCSR_LDG) { |
| 494 | printk("Guarded Load Error Report\n"); |
| 495 | recoverable = 0; |
| 496 | } |
| 497 | |
| 498 | if (reason & MCSR_TLBSYNC) |
| 499 | printk("Simultaneous tlbsync operations\n"); |
| 500 | |
| 501 | if (reason & MCSR_BSL2_ERR) { |
| 502 | printk("Level 2 Cache Error\n"); |
| 503 | recoverable = 0; |
| 504 | } |
| 505 | |
| 506 | if (reason & MCSR_MAV) { |
| 507 | u64 addr; |
| 508 | |
| 509 | addr = mfspr(SPRN_MCAR); |
| 510 | addr |= (u64)mfspr(SPRN_MCARU) << 32; |
| 511 | |
| 512 | printk("Machine Check %s Address: %#llx\n", |
| 513 | reason & MCSR_MEA ? "Effective" : "Physical", addr); |
| 514 | } |
| 515 | |
| 516 | silent_out: |
| 517 | mtspr(SPRN_MCSR, mcsr); |
| 518 | return mfspr(SPRN_MCSR) == 0 && recoverable; |
| 519 | } |
| 520 | |
| 521 | int machine_check_e500(struct pt_regs *regs) |
| 522 | { |
| 523 | unsigned long reason = get_mc_reason(regs); |
| 524 | |
| 525 | if (reason & MCSR_BUS_RBERR) { |
| 526 | if (fsl_rio_mcheck_exception(regs)) |
| 527 | return 1; |
| 528 | } |
| 529 | |
| 530 | printk("Machine check in kernel mode.\n"); |
| 531 | printk("Caused by (from MCSR=%lx): ", reason); |
| 532 | |
| 533 | if (reason & MCSR_MCP) |
| 534 | printk("Machine Check Signal\n"); |
| 535 | if (reason & MCSR_ICPERR) |
| 536 | printk("Instruction Cache Parity Error\n"); |
| 537 | if (reason & MCSR_DCP_PERR) |
| 538 | printk("Data Cache Push Parity Error\n"); |
| 539 | if (reason & MCSR_DCPERR) |
| 540 | printk("Data Cache Parity Error\n"); |
| 541 | if (reason & MCSR_BUS_IAERR) |
| 542 | printk("Bus - Instruction Address Error\n"); |
| 543 | if (reason & MCSR_BUS_RAERR) |
| 544 | printk("Bus - Read Address Error\n"); |
| 545 | if (reason & MCSR_BUS_WAERR) |
| 546 | printk("Bus - Write Address Error\n"); |
| 547 | if (reason & MCSR_BUS_IBERR) |
| 548 | printk("Bus - Instruction Data Error\n"); |
| 549 | if (reason & MCSR_BUS_RBERR) |
| 550 | printk("Bus - Read Data Bus Error\n"); |
| 551 | if (reason & MCSR_BUS_WBERR) |
| 552 | printk("Bus - Read Data Bus Error\n"); |
| 553 | if (reason & MCSR_BUS_IPERR) |
| 554 | printk("Bus - Instruction Parity Error\n"); |
| 555 | if (reason & MCSR_BUS_RPERR) |
| 556 | printk("Bus - Read Parity Error\n"); |
| 557 | |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | int machine_check_generic(struct pt_regs *regs) |
| 562 | { |
| 563 | return 0; |
| 564 | } |
| 565 | #elif defined(CONFIG_E200) |
| 566 | int machine_check_e200(struct pt_regs *regs) |
| 567 | { |
| 568 | unsigned long reason = get_mc_reason(regs); |
| 569 | |
| 570 | printk("Machine check in kernel mode.\n"); |
| 571 | printk("Caused by (from MCSR=%lx): ", reason); |
| 572 | |
| 573 | if (reason & MCSR_MCP) |
| 574 | printk("Machine Check Signal\n"); |
| 575 | if (reason & MCSR_CP_PERR) |
| 576 | printk("Cache Push Parity Error\n"); |
| 577 | if (reason & MCSR_CPERR) |
| 578 | printk("Cache Parity Error\n"); |
| 579 | if (reason & MCSR_EXCP_ERR) |
| 580 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); |
| 581 | if (reason & MCSR_BUS_IRERR) |
| 582 | printk("Bus - Read Bus Error on instruction fetch\n"); |
| 583 | if (reason & MCSR_BUS_DRERR) |
| 584 | printk("Bus - Read Bus Error on data load\n"); |
| 585 | if (reason & MCSR_BUS_WRERR) |
| 586 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); |
| 587 | |
| 588 | return 0; |
| 589 | } |
| 590 | #else |
| 591 | int machine_check_generic(struct pt_regs *regs) |
| 592 | { |
| 593 | unsigned long reason = get_mc_reason(regs); |
| 594 | |
| 595 | printk("Machine check in kernel mode.\n"); |
| 596 | printk("Caused by (from SRR1=%lx): ", reason); |
| 597 | switch (reason & 0x601F0000) { |
| 598 | case 0x80000: |
| 599 | printk("Machine check signal\n"); |
| 600 | break; |
| 601 | case 0: /* for 601 */ |
| 602 | case 0x40000: |
| 603 | case 0x140000: /* 7450 MSS error and TEA */ |
| 604 | printk("Transfer error ack signal\n"); |
| 605 | break; |
| 606 | case 0x20000: |
| 607 | printk("Data parity error signal\n"); |
| 608 | break; |
| 609 | case 0x10000: |
| 610 | printk("Address parity error signal\n"); |
| 611 | break; |
| 612 | case 0x20000000: |
| 613 | printk("L1 Data Cache error\n"); |
| 614 | break; |
| 615 | case 0x40000000: |
| 616 | printk("L1 Instruction Cache error\n"); |
| 617 | break; |
| 618 | case 0x00100000: |
| 619 | printk("L2 data cache parity error\n"); |
| 620 | break; |
| 621 | default: |
| 622 | printk("Unknown values in msr\n"); |
| 623 | } |
| 624 | return 0; |
| 625 | } |
| 626 | #endif /* everything else */ |
| 627 | |
| 628 | void machine_check_exception(struct pt_regs *regs) |
| 629 | { |
| 630 | int recover = 0; |
| 631 | |
| 632 | __get_cpu_var(irq_stat).mce_exceptions++; |
| 633 | |
| 634 | /* See if any machine dependent calls. In theory, we would want |
| 635 | * to call the CPU first, and call the ppc_md. one if the CPU |
| 636 | * one returns a positive number. However there is existing code |
| 637 | * that assumes the board gets a first chance, so let's keep it |
| 638 | * that way for now and fix things later. --BenH. |
| 639 | */ |
| 640 | if (ppc_md.machine_check_exception) |
| 641 | recover = ppc_md.machine_check_exception(regs); |
| 642 | else if (cur_cpu_spec->machine_check) |
| 643 | recover = cur_cpu_spec->machine_check(regs); |
| 644 | |
| 645 | if (recover > 0) |
| 646 | return; |
| 647 | |
| 648 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
| 649 | /* the qspan pci read routines can cause machine checks -- Cort |
| 650 | * |
| 651 | * yuck !!! that totally needs to go away ! There are better ways |
| 652 | * to deal with that than having a wart in the mcheck handler. |
| 653 | * -- BenH |
| 654 | */ |
| 655 | bad_page_fault(regs, regs->dar, SIGBUS); |
| 656 | return; |
| 657 | #endif |
| 658 | |
| 659 | if (debugger_fault_handler(regs)) |
| 660 | return; |
| 661 | |
| 662 | if (check_io_access(regs)) |
| 663 | return; |
| 664 | |
| 665 | die("Machine check", regs, SIGBUS); |
| 666 | |
| 667 | /* Must die if the interrupt is not recoverable */ |
| 668 | if (!(regs->msr & MSR_RI)) |
| 669 | panic("Unrecoverable Machine check"); |
| 670 | } |
| 671 | |
| 672 | void SMIException(struct pt_regs *regs) |
| 673 | { |
| 674 | die("System Management Interrupt", regs, SIGABRT); |
| 675 | } |
| 676 | |
| 677 | void unknown_exception(struct pt_regs *regs) |
| 678 | { |
| 679 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
| 680 | regs->nip, regs->msr, regs->trap); |
| 681 | |
| 682 | _exception(SIGTRAP, regs, 0, 0); |
| 683 | } |
| 684 | |
| 685 | void instruction_breakpoint_exception(struct pt_regs *regs) |
| 686 | { |
| 687 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
| 688 | 5, SIGTRAP) == NOTIFY_STOP) |
| 689 | return; |
| 690 | if (debugger_iabr_match(regs)) |
| 691 | return; |
| 692 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
| 693 | } |
| 694 | |
| 695 | void RunModeException(struct pt_regs *regs) |
| 696 | { |
| 697 | _exception(SIGTRAP, regs, 0, 0); |
| 698 | } |
| 699 | |
| 700 | void __kprobes single_step_exception(struct pt_regs *regs) |
| 701 | { |
| 702 | clear_single_step(regs); |
| 703 | |
| 704 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
| 705 | 5, SIGTRAP) == NOTIFY_STOP) |
| 706 | return; |
| 707 | if (debugger_sstep(regs)) |
| 708 | return; |
| 709 | |
| 710 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 711 | } |
| 712 | |
| 713 | /* |
| 714 | * After we have successfully emulated an instruction, we have to |
| 715 | * check if the instruction was being single-stepped, and if so, |
| 716 | * pretend we got a single-step exception. This was pointed out |
| 717 | * by Kumar Gala. -- paulus |
| 718 | */ |
| 719 | static void emulate_single_step(struct pt_regs *regs) |
| 720 | { |
| 721 | if (single_stepping(regs)) |
| 722 | single_step_exception(regs); |
| 723 | } |
| 724 | |
| 725 | static inline int __parse_fpscr(unsigned long fpscr) |
| 726 | { |
| 727 | int ret = 0; |
| 728 | |
| 729 | /* Invalid operation */ |
| 730 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) |
| 731 | ret = FPE_FLTINV; |
| 732 | |
| 733 | /* Overflow */ |
| 734 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) |
| 735 | ret = FPE_FLTOVF; |
| 736 | |
| 737 | /* Underflow */ |
| 738 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) |
| 739 | ret = FPE_FLTUND; |
| 740 | |
| 741 | /* Divide by zero */ |
| 742 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) |
| 743 | ret = FPE_FLTDIV; |
| 744 | |
| 745 | /* Inexact result */ |
| 746 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) |
| 747 | ret = FPE_FLTRES; |
| 748 | |
| 749 | return ret; |
| 750 | } |
| 751 | |
| 752 | static void parse_fpe(struct pt_regs *regs) |
| 753 | { |
| 754 | int code = 0; |
| 755 | |
| 756 | flush_fp_to_thread(current); |
| 757 | |
| 758 | code = __parse_fpscr(current->thread.fpscr.val); |
| 759 | |
| 760 | _exception(SIGFPE, regs, code, regs->nip); |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * Illegal instruction emulation support. Originally written to |
| 765 | * provide the PVR to user applications using the mfspr rd, PVR. |
| 766 | * Return non-zero if we can't emulate, or -EFAULT if the associated |
| 767 | * memory access caused an access fault. Return zero on success. |
| 768 | * |
| 769 | * There are a couple of ways to do this, either "decode" the instruction |
| 770 | * or directly match lots of bits. In this case, matching lots of |
| 771 | * bits is faster and easier. |
| 772 | * |
| 773 | */ |
| 774 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
| 775 | { |
| 776 | u8 rT = (instword >> 21) & 0x1f; |
| 777 | u8 rA = (instword >> 16) & 0x1f; |
| 778 | u8 NB_RB = (instword >> 11) & 0x1f; |
| 779 | u32 num_bytes; |
| 780 | unsigned long EA; |
| 781 | int pos = 0; |
| 782 | |
| 783 | /* Early out if we are an invalid form of lswx */ |
| 784 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
| 785 | if ((rT == rA) || (rT == NB_RB)) |
| 786 | return -EINVAL; |
| 787 | |
| 788 | EA = (rA == 0) ? 0 : regs->gpr[rA]; |
| 789 | |
| 790 | switch (instword & PPC_INST_STRING_MASK) { |
| 791 | case PPC_INST_LSWX: |
| 792 | case PPC_INST_STSWX: |
| 793 | EA += NB_RB; |
| 794 | num_bytes = regs->xer & 0x7f; |
| 795 | break; |
| 796 | case PPC_INST_LSWI: |
| 797 | case PPC_INST_STSWI: |
| 798 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
| 799 | break; |
| 800 | default: |
| 801 | return -EINVAL; |
| 802 | } |
| 803 | |
| 804 | while (num_bytes != 0) |
| 805 | { |
| 806 | u8 val; |
| 807 | u32 shift = 8 * (3 - (pos & 0x3)); |
| 808 | |
| 809 | switch ((instword & PPC_INST_STRING_MASK)) { |
| 810 | case PPC_INST_LSWX: |
| 811 | case PPC_INST_LSWI: |
| 812 | if (get_user(val, (u8 __user *)EA)) |
| 813 | return -EFAULT; |
| 814 | /* first time updating this reg, |
| 815 | * zero it out */ |
| 816 | if (pos == 0) |
| 817 | regs->gpr[rT] = 0; |
| 818 | regs->gpr[rT] |= val << shift; |
| 819 | break; |
| 820 | case PPC_INST_STSWI: |
| 821 | case PPC_INST_STSWX: |
| 822 | val = regs->gpr[rT] >> shift; |
| 823 | if (put_user(val, (u8 __user *)EA)) |
| 824 | return -EFAULT; |
| 825 | break; |
| 826 | } |
| 827 | /* move EA to next address */ |
| 828 | EA += 1; |
| 829 | num_bytes--; |
| 830 | |
| 831 | /* manage our position within the register */ |
| 832 | if (++pos == 4) { |
| 833 | pos = 0; |
| 834 | if (++rT == 32) |
| 835 | rT = 0; |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
| 843 | { |
| 844 | u32 ra,rs; |
| 845 | unsigned long tmp; |
| 846 | |
| 847 | ra = (instword >> 16) & 0x1f; |
| 848 | rs = (instword >> 21) & 0x1f; |
| 849 | |
| 850 | tmp = regs->gpr[rs]; |
| 851 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); |
| 852 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); |
| 853 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; |
| 854 | regs->gpr[ra] = tmp; |
| 855 | |
| 856 | return 0; |
| 857 | } |
| 858 | |
| 859 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
| 860 | { |
| 861 | u8 rT = (instword >> 21) & 0x1f; |
| 862 | u8 rA = (instword >> 16) & 0x1f; |
| 863 | u8 rB = (instword >> 11) & 0x1f; |
| 864 | u8 BC = (instword >> 6) & 0x1f; |
| 865 | u8 bit; |
| 866 | unsigned long tmp; |
| 867 | |
| 868 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; |
| 869 | bit = (regs->ccr >> (31 - BC)) & 0x1; |
| 870 | |
| 871 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; |
| 872 | |
| 873 | return 0; |
| 874 | } |
| 875 | |
| 876 | static int emulate_instruction(struct pt_regs *regs) |
| 877 | { |
| 878 | u32 instword; |
| 879 | u32 rd; |
| 880 | |
| 881 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
| 882 | return -EINVAL; |
| 883 | CHECK_FULL_REGS(regs); |
| 884 | |
| 885 | if (get_user(instword, (u32 __user *)(regs->nip))) |
| 886 | return -EFAULT; |
| 887 | |
| 888 | /* Emulate the mfspr rD, PVR. */ |
| 889 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
| 890 | PPC_WARN_EMULATED(mfpvr, regs); |
| 891 | rd = (instword >> 21) & 0x1f; |
| 892 | regs->gpr[rd] = mfspr(SPRN_PVR); |
| 893 | return 0; |
| 894 | } |
| 895 | |
| 896 | /* Emulating the dcba insn is just a no-op. */ |
| 897 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
| 898 | PPC_WARN_EMULATED(dcba, regs); |
| 899 | return 0; |
| 900 | } |
| 901 | |
| 902 | /* Emulate the mcrxr insn. */ |
| 903 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
| 904 | int shift = (instword >> 21) & 0x1c; |
| 905 | unsigned long msk = 0xf0000000UL >> shift; |
| 906 | |
| 907 | PPC_WARN_EMULATED(mcrxr, regs); |
| 908 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
| 909 | regs->xer &= ~0xf0000000UL; |
| 910 | return 0; |
| 911 | } |
| 912 | |
| 913 | /* Emulate load/store string insn. */ |
| 914 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
| 915 | PPC_WARN_EMULATED(string, regs); |
| 916 | return emulate_string_inst(regs, instword); |
| 917 | } |
| 918 | |
| 919 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
| 920 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
| 921 | PPC_WARN_EMULATED(popcntb, regs); |
| 922 | return emulate_popcntb_inst(regs, instword); |
| 923 | } |
| 924 | |
| 925 | /* Emulate isel (Integer Select) instruction */ |
| 926 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
| 927 | PPC_WARN_EMULATED(isel, regs); |
| 928 | return emulate_isel(regs, instword); |
| 929 | } |
| 930 | |
| 931 | #ifdef CONFIG_PPC64 |
| 932 | /* Emulate the mfspr rD, DSCR. */ |
| 933 | if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) && |
| 934 | cpu_has_feature(CPU_FTR_DSCR)) { |
| 935 | PPC_WARN_EMULATED(mfdscr, regs); |
| 936 | rd = (instword >> 21) & 0x1f; |
| 937 | regs->gpr[rd] = mfspr(SPRN_DSCR); |
| 938 | return 0; |
| 939 | } |
| 940 | /* Emulate the mtspr DSCR, rD. */ |
| 941 | if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) && |
| 942 | cpu_has_feature(CPU_FTR_DSCR)) { |
| 943 | PPC_WARN_EMULATED(mtdscr, regs); |
| 944 | rd = (instword >> 21) & 0x1f; |
| 945 | mtspr(SPRN_DSCR, regs->gpr[rd]); |
| 946 | current->thread.dscr_inherit = 1; |
| 947 | return 0; |
| 948 | } |
| 949 | #endif |
| 950 | |
| 951 | return -EINVAL; |
| 952 | } |
| 953 | |
| 954 | int is_valid_bugaddr(unsigned long addr) |
| 955 | { |
| 956 | return is_kernel_addr(addr); |
| 957 | } |
| 958 | |
| 959 | void __kprobes program_check_exception(struct pt_regs *regs) |
| 960 | { |
| 961 | unsigned int reason = get_reason(regs); |
| 962 | extern int do_mathemu(struct pt_regs *regs); |
| 963 | |
| 964 | /* We can now get here via a FP Unavailable exception if the core |
| 965 | * has no FPU, in that case the reason flags will be 0 */ |
| 966 | |
| 967 | if (reason & REASON_FP) { |
| 968 | /* IEEE FP exception */ |
| 969 | parse_fpe(regs); |
| 970 | return; |
| 971 | } |
| 972 | if (reason & REASON_TRAP) { |
| 973 | /* Debugger is first in line to stop recursive faults in |
| 974 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ |
| 975 | if (debugger_bpt(regs)) |
| 976 | return; |
| 977 | |
| 978 | /* trap exception */ |
| 979 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
| 980 | == NOTIFY_STOP) |
| 981 | return; |
| 982 | |
| 983 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
| 984 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
| 985 | regs->nip += 4; |
| 986 | return; |
| 987 | } |
| 988 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
| 989 | return; |
| 990 | } |
| 991 | |
| 992 | local_irq_enable(); |
| 993 | |
| 994 | #ifdef CONFIG_MATH_EMULATION |
| 995 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
| 996 | * but there seems to be a hardware bug on the 405GP (RevD) |
| 997 | * that means ESR is sometimes set incorrectly - either to |
| 998 | * ESR_DST (!?) or 0. In the process of chasing this with the |
| 999 | * hardware people - not sure if it can happen on any illegal |
| 1000 | * instruction or only on FP instructions, whether there is a |
| 1001 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
| 1002 | switch (do_mathemu(regs)) { |
| 1003 | case 0: |
| 1004 | emulate_single_step(regs); |
| 1005 | return; |
| 1006 | case 1: { |
| 1007 | int code = 0; |
| 1008 | code = __parse_fpscr(current->thread.fpscr.val); |
| 1009 | _exception(SIGFPE, regs, code, regs->nip); |
| 1010 | return; |
| 1011 | } |
| 1012 | case -EFAULT: |
| 1013 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1014 | return; |
| 1015 | } |
| 1016 | /* fall through on any other errors */ |
| 1017 | #endif /* CONFIG_MATH_EMULATION */ |
| 1018 | |
| 1019 | /* Try to emulate it if we should. */ |
| 1020 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { |
| 1021 | switch (emulate_instruction(regs)) { |
| 1022 | case 0: |
| 1023 | regs->nip += 4; |
| 1024 | emulate_single_step(regs); |
| 1025 | return; |
| 1026 | case -EFAULT: |
| 1027 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1028 | return; |
| 1029 | } |
| 1030 | } |
| 1031 | |
| 1032 | if (reason & REASON_PRIVILEGED) |
| 1033 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); |
| 1034 | else |
| 1035 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1036 | } |
| 1037 | |
| 1038 | void alignment_exception(struct pt_regs *regs) |
| 1039 | { |
| 1040 | int sig, code, fixed = 0; |
| 1041 | |
| 1042 | /* we don't implement logging of alignment exceptions */ |
| 1043 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) |
| 1044 | fixed = fix_alignment(regs); |
| 1045 | |
| 1046 | if (fixed == 1) { |
| 1047 | regs->nip += 4; /* skip over emulated instruction */ |
| 1048 | emulate_single_step(regs); |
| 1049 | return; |
| 1050 | } |
| 1051 | |
| 1052 | /* Operand address was bad */ |
| 1053 | if (fixed == -EFAULT) { |
| 1054 | sig = SIGSEGV; |
| 1055 | code = SEGV_ACCERR; |
| 1056 | } else { |
| 1057 | sig = SIGBUS; |
| 1058 | code = BUS_ADRALN; |
| 1059 | } |
| 1060 | if (user_mode(regs)) |
| 1061 | _exception(sig, regs, code, regs->dar); |
| 1062 | else |
| 1063 | bad_page_fault(regs, regs->dar, sig); |
| 1064 | } |
| 1065 | |
| 1066 | void StackOverflow(struct pt_regs *regs) |
| 1067 | { |
| 1068 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", |
| 1069 | current, regs->gpr[1]); |
| 1070 | debugger(regs); |
| 1071 | show_regs(regs); |
| 1072 | panic("kernel stack overflow"); |
| 1073 | } |
| 1074 | |
| 1075 | void nonrecoverable_exception(struct pt_regs *regs) |
| 1076 | { |
| 1077 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", |
| 1078 | regs->nip, regs->msr); |
| 1079 | debugger(regs); |
| 1080 | die("nonrecoverable exception", regs, SIGKILL); |
| 1081 | } |
| 1082 | |
| 1083 | void trace_syscall(struct pt_regs *regs) |
| 1084 | { |
| 1085 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", |
| 1086 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
| 1087 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
| 1088 | } |
| 1089 | |
| 1090 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
| 1091 | { |
| 1092 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
| 1093 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1094 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); |
| 1095 | } |
| 1096 | |
| 1097 | void altivec_unavailable_exception(struct pt_regs *regs) |
| 1098 | { |
| 1099 | if (user_mode(regs)) { |
| 1100 | /* A user program has executed an altivec instruction, |
| 1101 | but this kernel doesn't support altivec. */ |
| 1102 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1103 | return; |
| 1104 | } |
| 1105 | |
| 1106 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
| 1107 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1108 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); |
| 1109 | } |
| 1110 | |
| 1111 | void vsx_unavailable_exception(struct pt_regs *regs) |
| 1112 | { |
| 1113 | if (user_mode(regs)) { |
| 1114 | /* A user program has executed an vsx instruction, |
| 1115 | but this kernel doesn't support vsx. */ |
| 1116 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1117 | return; |
| 1118 | } |
| 1119 | |
| 1120 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " |
| 1121 | "%lx at %lx\n", regs->trap, regs->nip); |
| 1122 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); |
| 1123 | } |
| 1124 | |
| 1125 | void performance_monitor_exception(struct pt_regs *regs) |
| 1126 | { |
| 1127 | __get_cpu_var(irq_stat).pmu_irqs++; |
| 1128 | |
| 1129 | perf_irq(regs); |
| 1130 | } |
| 1131 | |
| 1132 | #ifdef CONFIG_8xx |
| 1133 | void SoftwareEmulation(struct pt_regs *regs) |
| 1134 | { |
| 1135 | extern int do_mathemu(struct pt_regs *); |
| 1136 | extern int Soft_emulate_8xx(struct pt_regs *); |
| 1137 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1138 | int errcode; |
| 1139 | #endif |
| 1140 | |
| 1141 | CHECK_FULL_REGS(regs); |
| 1142 | |
| 1143 | if (!user_mode(regs)) { |
| 1144 | debugger(regs); |
| 1145 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); |
| 1146 | } |
| 1147 | |
| 1148 | #ifdef CONFIG_MATH_EMULATION |
| 1149 | errcode = do_mathemu(regs); |
| 1150 | if (errcode >= 0) |
| 1151 | PPC_WARN_EMULATED(math, regs); |
| 1152 | |
| 1153 | switch (errcode) { |
| 1154 | case 0: |
| 1155 | emulate_single_step(regs); |
| 1156 | return; |
| 1157 | case 1: { |
| 1158 | int code = 0; |
| 1159 | code = __parse_fpscr(current->thread.fpscr.val); |
| 1160 | _exception(SIGFPE, regs, code, regs->nip); |
| 1161 | return; |
| 1162 | } |
| 1163 | case -EFAULT: |
| 1164 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1165 | return; |
| 1166 | default: |
| 1167 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1168 | return; |
| 1169 | } |
| 1170 | |
| 1171 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1172 | errcode = Soft_emulate_8xx(regs); |
| 1173 | if (errcode >= 0) |
| 1174 | PPC_WARN_EMULATED(8xx, regs); |
| 1175 | |
| 1176 | switch (errcode) { |
| 1177 | case 0: |
| 1178 | emulate_single_step(regs); |
| 1179 | return; |
| 1180 | case 1: |
| 1181 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1182 | return; |
| 1183 | case -EFAULT: |
| 1184 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); |
| 1185 | return; |
| 1186 | } |
| 1187 | #else |
| 1188 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1189 | #endif |
| 1190 | } |
| 1191 | #endif /* CONFIG_8xx */ |
| 1192 | |
| 1193 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
| 1194 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
| 1195 | { |
| 1196 | int changed = 0; |
| 1197 | /* |
| 1198 | * Determine the cause of the debug event, clear the |
| 1199 | * event flags and send a trap to the handler. Torez |
| 1200 | */ |
| 1201 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
| 1202 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
| 1203 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE |
| 1204 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; |
| 1205 | #endif |
| 1206 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, |
| 1207 | 5); |
| 1208 | changed |= 0x01; |
| 1209 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { |
| 1210 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
| 1211 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, |
| 1212 | 6); |
| 1213 | changed |= 0x01; |
| 1214 | } else if (debug_status & DBSR_IAC1) { |
| 1215 | current->thread.dbcr0 &= ~DBCR0_IAC1; |
| 1216 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
| 1217 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, |
| 1218 | 1); |
| 1219 | changed |= 0x01; |
| 1220 | } else if (debug_status & DBSR_IAC2) { |
| 1221 | current->thread.dbcr0 &= ~DBCR0_IAC2; |
| 1222 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
| 1223 | 2); |
| 1224 | changed |= 0x01; |
| 1225 | } else if (debug_status & DBSR_IAC3) { |
| 1226 | current->thread.dbcr0 &= ~DBCR0_IAC3; |
| 1227 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
| 1228 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, |
| 1229 | 3); |
| 1230 | changed |= 0x01; |
| 1231 | } else if (debug_status & DBSR_IAC4) { |
| 1232 | current->thread.dbcr0 &= ~DBCR0_IAC4; |
| 1233 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
| 1234 | 4); |
| 1235 | changed |= 0x01; |
| 1236 | } |
| 1237 | /* |
| 1238 | * At the point this routine was called, the MSR(DE) was turned off. |
| 1239 | * Check all other debug flags and see if that bit needs to be turned |
| 1240 | * back on or not. |
| 1241 | */ |
| 1242 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) |
| 1243 | regs->msr |= MSR_DE; |
| 1244 | else |
| 1245 | /* Make sure the IDM flag is off */ |
| 1246 | current->thread.dbcr0 &= ~DBCR0_IDM; |
| 1247 | |
| 1248 | if (changed & 0x01) |
| 1249 | mtspr(SPRN_DBCR0, current->thread.dbcr0); |
| 1250 | } |
| 1251 | |
| 1252 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
| 1253 | { |
| 1254 | current->thread.dbsr = debug_status; |
| 1255 | |
| 1256 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
| 1257 | * on server, it stops on the target of the branch. In order to simulate |
| 1258 | * the server behaviour, we thus restart right away with a single step |
| 1259 | * instead of stopping here when hitting a BT |
| 1260 | */ |
| 1261 | if (debug_status & DBSR_BT) { |
| 1262 | regs->msr &= ~MSR_DE; |
| 1263 | |
| 1264 | /* Disable BT */ |
| 1265 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); |
| 1266 | /* Clear the BT event */ |
| 1267 | mtspr(SPRN_DBSR, DBSR_BT); |
| 1268 | |
| 1269 | /* Do the single step trick only when coming from userspace */ |
| 1270 | if (user_mode(regs)) { |
| 1271 | current->thread.dbcr0 &= ~DBCR0_BT; |
| 1272 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
| 1273 | regs->msr |= MSR_DE; |
| 1274 | return; |
| 1275 | } |
| 1276 | |
| 1277 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
| 1278 | 5, SIGTRAP) == NOTIFY_STOP) { |
| 1279 | return; |
| 1280 | } |
| 1281 | if (debugger_sstep(regs)) |
| 1282 | return; |
| 1283 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ |
| 1284 | regs->msr &= ~MSR_DE; |
| 1285 | |
| 1286 | /* Disable instruction completion */ |
| 1287 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); |
| 1288 | /* Clear the instruction completion event */ |
| 1289 | mtspr(SPRN_DBSR, DBSR_IC); |
| 1290 | |
| 1291 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
| 1292 | 5, SIGTRAP) == NOTIFY_STOP) { |
| 1293 | return; |
| 1294 | } |
| 1295 | |
| 1296 | if (debugger_sstep(regs)) |
| 1297 | return; |
| 1298 | |
| 1299 | if (user_mode(regs)) { |
| 1300 | current->thread.dbcr0 &= ~DBCR0_IC; |
| 1301 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, |
| 1302 | current->thread.dbcr1)) |
| 1303 | regs->msr |= MSR_DE; |
| 1304 | else |
| 1305 | /* Make sure the IDM bit is off */ |
| 1306 | current->thread.dbcr0 &= ~DBCR0_IDM; |
| 1307 | } |
| 1308 | |
| 1309 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); |
| 1310 | } else |
| 1311 | handle_debug(regs, debug_status); |
| 1312 | } |
| 1313 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
| 1314 | |
| 1315 | #if !defined(CONFIG_TAU_INT) |
| 1316 | void TAUException(struct pt_regs *regs) |
| 1317 | { |
| 1318 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", |
| 1319 | regs->nip, regs->msr, regs->trap, print_tainted()); |
| 1320 | } |
| 1321 | #endif /* CONFIG_INT_TAU */ |
| 1322 | |
| 1323 | #ifdef CONFIG_ALTIVEC |
| 1324 | void altivec_assist_exception(struct pt_regs *regs) |
| 1325 | { |
| 1326 | int err; |
| 1327 | |
| 1328 | if (!user_mode(regs)) { |
| 1329 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" |
| 1330 | " at %lx\n", regs->nip); |
| 1331 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
| 1332 | } |
| 1333 | |
| 1334 | flush_altivec_to_thread(current); |
| 1335 | |
| 1336 | PPC_WARN_EMULATED(altivec, regs); |
| 1337 | err = emulate_altivec(regs); |
| 1338 | if (err == 0) { |
| 1339 | regs->nip += 4; /* skip emulated instruction */ |
| 1340 | emulate_single_step(regs); |
| 1341 | return; |
| 1342 | } |
| 1343 | |
| 1344 | if (err == -EFAULT) { |
| 1345 | /* got an error reading the instruction */ |
| 1346 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1347 | } else { |
| 1348 | /* didn't recognize the instruction */ |
| 1349 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ |
| 1350 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
| 1351 | "in %s at %lx\n", current->comm, regs->nip); |
| 1352 | current->thread.vscr.u[3] |= 0x10000; |
| 1353 | } |
| 1354 | } |
| 1355 | #endif /* CONFIG_ALTIVEC */ |
| 1356 | |
| 1357 | #ifdef CONFIG_VSX |
| 1358 | void vsx_assist_exception(struct pt_regs *regs) |
| 1359 | { |
| 1360 | if (!user_mode(regs)) { |
| 1361 | printk(KERN_EMERG "VSX assist exception in kernel mode" |
| 1362 | " at %lx\n", regs->nip); |
| 1363 | die("Kernel VSX assist exception", regs, SIGILL); |
| 1364 | } |
| 1365 | |
| 1366 | flush_vsx_to_thread(current); |
| 1367 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); |
| 1368 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); |
| 1369 | } |
| 1370 | #endif /* CONFIG_VSX */ |
| 1371 | |
| 1372 | #ifdef CONFIG_FSL_BOOKE |
| 1373 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
| 1374 | unsigned long error_code) |
| 1375 | { |
| 1376 | /* We treat cache locking instructions from the user |
| 1377 | * as priv ops, in the future we could try to do |
| 1378 | * something smarter |
| 1379 | */ |
| 1380 | if (error_code & (ESR_DLK|ESR_ILK)) |
| 1381 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); |
| 1382 | return; |
| 1383 | } |
| 1384 | #endif /* CONFIG_FSL_BOOKE */ |
| 1385 | |
| 1386 | #ifdef CONFIG_SPE |
| 1387 | void SPEFloatingPointException(struct pt_regs *regs) |
| 1388 | { |
| 1389 | extern int do_spe_mathemu(struct pt_regs *regs); |
| 1390 | unsigned long spefscr; |
| 1391 | int fpexc_mode; |
| 1392 | int code = 0; |
| 1393 | int err; |
| 1394 | |
| 1395 | flush_spe_to_thread(current); |
| 1396 | |
| 1397 | spefscr = current->thread.spefscr; |
| 1398 | fpexc_mode = current->thread.fpexc_mode; |
| 1399 | |
| 1400 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
| 1401 | code = FPE_FLTOVF; |
| 1402 | } |
| 1403 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { |
| 1404 | code = FPE_FLTUND; |
| 1405 | } |
| 1406 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) |
| 1407 | code = FPE_FLTDIV; |
| 1408 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { |
| 1409 | code = FPE_FLTINV; |
| 1410 | } |
| 1411 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) |
| 1412 | code = FPE_FLTRES; |
| 1413 | |
| 1414 | err = do_spe_mathemu(regs); |
| 1415 | if (err == 0) { |
| 1416 | regs->nip += 4; /* skip emulated instruction */ |
| 1417 | emulate_single_step(regs); |
| 1418 | return; |
| 1419 | } |
| 1420 | |
| 1421 | if (err == -EFAULT) { |
| 1422 | /* got an error reading the instruction */ |
| 1423 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1424 | } else if (err == -EINVAL) { |
| 1425 | /* didn't recognize the instruction */ |
| 1426 | printk(KERN_ERR "unrecognized spe instruction " |
| 1427 | "in %s at %lx\n", current->comm, regs->nip); |
| 1428 | } else { |
| 1429 | _exception(SIGFPE, regs, code, regs->nip); |
| 1430 | } |
| 1431 | |
| 1432 | return; |
| 1433 | } |
| 1434 | |
| 1435 | void SPEFloatingPointRoundException(struct pt_regs *regs) |
| 1436 | { |
| 1437 | extern int speround_handler(struct pt_regs *regs); |
| 1438 | int err; |
| 1439 | |
| 1440 | preempt_disable(); |
| 1441 | if (regs->msr & MSR_SPE) |
| 1442 | giveup_spe(current); |
| 1443 | preempt_enable(); |
| 1444 | |
| 1445 | regs->nip -= 4; |
| 1446 | err = speround_handler(regs); |
| 1447 | if (err == 0) { |
| 1448 | regs->nip += 4; /* skip emulated instruction */ |
| 1449 | emulate_single_step(regs); |
| 1450 | return; |
| 1451 | } |
| 1452 | |
| 1453 | if (err == -EFAULT) { |
| 1454 | /* got an error reading the instruction */ |
| 1455 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); |
| 1456 | } else if (err == -EINVAL) { |
| 1457 | /* didn't recognize the instruction */ |
| 1458 | printk(KERN_ERR "unrecognized spe instruction " |
| 1459 | "in %s at %lx\n", current->comm, regs->nip); |
| 1460 | } else { |
| 1461 | _exception(SIGFPE, regs, 0, regs->nip); |
| 1462 | return; |
| 1463 | } |
| 1464 | } |
| 1465 | #endif |
| 1466 | |
| 1467 | /* |
| 1468 | * We enter here if we get an unrecoverable exception, that is, one |
| 1469 | * that happened at a point where the RI (recoverable interrupt) bit |
| 1470 | * in the MSR is 0. This indicates that SRR0/1 are live, and that |
| 1471 | * we therefore lost state by taking this exception. |
| 1472 | */ |
| 1473 | void unrecoverable_exception(struct pt_regs *regs) |
| 1474 | { |
| 1475 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", |
| 1476 | regs->trap, regs->nip); |
| 1477 | die("Unrecoverable exception", regs, SIGABRT); |
| 1478 | } |
| 1479 | |
| 1480 | #ifdef CONFIG_BOOKE_WDT |
| 1481 | /* |
| 1482 | * Default handler for a Watchdog exception, |
| 1483 | * spins until a reboot occurs |
| 1484 | */ |
| 1485 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) |
| 1486 | { |
| 1487 | /* Generic WatchdogHandler, implement your own */ |
| 1488 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); |
| 1489 | return; |
| 1490 | } |
| 1491 | |
| 1492 | void WatchdogException(struct pt_regs *regs) |
| 1493 | { |
| 1494 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); |
| 1495 | WatchdogHandler(regs); |
| 1496 | } |
| 1497 | #endif |
| 1498 | |
| 1499 | /* |
| 1500 | * We enter here if we discover during exception entry that we are |
| 1501 | * running in supervisor mode with a userspace value in the stack pointer. |
| 1502 | */ |
| 1503 | void kernel_bad_stack(struct pt_regs *regs) |
| 1504 | { |
| 1505 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", |
| 1506 | regs->gpr[1], regs->nip); |
| 1507 | die("Bad kernel stack pointer", regs, SIGABRT); |
| 1508 | } |
| 1509 | |
| 1510 | void __init trap_init(void) |
| 1511 | { |
| 1512 | } |
| 1513 | |
| 1514 | |
| 1515 | #ifdef CONFIG_PPC_EMULATED_STATS |
| 1516 | |
| 1517 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } |
| 1518 | |
| 1519 | struct ppc_emulated ppc_emulated = { |
| 1520 | #ifdef CONFIG_ALTIVEC |
| 1521 | WARN_EMULATED_SETUP(altivec), |
| 1522 | #endif |
| 1523 | WARN_EMULATED_SETUP(dcba), |
| 1524 | WARN_EMULATED_SETUP(dcbz), |
| 1525 | WARN_EMULATED_SETUP(fp_pair), |
| 1526 | WARN_EMULATED_SETUP(isel), |
| 1527 | WARN_EMULATED_SETUP(mcrxr), |
| 1528 | WARN_EMULATED_SETUP(mfpvr), |
| 1529 | WARN_EMULATED_SETUP(multiple), |
| 1530 | WARN_EMULATED_SETUP(popcntb), |
| 1531 | WARN_EMULATED_SETUP(spe), |
| 1532 | WARN_EMULATED_SETUP(string), |
| 1533 | WARN_EMULATED_SETUP(unaligned), |
| 1534 | #ifdef CONFIG_MATH_EMULATION |
| 1535 | WARN_EMULATED_SETUP(math), |
| 1536 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
| 1537 | WARN_EMULATED_SETUP(8xx), |
| 1538 | #endif |
| 1539 | #ifdef CONFIG_VSX |
| 1540 | WARN_EMULATED_SETUP(vsx), |
| 1541 | #endif |
| 1542 | #ifdef CONFIG_PPC64 |
| 1543 | WARN_EMULATED_SETUP(mfdscr), |
| 1544 | WARN_EMULATED_SETUP(mtdscr), |
| 1545 | #endif |
| 1546 | }; |
| 1547 | |
| 1548 | u32 ppc_warn_emulated; |
| 1549 | |
| 1550 | void ppc_warn_emulated_print(const char *type) |
| 1551 | { |
| 1552 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
| 1553 | type); |
| 1554 | } |
| 1555 | |
| 1556 | static int __init ppc_warn_emulated_init(void) |
| 1557 | { |
| 1558 | struct dentry *dir, *d; |
| 1559 | unsigned int i; |
| 1560 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; |
| 1561 | |
| 1562 | if (!powerpc_debugfs_root) |
| 1563 | return -ENODEV; |
| 1564 | |
| 1565 | dir = debugfs_create_dir("emulated_instructions", |
| 1566 | powerpc_debugfs_root); |
| 1567 | if (!dir) |
| 1568 | return -ENOMEM; |
| 1569 | |
| 1570 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, |
| 1571 | &ppc_warn_emulated); |
| 1572 | if (!d) |
| 1573 | goto fail; |
| 1574 | |
| 1575 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { |
| 1576 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, |
| 1577 | (u32 *)&entries[i].val.counter); |
| 1578 | if (!d) |
| 1579 | goto fail; |
| 1580 | } |
| 1581 | |
| 1582 | return 0; |
| 1583 | |
| 1584 | fail: |
| 1585 | debugfs_remove_recursive(dir); |
| 1586 | return -ENOMEM; |
| 1587 | } |
| 1588 | |
| 1589 | device_initcall(ppc_warn_emulated_init); |
| 1590 | |
| 1591 | #endif /* CONFIG_PPC_EMULATED_STATS */ |