| 1 | /* |
| 2 | * This file contains low-level functions for performing various |
| 3 | * types of TLB invalidations on various processors with no hash |
| 4 | * table. |
| 5 | * |
| 6 | * This file implements the following functions for all no-hash |
| 7 | * processors. Some aren't implemented for some variants. Some |
| 8 | * are inline in tlbflush.h |
| 9 | * |
| 10 | * - tlbil_va |
| 11 | * - tlbil_pid |
| 12 | * - tlbil_all |
| 13 | * - tlbivax_bcast (not yet) |
| 14 | * |
| 15 | * Code mostly moved over from misc_32.S |
| 16 | * |
| 17 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 18 | * |
| 19 | * Partially rewritten by Cort Dougan (cort@cs.nmt.edu) |
| 20 | * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt. |
| 21 | * |
| 22 | * This program is free software; you can redistribute it and/or |
| 23 | * modify it under the terms of the GNU General Public License |
| 24 | * as published by the Free Software Foundation; either version |
| 25 | * 2 of the License, or (at your option) any later version. |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <asm/reg.h> |
| 30 | #include <asm/page.h> |
| 31 | #include <asm/cputable.h> |
| 32 | #include <asm/mmu.h> |
| 33 | #include <asm/ppc_asm.h> |
| 34 | #include <asm/asm-offsets.h> |
| 35 | #include <asm/processor.h> |
| 36 | |
| 37 | #if defined(CONFIG_40x) |
| 38 | |
| 39 | /* |
| 40 | * 40x implementation needs only tlbil_va |
| 41 | */ |
| 42 | _GLOBAL(_tlbil_va) |
| 43 | /* We run the search with interrupts disabled because we have to change |
| 44 | * the PID and I don't want to preempt when that happens. |
| 45 | */ |
| 46 | mfmsr r5 |
| 47 | mfspr r6,SPRN_PID |
| 48 | wrteei 0 |
| 49 | mtspr SPRN_PID,r4 |
| 50 | tlbsx. r3, 0, r3 |
| 51 | mtspr SPRN_PID,r6 |
| 52 | wrtee r5 |
| 53 | bne 1f |
| 54 | sync |
| 55 | /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is |
| 56 | * clear. Since 25 is the V bit in the TLB_TAG, loading this value |
| 57 | * will invalidate the TLB entry. */ |
| 58 | tlbwe r3, r3, TLB_TAG |
| 59 | isync |
| 60 | 1: blr |
| 61 | |
| 62 | #elif defined(CONFIG_8xx) |
| 63 | |
| 64 | /* |
| 65 | * Nothing to do for 8xx, everything is inline |
| 66 | */ |
| 67 | |
| 68 | #elif defined(CONFIG_44x) |
| 69 | |
| 70 | /* |
| 71 | * 440 implementation uses tlbsx/we for tlbil_va and a full sweep |
| 72 | * of the TLB for everything else. |
| 73 | */ |
| 74 | _GLOBAL(_tlbil_va) |
| 75 | mfspr r5,SPRN_MMUCR |
| 76 | rlwimi r5,r4,0,24,31 /* Set TID */ |
| 77 | |
| 78 | /* We have to run the search with interrupts disabled, otherwise |
| 79 | * an interrupt which causes a TLB miss can clobber the MMUCR |
| 80 | * between the mtspr and the tlbsx. |
| 81 | * |
| 82 | * Critical and Machine Check interrupts take care of saving |
| 83 | * and restoring MMUCR, so only normal interrupts have to be |
| 84 | * taken care of. |
| 85 | */ |
| 86 | mfmsr r4 |
| 87 | wrteei 0 |
| 88 | mtspr SPRN_MMUCR,r5 |
| 89 | tlbsx. r3, 0, r3 |
| 90 | wrtee r4 |
| 91 | bne 1f |
| 92 | sync |
| 93 | /* There are only 64 TLB entries, so r3 < 64, |
| 94 | * which means bit 22, is clear. Since 22 is |
| 95 | * the V bit in the TLB_PAGEID, loading this |
| 96 | * value will invalidate the TLB entry. |
| 97 | */ |
| 98 | tlbwe r3, r3, PPC44x_TLB_PAGEID |
| 99 | isync |
| 100 | 1: blr |
| 101 | |
| 102 | _GLOBAL(_tlbil_all) |
| 103 | _GLOBAL(_tlbil_pid) |
| 104 | li r3,0 |
| 105 | sync |
| 106 | |
| 107 | /* Load high watermark */ |
| 108 | lis r4,tlb_44x_hwater@ha |
| 109 | lwz r5,tlb_44x_hwater@l(r4) |
| 110 | |
| 111 | 1: tlbwe r3,r3,PPC44x_TLB_PAGEID |
| 112 | addi r3,r3,1 |
| 113 | cmpw 0,r3,r5 |
| 114 | ble 1b |
| 115 | |
| 116 | isync |
| 117 | blr |
| 118 | |
| 119 | #elif defined(CONFIG_FSL_BOOKE) |
| 120 | /* |
| 121 | * FSL BookE implementations. Currently _pid and _all are the |
| 122 | * same. This will change when tlbilx is actually supported and |
| 123 | * performs invalidate-by-PID. This change will be driven by |
| 124 | * mmu_features conditional |
| 125 | */ |
| 126 | |
| 127 | /* |
| 128 | * Flush MMU TLB on the local processor |
| 129 | */ |
| 130 | _GLOBAL(_tlbil_pid) |
| 131 | _GLOBAL(_tlbil_all) |
| 132 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ |
| 133 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) |
| 134 | li r3,(MMUCSR0_TLBFI)@l |
| 135 | mtspr SPRN_MMUCSR0, r3 |
| 136 | 1: |
| 137 | mfspr r3,SPRN_MMUCSR0 |
| 138 | andi. r3,r3,MMUCSR0_TLBFI@l |
| 139 | bne 1b |
| 140 | msync |
| 141 | isync |
| 142 | blr |
| 143 | |
| 144 | /* |
| 145 | * Flush MMU TLB for a particular address, but only on the local processor |
| 146 | * (no broadcast) |
| 147 | */ |
| 148 | _GLOBAL(_tlbil_va) |
| 149 | mfmsr r10 |
| 150 | wrteei 0 |
| 151 | slwi r4,r4,16 |
| 152 | mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ |
| 153 | tlbsx 0,r3 |
| 154 | mfspr r4,SPRN_MAS1 /* check valid */ |
| 155 | andis. r3,r4,MAS1_VALID@h |
| 156 | beq 1f |
| 157 | rlwinm r4,r4,0,1,31 |
| 158 | mtspr SPRN_MAS1,r4 |
| 159 | tlbwe |
| 160 | msync |
| 161 | isync |
| 162 | 1: wrtee r10 |
| 163 | blr |
| 164 | #elif |
| 165 | #error Unsupported processor type ! |
| 166 | #endif |