| 1 | /* |
| 2 | * SH7343 Setup |
| 3 | * |
| 4 | * Copyright (C) 2006 Paul Mundt |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/serial.h> |
| 13 | #include <linux/serial_sci.h> |
| 14 | #include <linux/uio_driver.h> |
| 15 | #include <linux/sh_timer.h> |
| 16 | #include <asm/clock.h> |
| 17 | |
| 18 | /* Serial */ |
| 19 | static struct plat_sci_port scif0_platform_data = { |
| 20 | .mapbase = 0xffe00000, |
| 21 | .flags = UPF_BOOT_AUTOCONF, |
| 22 | .type = PORT_SCIF, |
| 23 | .irqs = { 80, 80, 80, 80 }, |
| 24 | }; |
| 25 | |
| 26 | static struct platform_device scif0_device = { |
| 27 | .name = "sh-sci", |
| 28 | .id = 0, |
| 29 | .dev = { |
| 30 | .platform_data = &scif0_platform_data, |
| 31 | }, |
| 32 | }; |
| 33 | |
| 34 | static struct plat_sci_port scif1_platform_data = { |
| 35 | .mapbase = 0xffe10000, |
| 36 | .flags = UPF_BOOT_AUTOCONF, |
| 37 | .type = PORT_SCIF, |
| 38 | .irqs = { 81, 81, 81, 81 }, |
| 39 | }; |
| 40 | |
| 41 | static struct platform_device scif1_device = { |
| 42 | .name = "sh-sci", |
| 43 | .id = 1, |
| 44 | .dev = { |
| 45 | .platform_data = &scif1_platform_data, |
| 46 | }, |
| 47 | }; |
| 48 | |
| 49 | static struct plat_sci_port scif2_platform_data = { |
| 50 | .mapbase = 0xffe20000, |
| 51 | .flags = UPF_BOOT_AUTOCONF, |
| 52 | .type = PORT_SCIF, |
| 53 | .irqs = { 82, 82, 82, 82 }, |
| 54 | }; |
| 55 | |
| 56 | static struct platform_device scif2_device = { |
| 57 | .name = "sh-sci", |
| 58 | .id = 2, |
| 59 | .dev = { |
| 60 | .platform_data = &scif2_platform_data, |
| 61 | }, |
| 62 | }; |
| 63 | |
| 64 | static struct plat_sci_port scif3_platform_data = { |
| 65 | .mapbase = 0xffe30000, |
| 66 | .flags = UPF_BOOT_AUTOCONF, |
| 67 | .type = PORT_SCIF, |
| 68 | .irqs = { 83, 83, 83, 83 }, |
| 69 | }; |
| 70 | |
| 71 | static struct platform_device scif3_device = { |
| 72 | .name = "sh-sci", |
| 73 | .id = 3, |
| 74 | .dev = { |
| 75 | .platform_data = &scif3_platform_data, |
| 76 | }, |
| 77 | }; |
| 78 | |
| 79 | static struct resource iic0_resources[] = { |
| 80 | [0] = { |
| 81 | .name = "IIC0", |
| 82 | .start = 0x04470000, |
| 83 | .end = 0x04470017, |
| 84 | .flags = IORESOURCE_MEM, |
| 85 | }, |
| 86 | [1] = { |
| 87 | .start = 96, |
| 88 | .end = 99, |
| 89 | .flags = IORESOURCE_IRQ, |
| 90 | }, |
| 91 | }; |
| 92 | |
| 93 | static struct platform_device iic0_device = { |
| 94 | .name = "i2c-sh_mobile", |
| 95 | .id = 0, /* "i2c0" clock */ |
| 96 | .num_resources = ARRAY_SIZE(iic0_resources), |
| 97 | .resource = iic0_resources, |
| 98 | }; |
| 99 | |
| 100 | static struct resource iic1_resources[] = { |
| 101 | [0] = { |
| 102 | .name = "IIC1", |
| 103 | .start = 0x04750000, |
| 104 | .end = 0x04750017, |
| 105 | .flags = IORESOURCE_MEM, |
| 106 | }, |
| 107 | [1] = { |
| 108 | .start = 44, |
| 109 | .end = 47, |
| 110 | .flags = IORESOURCE_IRQ, |
| 111 | }, |
| 112 | }; |
| 113 | |
| 114 | static struct platform_device iic1_device = { |
| 115 | .name = "i2c-sh_mobile", |
| 116 | .id = 1, /* "i2c1" clock */ |
| 117 | .num_resources = ARRAY_SIZE(iic1_resources), |
| 118 | .resource = iic1_resources, |
| 119 | }; |
| 120 | |
| 121 | static struct uio_info vpu_platform_data = { |
| 122 | .name = "VPU4", |
| 123 | .version = "0", |
| 124 | .irq = 60, |
| 125 | }; |
| 126 | |
| 127 | static struct resource vpu_resources[] = { |
| 128 | [0] = { |
| 129 | .name = "VPU", |
| 130 | .start = 0xfe900000, |
| 131 | .end = 0xfe9022eb, |
| 132 | .flags = IORESOURCE_MEM, |
| 133 | }, |
| 134 | [1] = { |
| 135 | /* place holder for contiguous memory */ |
| 136 | }, |
| 137 | }; |
| 138 | |
| 139 | static struct platform_device vpu_device = { |
| 140 | .name = "uio_pdrv_genirq", |
| 141 | .id = 0, |
| 142 | .dev = { |
| 143 | .platform_data = &vpu_platform_data, |
| 144 | }, |
| 145 | .resource = vpu_resources, |
| 146 | .num_resources = ARRAY_SIZE(vpu_resources), |
| 147 | }; |
| 148 | |
| 149 | static struct uio_info veu_platform_data = { |
| 150 | .name = "VEU", |
| 151 | .version = "0", |
| 152 | .irq = 54, |
| 153 | }; |
| 154 | |
| 155 | static struct resource veu_resources[] = { |
| 156 | [0] = { |
| 157 | .name = "VEU", |
| 158 | .start = 0xfe920000, |
| 159 | .end = 0xfe9200b7, |
| 160 | .flags = IORESOURCE_MEM, |
| 161 | }, |
| 162 | [1] = { |
| 163 | /* place holder for contiguous memory */ |
| 164 | }, |
| 165 | }; |
| 166 | |
| 167 | static struct platform_device veu_device = { |
| 168 | .name = "uio_pdrv_genirq", |
| 169 | .id = 1, |
| 170 | .dev = { |
| 171 | .platform_data = &veu_platform_data, |
| 172 | }, |
| 173 | .resource = veu_resources, |
| 174 | .num_resources = ARRAY_SIZE(veu_resources), |
| 175 | }; |
| 176 | |
| 177 | static struct uio_info jpu_platform_data = { |
| 178 | .name = "JPU", |
| 179 | .version = "0", |
| 180 | .irq = 27, |
| 181 | }; |
| 182 | |
| 183 | static struct resource jpu_resources[] = { |
| 184 | [0] = { |
| 185 | .name = "JPU", |
| 186 | .start = 0xfea00000, |
| 187 | .end = 0xfea102d3, |
| 188 | .flags = IORESOURCE_MEM, |
| 189 | }, |
| 190 | [1] = { |
| 191 | /* place holder for contiguous memory */ |
| 192 | }, |
| 193 | }; |
| 194 | |
| 195 | static struct platform_device jpu_device = { |
| 196 | .name = "uio_pdrv_genirq", |
| 197 | .id = 2, |
| 198 | .dev = { |
| 199 | .platform_data = &jpu_platform_data, |
| 200 | }, |
| 201 | .resource = jpu_resources, |
| 202 | .num_resources = ARRAY_SIZE(jpu_resources), |
| 203 | }; |
| 204 | |
| 205 | static struct sh_timer_config cmt_platform_data = { |
| 206 | .channel_offset = 0x60, |
| 207 | .timer_bit = 5, |
| 208 | .clockevent_rating = 125, |
| 209 | .clocksource_rating = 200, |
| 210 | }; |
| 211 | |
| 212 | static struct resource cmt_resources[] = { |
| 213 | [0] = { |
| 214 | .start = 0x044a0060, |
| 215 | .end = 0x044a006b, |
| 216 | .flags = IORESOURCE_MEM, |
| 217 | }, |
| 218 | [1] = { |
| 219 | .start = 104, |
| 220 | .flags = IORESOURCE_IRQ, |
| 221 | }, |
| 222 | }; |
| 223 | |
| 224 | static struct platform_device cmt_device = { |
| 225 | .name = "sh_cmt", |
| 226 | .id = 0, |
| 227 | .dev = { |
| 228 | .platform_data = &cmt_platform_data, |
| 229 | }, |
| 230 | .resource = cmt_resources, |
| 231 | .num_resources = ARRAY_SIZE(cmt_resources), |
| 232 | }; |
| 233 | |
| 234 | static struct sh_timer_config tmu0_platform_data = { |
| 235 | .channel_offset = 0x04, |
| 236 | .timer_bit = 0, |
| 237 | .clockevent_rating = 200, |
| 238 | }; |
| 239 | |
| 240 | static struct resource tmu0_resources[] = { |
| 241 | [0] = { |
| 242 | .start = 0xffd80008, |
| 243 | .end = 0xffd80013, |
| 244 | .flags = IORESOURCE_MEM, |
| 245 | }, |
| 246 | [1] = { |
| 247 | .start = 16, |
| 248 | .flags = IORESOURCE_IRQ, |
| 249 | }, |
| 250 | }; |
| 251 | |
| 252 | static struct platform_device tmu0_device = { |
| 253 | .name = "sh_tmu", |
| 254 | .id = 0, |
| 255 | .dev = { |
| 256 | .platform_data = &tmu0_platform_data, |
| 257 | }, |
| 258 | .resource = tmu0_resources, |
| 259 | .num_resources = ARRAY_SIZE(tmu0_resources), |
| 260 | }; |
| 261 | |
| 262 | static struct sh_timer_config tmu1_platform_data = { |
| 263 | .channel_offset = 0x10, |
| 264 | .timer_bit = 1, |
| 265 | .clocksource_rating = 200, |
| 266 | }; |
| 267 | |
| 268 | static struct resource tmu1_resources[] = { |
| 269 | [0] = { |
| 270 | .start = 0xffd80014, |
| 271 | .end = 0xffd8001f, |
| 272 | .flags = IORESOURCE_MEM, |
| 273 | }, |
| 274 | [1] = { |
| 275 | .start = 17, |
| 276 | .flags = IORESOURCE_IRQ, |
| 277 | }, |
| 278 | }; |
| 279 | |
| 280 | static struct platform_device tmu1_device = { |
| 281 | .name = "sh_tmu", |
| 282 | .id = 1, |
| 283 | .dev = { |
| 284 | .platform_data = &tmu1_platform_data, |
| 285 | }, |
| 286 | .resource = tmu1_resources, |
| 287 | .num_resources = ARRAY_SIZE(tmu1_resources), |
| 288 | }; |
| 289 | |
| 290 | static struct sh_timer_config tmu2_platform_data = { |
| 291 | .channel_offset = 0x1c, |
| 292 | .timer_bit = 2, |
| 293 | }; |
| 294 | |
| 295 | static struct resource tmu2_resources[] = { |
| 296 | [0] = { |
| 297 | .start = 0xffd80020, |
| 298 | .end = 0xffd8002b, |
| 299 | .flags = IORESOURCE_MEM, |
| 300 | }, |
| 301 | [1] = { |
| 302 | .start = 18, |
| 303 | .flags = IORESOURCE_IRQ, |
| 304 | }, |
| 305 | }; |
| 306 | |
| 307 | static struct platform_device tmu2_device = { |
| 308 | .name = "sh_tmu", |
| 309 | .id = 2, |
| 310 | .dev = { |
| 311 | .platform_data = &tmu2_platform_data, |
| 312 | }, |
| 313 | .resource = tmu2_resources, |
| 314 | .num_resources = ARRAY_SIZE(tmu2_resources), |
| 315 | }; |
| 316 | |
| 317 | static struct platform_device *sh7343_devices[] __initdata = { |
| 318 | &scif0_device, |
| 319 | &scif1_device, |
| 320 | &scif2_device, |
| 321 | &scif3_device, |
| 322 | &cmt_device, |
| 323 | &tmu0_device, |
| 324 | &tmu1_device, |
| 325 | &tmu2_device, |
| 326 | &iic0_device, |
| 327 | &iic1_device, |
| 328 | &vpu_device, |
| 329 | &veu_device, |
| 330 | &jpu_device, |
| 331 | }; |
| 332 | |
| 333 | static int __init sh7343_devices_setup(void) |
| 334 | { |
| 335 | platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); |
| 336 | platform_resource_setup_memory(&veu_device, "veu", 2 << 20); |
| 337 | platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); |
| 338 | |
| 339 | return platform_add_devices(sh7343_devices, |
| 340 | ARRAY_SIZE(sh7343_devices)); |
| 341 | } |
| 342 | arch_initcall(sh7343_devices_setup); |
| 343 | |
| 344 | static struct platform_device *sh7343_early_devices[] __initdata = { |
| 345 | &scif0_device, |
| 346 | &scif1_device, |
| 347 | &scif2_device, |
| 348 | &scif3_device, |
| 349 | &cmt_device, |
| 350 | &tmu0_device, |
| 351 | &tmu1_device, |
| 352 | &tmu2_device, |
| 353 | }; |
| 354 | |
| 355 | void __init plat_early_device_setup(void) |
| 356 | { |
| 357 | early_platform_add_devices(sh7343_early_devices, |
| 358 | ARRAY_SIZE(sh7343_early_devices)); |
| 359 | } |
| 360 | |
| 361 | enum { |
| 362 | UNUSED = 0, |
| 363 | |
| 364 | /* interrupt sources */ |
| 365 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, |
| 366 | DMAC0, DMAC1, DMAC2, DMAC3, |
| 367 | VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, |
| 368 | MFI, VPU, TPU, Z3D4, USBI0, USBI1, |
| 369 | MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, |
| 370 | DMAC4, DMAC5, DMAC_DADERR, |
| 371 | KEYSC, |
| 372 | SCIF, SCIF1, SCIF2, SCIF3, |
| 373 | SIOF0, SIOF1, SIO, |
| 374 | FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, |
| 375 | I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, |
| 376 | I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, |
| 377 | SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, |
| 378 | IRDA, |
| 379 | SDHI0, SDHI1, SDHI2, SDHI3, |
| 380 | CMT, TSIF, SIU, |
| 381 | TMU0, TMU1, TMU2, |
| 382 | JPU, LCDC, |
| 383 | |
| 384 | /* interrupt groups */ |
| 385 | |
| 386 | DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, |
| 387 | }; |
| 388 | |
| 389 | static struct intc_vect vectors[] __initdata = { |
| 390 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
| 391 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
| 392 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
| 393 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), |
| 394 | INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), |
| 395 | INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), |
| 396 | INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), |
| 397 | INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), |
| 398 | INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), |
| 399 | INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), |
| 400 | INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), |
| 401 | INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), |
| 402 | INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), |
| 403 | INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), |
| 404 | INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), |
| 405 | INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), |
| 406 | INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), |
| 407 | INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), |
| 408 | INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), |
| 409 | INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), |
| 410 | INTC_VECT(SIO, 0xd00), |
| 411 | INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), |
| 412 | INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), |
| 413 | INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), |
| 414 | INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), |
| 415 | INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), |
| 416 | INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), |
| 417 | INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), |
| 418 | INTC_VECT(SIU, 0xf80), |
| 419 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
| 420 | INTC_VECT(TMU2, 0x440), |
| 421 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), |
| 422 | }; |
| 423 | |
| 424 | static struct intc_group groups[] __initdata = { |
| 425 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), |
| 426 | INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), |
| 427 | INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), |
| 428 | INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), |
| 429 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, |
| 430 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), |
| 431 | INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), |
| 432 | INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), |
| 433 | INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), |
| 434 | INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), |
| 435 | INTC_GROUP(USB, USBI0, USBI1), |
| 436 | }; |
| 437 | |
| 438 | static struct intc_mask_reg mask_registers[] __initdata = { |
| 439 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
| 440 | { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, |
| 441 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ |
| 442 | { 0, 0, 0, VPU, 0, 0, 0, MFI } }, |
| 443 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ |
| 444 | { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, |
| 445 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ |
| 446 | { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, |
| 447 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ |
| 448 | { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, |
| 449 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ |
| 450 | { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, |
| 451 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ |
| 452 | { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, |
| 453 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, |
| 454 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ |
| 455 | { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, |
| 456 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
| 457 | { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, |
| 458 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
| 459 | { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, |
| 460 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ |
| 461 | { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, |
| 462 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ |
| 463 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 464 | }; |
| 465 | |
| 466 | static struct intc_prio_reg prio_registers[] __initdata = { |
| 467 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, |
| 468 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, |
| 469 | { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, |
| 470 | { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, |
| 471 | { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, |
| 472 | { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, |
| 473 | { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, |
| 474 | { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, |
| 475 | { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, |
| 476 | { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, |
| 477 | { 0xa4140010, 0, 32, 4, /* INTPRI00 */ |
| 478 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 479 | }; |
| 480 | |
| 481 | static struct intc_sense_reg sense_registers[] __initdata = { |
| 482 | { 0xa414001c, 16, 2, /* ICR1 */ |
| 483 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 484 | }; |
| 485 | |
| 486 | static struct intc_mask_reg ack_registers[] __initdata = { |
| 487 | { 0xa4140024, 0, 8, /* INTREQ00 */ |
| 488 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
| 489 | }; |
| 490 | |
| 491 | static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, |
| 492 | mask_registers, prio_registers, sense_registers, |
| 493 | ack_registers); |
| 494 | |
| 495 | void __init plat_irq_setup(void) |
| 496 | { |
| 497 | register_intc_controller(&intc_desc); |
| 498 | } |