| 1 | /* pci.c: UltraSparc PCI controller support. |
| 2 | * |
| 3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) |
| 4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
| 5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) |
| 6 | * |
| 7 | * OF tree based PCI bus probing taken from the PowerPC port |
| 8 | * with minor modifications, see there for credits. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/export.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/string.h> |
| 14 | #include <linux/sched.h> |
| 15 | #include <linux/capability.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/msi.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | |
| 24 | #include <asm/uaccess.h> |
| 25 | #include <asm/pgtable.h> |
| 26 | #include <asm/irq.h> |
| 27 | #include <asm/prom.h> |
| 28 | #include <asm/apb.h> |
| 29 | |
| 30 | #include "pci_impl.h" |
| 31 | |
| 32 | /* List of all PCI controllers found in the system. */ |
| 33 | struct pci_pbm_info *pci_pbm_root = NULL; |
| 34 | |
| 35 | /* Each PBM found gets a unique index. */ |
| 36 | int pci_num_pbms = 0; |
| 37 | |
| 38 | volatile int pci_poke_in_progress; |
| 39 | volatile int pci_poke_cpu = -1; |
| 40 | volatile int pci_poke_faulted; |
| 41 | |
| 42 | static DEFINE_SPINLOCK(pci_poke_lock); |
| 43 | |
| 44 | void pci_config_read8(u8 *addr, u8 *ret) |
| 45 | { |
| 46 | unsigned long flags; |
| 47 | u8 byte; |
| 48 | |
| 49 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 50 | pci_poke_cpu = smp_processor_id(); |
| 51 | pci_poke_in_progress = 1; |
| 52 | pci_poke_faulted = 0; |
| 53 | __asm__ __volatile__("membar #Sync\n\t" |
| 54 | "lduba [%1] %2, %0\n\t" |
| 55 | "membar #Sync" |
| 56 | : "=r" (byte) |
| 57 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 58 | : "memory"); |
| 59 | pci_poke_in_progress = 0; |
| 60 | pci_poke_cpu = -1; |
| 61 | if (!pci_poke_faulted) |
| 62 | *ret = byte; |
| 63 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 64 | } |
| 65 | |
| 66 | void pci_config_read16(u16 *addr, u16 *ret) |
| 67 | { |
| 68 | unsigned long flags; |
| 69 | u16 word; |
| 70 | |
| 71 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 72 | pci_poke_cpu = smp_processor_id(); |
| 73 | pci_poke_in_progress = 1; |
| 74 | pci_poke_faulted = 0; |
| 75 | __asm__ __volatile__("membar #Sync\n\t" |
| 76 | "lduha [%1] %2, %0\n\t" |
| 77 | "membar #Sync" |
| 78 | : "=r" (word) |
| 79 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 80 | : "memory"); |
| 81 | pci_poke_in_progress = 0; |
| 82 | pci_poke_cpu = -1; |
| 83 | if (!pci_poke_faulted) |
| 84 | *ret = word; |
| 85 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 86 | } |
| 87 | |
| 88 | void pci_config_read32(u32 *addr, u32 *ret) |
| 89 | { |
| 90 | unsigned long flags; |
| 91 | u32 dword; |
| 92 | |
| 93 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 94 | pci_poke_cpu = smp_processor_id(); |
| 95 | pci_poke_in_progress = 1; |
| 96 | pci_poke_faulted = 0; |
| 97 | __asm__ __volatile__("membar #Sync\n\t" |
| 98 | "lduwa [%1] %2, %0\n\t" |
| 99 | "membar #Sync" |
| 100 | : "=r" (dword) |
| 101 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 102 | : "memory"); |
| 103 | pci_poke_in_progress = 0; |
| 104 | pci_poke_cpu = -1; |
| 105 | if (!pci_poke_faulted) |
| 106 | *ret = dword; |
| 107 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 108 | } |
| 109 | |
| 110 | void pci_config_write8(u8 *addr, u8 val) |
| 111 | { |
| 112 | unsigned long flags; |
| 113 | |
| 114 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 115 | pci_poke_cpu = smp_processor_id(); |
| 116 | pci_poke_in_progress = 1; |
| 117 | pci_poke_faulted = 0; |
| 118 | __asm__ __volatile__("membar #Sync\n\t" |
| 119 | "stba %0, [%1] %2\n\t" |
| 120 | "membar #Sync" |
| 121 | : /* no outputs */ |
| 122 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 123 | : "memory"); |
| 124 | pci_poke_in_progress = 0; |
| 125 | pci_poke_cpu = -1; |
| 126 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 127 | } |
| 128 | |
| 129 | void pci_config_write16(u16 *addr, u16 val) |
| 130 | { |
| 131 | unsigned long flags; |
| 132 | |
| 133 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 134 | pci_poke_cpu = smp_processor_id(); |
| 135 | pci_poke_in_progress = 1; |
| 136 | pci_poke_faulted = 0; |
| 137 | __asm__ __volatile__("membar #Sync\n\t" |
| 138 | "stha %0, [%1] %2\n\t" |
| 139 | "membar #Sync" |
| 140 | : /* no outputs */ |
| 141 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 142 | : "memory"); |
| 143 | pci_poke_in_progress = 0; |
| 144 | pci_poke_cpu = -1; |
| 145 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 146 | } |
| 147 | |
| 148 | void pci_config_write32(u32 *addr, u32 val) |
| 149 | { |
| 150 | unsigned long flags; |
| 151 | |
| 152 | spin_lock_irqsave(&pci_poke_lock, flags); |
| 153 | pci_poke_cpu = smp_processor_id(); |
| 154 | pci_poke_in_progress = 1; |
| 155 | pci_poke_faulted = 0; |
| 156 | __asm__ __volatile__("membar #Sync\n\t" |
| 157 | "stwa %0, [%1] %2\n\t" |
| 158 | "membar #Sync" |
| 159 | : /* no outputs */ |
| 160 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) |
| 161 | : "memory"); |
| 162 | pci_poke_in_progress = 0; |
| 163 | pci_poke_cpu = -1; |
| 164 | spin_unlock_irqrestore(&pci_poke_lock, flags); |
| 165 | } |
| 166 | |
| 167 | static int ofpci_verbose; |
| 168 | |
| 169 | static int __init ofpci_debug(char *str) |
| 170 | { |
| 171 | int val = 0; |
| 172 | |
| 173 | get_option(&str, &val); |
| 174 | if (val) |
| 175 | ofpci_verbose = 1; |
| 176 | return 1; |
| 177 | } |
| 178 | |
| 179 | __setup("ofpci_debug=", ofpci_debug); |
| 180 | |
| 181 | static unsigned long pci_parse_of_flags(u32 addr0) |
| 182 | { |
| 183 | unsigned long flags = 0; |
| 184 | |
| 185 | if (addr0 & 0x02000000) { |
| 186 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
| 187 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; |
| 188 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; |
| 189 | if (addr0 & 0x40000000) |
| 190 | flags |= IORESOURCE_PREFETCH |
| 191 | | PCI_BASE_ADDRESS_MEM_PREFETCH; |
| 192 | } else if (addr0 & 0x01000000) |
| 193 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
| 194 | return flags; |
| 195 | } |
| 196 | |
| 197 | /* The of_device layer has translated all of the assigned-address properties |
| 198 | * into physical address resources, we only have to figure out the register |
| 199 | * mapping. |
| 200 | */ |
| 201 | static void pci_parse_of_addrs(struct platform_device *op, |
| 202 | struct device_node *node, |
| 203 | struct pci_dev *dev) |
| 204 | { |
| 205 | struct resource *op_res; |
| 206 | const u32 *addrs; |
| 207 | int proplen; |
| 208 | |
| 209 | addrs = of_get_property(node, "assigned-addresses", &proplen); |
| 210 | if (!addrs) |
| 211 | return; |
| 212 | if (ofpci_verbose) |
| 213 | printk(" parse addresses (%d bytes) @ %p\n", |
| 214 | proplen, addrs); |
| 215 | op_res = &op->resource[0]; |
| 216 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { |
| 217 | struct resource *res; |
| 218 | unsigned long flags; |
| 219 | int i; |
| 220 | |
| 221 | flags = pci_parse_of_flags(addrs[0]); |
| 222 | if (!flags) |
| 223 | continue; |
| 224 | i = addrs[0] & 0xff; |
| 225 | if (ofpci_verbose) |
| 226 | printk(" start: %llx, end: %llx, i: %x\n", |
| 227 | op_res->start, op_res->end, i); |
| 228 | |
| 229 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { |
| 230 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; |
| 231 | } else if (i == dev->rom_base_reg) { |
| 232 | res = &dev->resource[PCI_ROM_RESOURCE]; |
| 233 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
| 234 | | IORESOURCE_SIZEALIGN; |
| 235 | } else { |
| 236 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); |
| 237 | continue; |
| 238 | } |
| 239 | res->start = op_res->start; |
| 240 | res->end = op_res->end; |
| 241 | res->flags = flags; |
| 242 | res->name = pci_name(dev); |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, |
| 247 | struct device_node *node, |
| 248 | struct pci_bus *bus, int devfn) |
| 249 | { |
| 250 | struct dev_archdata *sd; |
| 251 | struct pci_slot *slot; |
| 252 | struct platform_device *op; |
| 253 | struct pci_dev *dev; |
| 254 | const char *type; |
| 255 | u32 class; |
| 256 | |
| 257 | dev = alloc_pci_dev(); |
| 258 | if (!dev) |
| 259 | return NULL; |
| 260 | |
| 261 | sd = &dev->dev.archdata; |
| 262 | sd->iommu = pbm->iommu; |
| 263 | sd->stc = &pbm->stc; |
| 264 | sd->host_controller = pbm; |
| 265 | sd->op = op = of_find_device_by_node(node); |
| 266 | sd->numa_node = pbm->numa_node; |
| 267 | |
| 268 | sd = &op->dev.archdata; |
| 269 | sd->iommu = pbm->iommu; |
| 270 | sd->stc = &pbm->stc; |
| 271 | sd->numa_node = pbm->numa_node; |
| 272 | |
| 273 | if (!strcmp(node->name, "ebus")) |
| 274 | of_propagate_archdata(op); |
| 275 | |
| 276 | type = of_get_property(node, "device_type", NULL); |
| 277 | if (type == NULL) |
| 278 | type = ""; |
| 279 | |
| 280 | if (ofpci_verbose) |
| 281 | printk(" create device, devfn: %x, type: %s\n", |
| 282 | devfn, type); |
| 283 | |
| 284 | dev->bus = bus; |
| 285 | dev->sysdata = node; |
| 286 | dev->dev.parent = bus->bridge; |
| 287 | dev->dev.bus = &pci_bus_type; |
| 288 | dev->dev.of_node = of_node_get(node); |
| 289 | dev->devfn = devfn; |
| 290 | dev->multifunction = 0; /* maybe a lie? */ |
| 291 | set_pcie_port_type(dev); |
| 292 | |
| 293 | list_for_each_entry(slot, &dev->bus->slots, list) |
| 294 | if (PCI_SLOT(dev->devfn) == slot->number) |
| 295 | dev->slot = slot; |
| 296 | |
| 297 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); |
| 298 | dev->device = of_getintprop_default(node, "device-id", 0xffff); |
| 299 | dev->subsystem_vendor = |
| 300 | of_getintprop_default(node, "subsystem-vendor-id", 0); |
| 301 | dev->subsystem_device = |
| 302 | of_getintprop_default(node, "subsystem-id", 0); |
| 303 | |
| 304 | dev->cfg_size = pci_cfg_space_size(dev); |
| 305 | |
| 306 | /* We can't actually use the firmware value, we have |
| 307 | * to read what is in the register right now. One |
| 308 | * reason is that in the case of IDE interfaces the |
| 309 | * firmware can sample the value before the the IDE |
| 310 | * interface is programmed into native mode. |
| 311 | */ |
| 312 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); |
| 313 | dev->class = class >> 8; |
| 314 | dev->revision = class & 0xff; |
| 315 | |
| 316 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), |
| 317 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 318 | |
| 319 | if (ofpci_verbose) |
| 320 | printk(" class: 0x%x device name: %s\n", |
| 321 | dev->class, pci_name(dev)); |
| 322 | |
| 323 | /* I have seen IDE devices which will not respond to |
| 324 | * the bmdma simplex check reads if bus mastering is |
| 325 | * disabled. |
| 326 | */ |
| 327 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) |
| 328 | pci_set_master(dev); |
| 329 | |
| 330 | dev->current_state = 4; /* unknown power state */ |
| 331 | dev->error_state = pci_channel_io_normal; |
| 332 | dev->dma_mask = 0xffffffff; |
| 333 | |
| 334 | if (!strcmp(node->name, "pci")) { |
| 335 | /* a PCI-PCI bridge */ |
| 336 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
| 337 | dev->rom_base_reg = PCI_ROM_ADDRESS1; |
| 338 | } else if (!strcmp(type, "cardbus")) { |
| 339 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; |
| 340 | } else { |
| 341 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; |
| 342 | dev->rom_base_reg = PCI_ROM_ADDRESS; |
| 343 | |
| 344 | dev->irq = sd->op->archdata.irqs[0]; |
| 345 | if (dev->irq == 0xffffffff) |
| 346 | dev->irq = PCI_IRQ_NONE; |
| 347 | } |
| 348 | |
| 349 | pci_parse_of_addrs(sd->op, node, dev); |
| 350 | |
| 351 | if (ofpci_verbose) |
| 352 | printk(" adding to system ...\n"); |
| 353 | |
| 354 | pci_device_add(dev, bus); |
| 355 | |
| 356 | return dev; |
| 357 | } |
| 358 | |
| 359 | static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
| 360 | { |
| 361 | u32 idx, first, last; |
| 362 | |
| 363 | first = 8; |
| 364 | last = 0; |
| 365 | for (idx = 0; idx < 8; idx++) { |
| 366 | if ((map & (1 << idx)) != 0) { |
| 367 | if (first > idx) |
| 368 | first = idx; |
| 369 | if (last < idx) |
| 370 | last = idx; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | *first_p = first; |
| 375 | *last_p = last; |
| 376 | } |
| 377 | |
| 378 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
| 379 | * a proper 'ranges' property. |
| 380 | */ |
| 381 | static void apb_fake_ranges(struct pci_dev *dev, struct pci_bus *bus, |
| 382 | struct pci_pbm_info *pbm) |
| 383 | { |
| 384 | struct pci_bus_region region; |
| 385 | struct resource *res; |
| 386 | u32 first, last; |
| 387 | u8 map; |
| 388 | |
| 389 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); |
| 390 | apb_calc_first_last(map, &first, &last); |
| 391 | res = bus->resource[0]; |
| 392 | res->flags = IORESOURCE_IO; |
| 393 | region.start = (first << 21); |
| 394 | region.end = (last << 21) + ((1 << 21) - 1); |
| 395 | pcibios_bus_to_resource(dev, res, ®ion); |
| 396 | |
| 397 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); |
| 398 | apb_calc_first_last(map, &first, &last); |
| 399 | res = bus->resource[1]; |
| 400 | res->flags = IORESOURCE_MEM; |
| 401 | region.start = (first << 21); |
| 402 | region.end = (last << 21) + ((1 << 21) - 1); |
| 403 | pcibios_bus_to_resource(dev, res, ®ion); |
| 404 | } |
| 405 | |
| 406 | static void pci_of_scan_bus(struct pci_pbm_info *pbm, struct device_node *node, |
| 407 | struct pci_bus *bus); |
| 408 | |
| 409 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) |
| 410 | |
| 411 | static void of_scan_pci_bridge(struct pci_pbm_info *pbm, |
| 412 | struct device_node *node, struct pci_dev *dev) |
| 413 | { |
| 414 | struct pci_bus *bus; |
| 415 | const u32 *busrange, *ranges; |
| 416 | int len, i, simba; |
| 417 | struct pci_bus_region region; |
| 418 | struct resource *res; |
| 419 | unsigned int flags; |
| 420 | u64 size; |
| 421 | |
| 422 | if (ofpci_verbose) |
| 423 | printk("of_scan_pci_bridge(%s)\n", node->full_name); |
| 424 | |
| 425 | /* parse bus-range property */ |
| 426 | busrange = of_get_property(node, "bus-range", &len); |
| 427 | if (busrange == NULL || len != 8) { |
| 428 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", |
| 429 | node->full_name); |
| 430 | return; |
| 431 | } |
| 432 | ranges = of_get_property(node, "ranges", &len); |
| 433 | simba = 0; |
| 434 | if (ranges == NULL) { |
| 435 | const char *model = of_get_property(node, "model", NULL); |
| 436 | if (model && !strcmp(model, "SUNW,simba")) |
| 437 | simba = 1; |
| 438 | } |
| 439 | |
| 440 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); |
| 441 | if (!bus) { |
| 442 | printk(KERN_ERR "Failed to create pci bus for %s\n", |
| 443 | node->full_name); |
| 444 | return; |
| 445 | } |
| 446 | |
| 447 | bus->primary = dev->bus->number; |
| 448 | pci_bus_insert_busn_res(bus, busrange[0], busrange[1]); |
| 449 | bus->bridge_ctl = 0; |
| 450 | |
| 451 | /* parse ranges property, or cook one up by hand for Simba */ |
| 452 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
| 453 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
| 454 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { |
| 455 | res->flags = 0; |
| 456 | bus->resource[i] = res; |
| 457 | ++res; |
| 458 | } |
| 459 | if (simba) { |
| 460 | apb_fake_ranges(dev, bus, pbm); |
| 461 | goto after_ranges; |
| 462 | } else if (ranges == NULL) { |
| 463 | pci_read_bridge_bases(bus); |
| 464 | goto after_ranges; |
| 465 | } |
| 466 | i = 1; |
| 467 | for (; len >= 32; len -= 32, ranges += 8) { |
| 468 | flags = pci_parse_of_flags(ranges[0]); |
| 469 | size = GET_64BIT(ranges, 6); |
| 470 | if (flags == 0 || size == 0) |
| 471 | continue; |
| 472 | if (flags & IORESOURCE_IO) { |
| 473 | res = bus->resource[0]; |
| 474 | if (res->flags) { |
| 475 | printk(KERN_ERR "PCI: ignoring extra I/O range" |
| 476 | " for bridge %s\n", node->full_name); |
| 477 | continue; |
| 478 | } |
| 479 | } else { |
| 480 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { |
| 481 | printk(KERN_ERR "PCI: too many memory ranges" |
| 482 | " for bridge %s\n", node->full_name); |
| 483 | continue; |
| 484 | } |
| 485 | res = bus->resource[i]; |
| 486 | ++i; |
| 487 | } |
| 488 | |
| 489 | res->flags = flags; |
| 490 | region.start = GET_64BIT(ranges, 1); |
| 491 | region.end = region.start + size - 1; |
| 492 | pcibios_bus_to_resource(dev, res, ®ion); |
| 493 | } |
| 494 | after_ranges: |
| 495 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
| 496 | bus->number); |
| 497 | if (ofpci_verbose) |
| 498 | printk(" bus name: %s\n", bus->name); |
| 499 | |
| 500 | pci_of_scan_bus(pbm, node, bus); |
| 501 | } |
| 502 | |
| 503 | static void pci_of_scan_bus(struct pci_pbm_info *pbm, struct device_node *node, |
| 504 | struct pci_bus *bus) |
| 505 | { |
| 506 | struct device_node *child; |
| 507 | const u32 *reg; |
| 508 | int reglen, devfn, prev_devfn; |
| 509 | struct pci_dev *dev; |
| 510 | |
| 511 | if (ofpci_verbose) |
| 512 | printk("PCI: scan_bus[%s] bus no %d\n", |
| 513 | node->full_name, bus->number); |
| 514 | |
| 515 | child = NULL; |
| 516 | prev_devfn = -1; |
| 517 | while ((child = of_get_next_child(node, child)) != NULL) { |
| 518 | if (ofpci_verbose) |
| 519 | printk(" * %s\n", child->full_name); |
| 520 | reg = of_get_property(child, "reg", ®len); |
| 521 | if (reg == NULL || reglen < 20) |
| 522 | continue; |
| 523 | |
| 524 | devfn = (reg[0] >> 8) & 0xff; |
| 525 | |
| 526 | /* This is a workaround for some device trees |
| 527 | * which list PCI devices twice. On the V100 |
| 528 | * for example, device number 3 is listed twice. |
| 529 | * Once as "pm" and once again as "lomp". |
| 530 | */ |
| 531 | if (devfn == prev_devfn) |
| 532 | continue; |
| 533 | prev_devfn = devfn; |
| 534 | |
| 535 | /* create a new pci_dev for this device */ |
| 536 | dev = of_create_pci_dev(pbm, child, bus, devfn); |
| 537 | if (!dev) |
| 538 | continue; |
| 539 | if (ofpci_verbose) |
| 540 | printk("PCI: dev header type: %x\n", |
| 541 | dev->hdr_type); |
| 542 | |
| 543 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
| 544 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) |
| 545 | of_scan_pci_bridge(pbm, child, dev); |
| 546 | } |
| 547 | } |
| 548 | |
| 549 | static ssize_t |
| 550 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) |
| 551 | { |
| 552 | struct pci_dev *pdev; |
| 553 | struct device_node *dp; |
| 554 | |
| 555 | pdev = to_pci_dev(dev); |
| 556 | dp = pdev->dev.of_node; |
| 557 | |
| 558 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); |
| 559 | } |
| 560 | |
| 561 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); |
| 562 | |
| 563 | static void pci_bus_register_of_sysfs(struct pci_bus *bus) |
| 564 | { |
| 565 | struct pci_dev *dev; |
| 566 | struct pci_bus *child_bus; |
| 567 | int err; |
| 568 | |
| 569 | list_for_each_entry(dev, &bus->devices, bus_list) { |
| 570 | /* we don't really care if we can create this file or |
| 571 | * not, but we need to assign the result of the call |
| 572 | * or the world will fall under alien invasion and |
| 573 | * everybody will be frozen on a spaceship ready to be |
| 574 | * eaten on alpha centauri by some green and jelly |
| 575 | * humanoid. |
| 576 | */ |
| 577 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); |
| 578 | (void) err; |
| 579 | } |
| 580 | list_for_each_entry(child_bus, &bus->children, node) |
| 581 | pci_bus_register_of_sysfs(child_bus); |
| 582 | } |
| 583 | |
| 584 | struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, |
| 585 | struct device *parent) |
| 586 | { |
| 587 | LIST_HEAD(resources); |
| 588 | struct device_node *node = pbm->op->dev.of_node; |
| 589 | struct pci_bus *bus; |
| 590 | |
| 591 | printk("PCI: Scanning PBM %s\n", node->full_name); |
| 592 | |
| 593 | pci_add_resource_offset(&resources, &pbm->io_space, |
| 594 | pbm->io_space.start); |
| 595 | pci_add_resource_offset(&resources, &pbm->mem_space, |
| 596 | pbm->mem_space.start); |
| 597 | pbm->busn.start = pbm->pci_first_busno; |
| 598 | pbm->busn.end = pbm->pci_last_busno; |
| 599 | pbm->busn.flags = IORESOURCE_BUS; |
| 600 | pci_add_resource(&resources, &pbm->busn); |
| 601 | bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, |
| 602 | pbm, &resources); |
| 603 | if (!bus) { |
| 604 | printk(KERN_ERR "Failed to create bus for %s\n", |
| 605 | node->full_name); |
| 606 | pci_free_resource_list(&resources); |
| 607 | return NULL; |
| 608 | } |
| 609 | |
| 610 | pci_of_scan_bus(pbm, node, bus); |
| 611 | pci_bus_add_devices(bus); |
| 612 | pci_bus_register_of_sysfs(bus); |
| 613 | |
| 614 | return bus; |
| 615 | } |
| 616 | |
| 617 | void pcibios_fixup_bus(struct pci_bus *pbus) |
| 618 | { |
| 619 | } |
| 620 | |
| 621 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
| 622 | resource_size_t size, resource_size_t align) |
| 623 | { |
| 624 | return res->start; |
| 625 | } |
| 626 | |
| 627 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 628 | { |
| 629 | u16 cmd, oldcmd; |
| 630 | int i; |
| 631 | |
| 632 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 633 | oldcmd = cmd; |
| 634 | |
| 635 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 636 | struct resource *res = &dev->resource[i]; |
| 637 | |
| 638 | /* Only set up the requested stuff */ |
| 639 | if (!(mask & (1<<i))) |
| 640 | continue; |
| 641 | |
| 642 | if (res->flags & IORESOURCE_IO) |
| 643 | cmd |= PCI_COMMAND_IO; |
| 644 | if (res->flags & IORESOURCE_MEM) |
| 645 | cmd |= PCI_COMMAND_MEMORY; |
| 646 | } |
| 647 | |
| 648 | if (cmd != oldcmd) { |
| 649 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", |
| 650 | pci_name(dev), cmd); |
| 651 | /* Enable the appropriate bits in the PCI command register. */ |
| 652 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 653 | } |
| 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ |
| 658 | |
| 659 | /* If the user uses a host-bridge as the PCI device, he may use |
| 660 | * this to perform a raw mmap() of the I/O or MEM space behind |
| 661 | * that controller. |
| 662 | * |
| 663 | * This can be useful for execution of x86 PCI bios initialization code |
| 664 | * on a PCI card, like the xfree86 int10 stuff does. |
| 665 | */ |
| 666 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, |
| 667 | enum pci_mmap_state mmap_state) |
| 668 | { |
| 669 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
| 670 | unsigned long space_size, user_offset, user_size; |
| 671 | |
| 672 | if (mmap_state == pci_mmap_io) { |
| 673 | space_size = resource_size(&pbm->io_space); |
| 674 | } else { |
| 675 | space_size = resource_size(&pbm->mem_space); |
| 676 | } |
| 677 | |
| 678 | /* Make sure the request is in range. */ |
| 679 | user_offset = vma->vm_pgoff << PAGE_SHIFT; |
| 680 | user_size = vma->vm_end - vma->vm_start; |
| 681 | |
| 682 | if (user_offset >= space_size || |
| 683 | (user_offset + user_size) > space_size) |
| 684 | return -EINVAL; |
| 685 | |
| 686 | if (mmap_state == pci_mmap_io) { |
| 687 | vma->vm_pgoff = (pbm->io_space.start + |
| 688 | user_offset) >> PAGE_SHIFT; |
| 689 | } else { |
| 690 | vma->vm_pgoff = (pbm->mem_space.start + |
| 691 | user_offset) >> PAGE_SHIFT; |
| 692 | } |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | /* Adjust vm_pgoff of VMA such that it is the physical page offset |
| 698 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. |
| 699 | * |
| 700 | * Basically, the user finds the base address for his device which he wishes |
| 701 | * to mmap. They read the 32-bit value from the config space base register, |
| 702 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the |
| 703 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. |
| 704 | * |
| 705 | * Returns negative error code on failure, zero on success. |
| 706 | */ |
| 707 | static int __pci_mmap_make_offset(struct pci_dev *pdev, |
| 708 | struct vm_area_struct *vma, |
| 709 | enum pci_mmap_state mmap_state) |
| 710 | { |
| 711 | unsigned long user_paddr, user_size; |
| 712 | int i, err; |
| 713 | |
| 714 | /* First compute the physical address in vma->vm_pgoff, |
| 715 | * making sure the user offset is within range in the |
| 716 | * appropriate PCI space. |
| 717 | */ |
| 718 | err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); |
| 719 | if (err) |
| 720 | return err; |
| 721 | |
| 722 | /* If this is a mapping on a host bridge, any address |
| 723 | * is OK. |
| 724 | */ |
| 725 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) |
| 726 | return err; |
| 727 | |
| 728 | /* Otherwise make sure it's in the range for one of the |
| 729 | * device's resources. |
| 730 | */ |
| 731 | user_paddr = vma->vm_pgoff << PAGE_SHIFT; |
| 732 | user_size = vma->vm_end - vma->vm_start; |
| 733 | |
| 734 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 735 | struct resource *rp = &pdev->resource[i]; |
| 736 | resource_size_t aligned_end; |
| 737 | |
| 738 | /* Active? */ |
| 739 | if (!rp->flags) |
| 740 | continue; |
| 741 | |
| 742 | /* Same type? */ |
| 743 | if (i == PCI_ROM_RESOURCE) { |
| 744 | if (mmap_state != pci_mmap_mem) |
| 745 | continue; |
| 746 | } else { |
| 747 | if ((mmap_state == pci_mmap_io && |
| 748 | (rp->flags & IORESOURCE_IO) == 0) || |
| 749 | (mmap_state == pci_mmap_mem && |
| 750 | (rp->flags & IORESOURCE_MEM) == 0)) |
| 751 | continue; |
| 752 | } |
| 753 | |
| 754 | /* Align the resource end to the next page address. |
| 755 | * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), |
| 756 | * because actually we need the address of the next byte |
| 757 | * after rp->end. |
| 758 | */ |
| 759 | aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; |
| 760 | |
| 761 | if ((rp->start <= user_paddr) && |
| 762 | (user_paddr + user_size) <= aligned_end) |
| 763 | break; |
| 764 | } |
| 765 | |
| 766 | if (i > PCI_ROM_RESOURCE) |
| 767 | return -EINVAL; |
| 768 | |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device |
| 773 | * mapping. |
| 774 | */ |
| 775 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, |
| 776 | enum pci_mmap_state mmap_state) |
| 777 | { |
| 778 | vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; |
| 779 | } |
| 780 | |
| 781 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci |
| 782 | * device mapping. |
| 783 | */ |
| 784 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, |
| 785 | enum pci_mmap_state mmap_state) |
| 786 | { |
| 787 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
| 788 | } |
| 789 | |
| 790 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate |
| 791 | * for this architecture. The region in the process to map is described by vm_start |
| 792 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. |
| 793 | * The pci device structure is provided so that architectures may make mapping |
| 794 | * decisions on a per-device or per-bus basis. |
| 795 | * |
| 796 | * Returns a negative error code on failure, zero on success. |
| 797 | */ |
| 798 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 799 | enum pci_mmap_state mmap_state, |
| 800 | int write_combine) |
| 801 | { |
| 802 | int ret; |
| 803 | |
| 804 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); |
| 805 | if (ret < 0) |
| 806 | return ret; |
| 807 | |
| 808 | __pci_mmap_set_flags(dev, vma, mmap_state); |
| 809 | __pci_mmap_set_pgprot(dev, vma, mmap_state); |
| 810 | |
| 811 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
| 812 | ret = io_remap_pfn_range(vma, vma->vm_start, |
| 813 | vma->vm_pgoff, |
| 814 | vma->vm_end - vma->vm_start, |
| 815 | vma->vm_page_prot); |
| 816 | if (ret) |
| 817 | return ret; |
| 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |
| 822 | #ifdef CONFIG_NUMA |
| 823 | int pcibus_to_node(struct pci_bus *pbus) |
| 824 | { |
| 825 | struct pci_pbm_info *pbm = pbus->sysdata; |
| 826 | |
| 827 | return pbm->numa_node; |
| 828 | } |
| 829 | EXPORT_SYMBOL(pcibus_to_node); |
| 830 | #endif |
| 831 | |
| 832 | /* Return the domain number for this pci bus */ |
| 833 | |
| 834 | int pci_domain_nr(struct pci_bus *pbus) |
| 835 | { |
| 836 | struct pci_pbm_info *pbm = pbus->sysdata; |
| 837 | int ret; |
| 838 | |
| 839 | if (!pbm) { |
| 840 | ret = -ENXIO; |
| 841 | } else { |
| 842 | ret = pbm->index; |
| 843 | } |
| 844 | |
| 845 | return ret; |
| 846 | } |
| 847 | EXPORT_SYMBOL(pci_domain_nr); |
| 848 | |
| 849 | #ifdef CONFIG_PCI_MSI |
| 850 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
| 851 | { |
| 852 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
| 853 | unsigned int irq; |
| 854 | |
| 855 | if (!pbm->setup_msi_irq) |
| 856 | return -EINVAL; |
| 857 | |
| 858 | return pbm->setup_msi_irq(&irq, pdev, desc); |
| 859 | } |
| 860 | |
| 861 | void arch_teardown_msi_irq(unsigned int irq) |
| 862 | { |
| 863 | struct msi_desc *entry = irq_get_msi_desc(irq); |
| 864 | struct pci_dev *pdev = entry->dev; |
| 865 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
| 866 | |
| 867 | if (pbm->teardown_msi_irq) |
| 868 | pbm->teardown_msi_irq(irq, pdev); |
| 869 | } |
| 870 | #endif /* !(CONFIG_PCI_MSI) */ |
| 871 | |
| 872 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
| 873 | { |
| 874 | struct pci_dev *ali_isa_bridge; |
| 875 | u8 val; |
| 876 | |
| 877 | /* ALI sound chips generate 31-bits of DMA, a special register |
| 878 | * determines what bit 31 is emitted as. |
| 879 | */ |
| 880 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, |
| 881 | PCI_DEVICE_ID_AL_M1533, |
| 882 | NULL); |
| 883 | |
| 884 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); |
| 885 | if (set_bit) |
| 886 | val |= 0x01; |
| 887 | else |
| 888 | val &= ~0x01; |
| 889 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); |
| 890 | pci_dev_put(ali_isa_bridge); |
| 891 | } |
| 892 | |
| 893 | int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask) |
| 894 | { |
| 895 | u64 dma_addr_mask; |
| 896 | |
| 897 | if (pdev == NULL) { |
| 898 | dma_addr_mask = 0xffffffff; |
| 899 | } else { |
| 900 | struct iommu *iommu = pdev->dev.archdata.iommu; |
| 901 | |
| 902 | dma_addr_mask = iommu->dma_addr_mask; |
| 903 | |
| 904 | if (pdev->vendor == PCI_VENDOR_ID_AL && |
| 905 | pdev->device == PCI_DEVICE_ID_AL_M5451 && |
| 906 | device_mask == 0x7fffffff) { |
| 907 | ali_sound_dma_hack(pdev, |
| 908 | (dma_addr_mask & 0x80000000) != 0); |
| 909 | return 1; |
| 910 | } |
| 911 | } |
| 912 | |
| 913 | if (device_mask >= (1UL << 32UL)) |
| 914 | return 0; |
| 915 | |
| 916 | return (device_mask & dma_addr_mask) == dma_addr_mask; |
| 917 | } |
| 918 | |
| 919 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
| 920 | const struct resource *rp, resource_size_t *start, |
| 921 | resource_size_t *end) |
| 922 | { |
| 923 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
| 924 | unsigned long offset; |
| 925 | |
| 926 | if (rp->flags & IORESOURCE_IO) |
| 927 | offset = pbm->io_space.start; |
| 928 | else |
| 929 | offset = pbm->mem_space.start; |
| 930 | |
| 931 | *start = rp->start - offset; |
| 932 | *end = rp->end - offset; |
| 933 | } |
| 934 | |
| 935 | void pcibios_set_master(struct pci_dev *dev) |
| 936 | { |
| 937 | /* No special bus mastering setup handling */ |
| 938 | } |
| 939 | |
| 940 | static int __init pcibios_init(void) |
| 941 | { |
| 942 | pci_dfl_cache_line_size = 64 >> 2; |
| 943 | return 0; |
| 944 | } |
| 945 | subsys_initcall(pcibios_init); |
| 946 | |
| 947 | #ifdef CONFIG_SYSFS |
| 948 | static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus) |
| 949 | { |
| 950 | const struct pci_slot_names { |
| 951 | u32 slot_mask; |
| 952 | char names[0]; |
| 953 | } *prop; |
| 954 | const char *sp; |
| 955 | int len, i; |
| 956 | u32 mask; |
| 957 | |
| 958 | prop = of_get_property(node, "slot-names", &len); |
| 959 | if (!prop) |
| 960 | return; |
| 961 | |
| 962 | mask = prop->slot_mask; |
| 963 | sp = prop->names; |
| 964 | |
| 965 | if (ofpci_verbose) |
| 966 | printk("PCI: Making slots for [%s] mask[0x%02x]\n", |
| 967 | node->full_name, mask); |
| 968 | |
| 969 | i = 0; |
| 970 | while (mask) { |
| 971 | struct pci_slot *pci_slot; |
| 972 | u32 this_bit = 1 << i; |
| 973 | |
| 974 | if (!(mask & this_bit)) { |
| 975 | i++; |
| 976 | continue; |
| 977 | } |
| 978 | |
| 979 | if (ofpci_verbose) |
| 980 | printk("PCI: Making slot [%s]\n", sp); |
| 981 | |
| 982 | pci_slot = pci_create_slot(bus, i, sp, NULL); |
| 983 | if (IS_ERR(pci_slot)) |
| 984 | printk(KERN_ERR "PCI: pci_create_slot returned %ld\n", |
| 985 | PTR_ERR(pci_slot)); |
| 986 | |
| 987 | sp += strlen(sp) + 1; |
| 988 | mask &= ~this_bit; |
| 989 | i++; |
| 990 | } |
| 991 | } |
| 992 | |
| 993 | static int __init of_pci_slot_init(void) |
| 994 | { |
| 995 | struct pci_bus *pbus = NULL; |
| 996 | |
| 997 | while ((pbus = pci_find_next_bus(pbus)) != NULL) { |
| 998 | struct device_node *node; |
| 999 | |
| 1000 | if (pbus->self) { |
| 1001 | /* PCI->PCI bridge */ |
| 1002 | node = pbus->self->dev.of_node; |
| 1003 | } else { |
| 1004 | struct pci_pbm_info *pbm = pbus->sysdata; |
| 1005 | |
| 1006 | /* Host PCI controller */ |
| 1007 | node = pbm->op->dev.of_node; |
| 1008 | } |
| 1009 | |
| 1010 | pci_bus_slot_names(node, pbus); |
| 1011 | } |
| 1012 | |
| 1013 | return 0; |
| 1014 | } |
| 1015 | |
| 1016 | module_init(of_pci_slot_init); |
| 1017 | #endif |