| 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
| 2 | * |
| 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
| 4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
| 5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) |
| 6 | */ |
| 7 | |
| 8 | #include <linux/module.h> |
| 9 | #include <linux/sched.h> |
| 10 | #include <linux/ptrace.h> |
| 11 | #include <linux/errno.h> |
| 12 | #include <linux/kernel_stat.h> |
| 13 | #include <linux/signal.h> |
| 14 | #include <linux/mm.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/random.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/proc_fs.h> |
| 21 | #include <linux/seq_file.h> |
| 22 | #include <linux/bootmem.h> |
| 23 | #include <linux/irq.h> |
| 24 | |
| 25 | #include <asm/ptrace.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/atomic.h> |
| 28 | #include <asm/system.h> |
| 29 | #include <asm/irq.h> |
| 30 | #include <asm/io.h> |
| 31 | #include <asm/sbus.h> |
| 32 | #include <asm/iommu.h> |
| 33 | #include <asm/upa.h> |
| 34 | #include <asm/oplib.h> |
| 35 | #include <asm/prom.h> |
| 36 | #include <asm/timer.h> |
| 37 | #include <asm/smp.h> |
| 38 | #include <asm/starfire.h> |
| 39 | #include <asm/uaccess.h> |
| 40 | #include <asm/cache.h> |
| 41 | #include <asm/cpudata.h> |
| 42 | #include <asm/auxio.h> |
| 43 | #include <asm/head.h> |
| 44 | #include <asm/hypervisor.h> |
| 45 | #include <asm/cacheflush.h> |
| 46 | |
| 47 | #include "entry.h" |
| 48 | |
| 49 | #define NUM_IVECS (IMAP_INR + 1) |
| 50 | |
| 51 | struct ino_bucket *ivector_table; |
| 52 | unsigned long ivector_table_pa; |
| 53 | |
| 54 | /* On several sun4u processors, it is illegal to mix bypass and |
| 55 | * non-bypass accesses. Therefore we access all INO buckets |
| 56 | * using bypass accesses only. |
| 57 | */ |
| 58 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) |
| 59 | { |
| 60 | unsigned long ret; |
| 61 | |
| 62 | __asm__ __volatile__("ldxa [%1] %2, %0" |
| 63 | : "=&r" (ret) |
| 64 | : "r" (bucket_pa + |
| 65 | offsetof(struct ino_bucket, |
| 66 | __irq_chain_pa)), |
| 67 | "i" (ASI_PHYS_USE_EC)); |
| 68 | |
| 69 | return ret; |
| 70 | } |
| 71 | |
| 72 | static void bucket_clear_chain_pa(unsigned long bucket_pa) |
| 73 | { |
| 74 | __asm__ __volatile__("stxa %%g0, [%0] %1" |
| 75 | : /* no outputs */ |
| 76 | : "r" (bucket_pa + |
| 77 | offsetof(struct ino_bucket, |
| 78 | __irq_chain_pa)), |
| 79 | "i" (ASI_PHYS_USE_EC)); |
| 80 | } |
| 81 | |
| 82 | static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) |
| 83 | { |
| 84 | unsigned int ret; |
| 85 | |
| 86 | __asm__ __volatile__("lduwa [%1] %2, %0" |
| 87 | : "=&r" (ret) |
| 88 | : "r" (bucket_pa + |
| 89 | offsetof(struct ino_bucket, |
| 90 | __virt_irq)), |
| 91 | "i" (ASI_PHYS_USE_EC)); |
| 92 | |
| 93 | return ret; |
| 94 | } |
| 95 | |
| 96 | static void bucket_set_virt_irq(unsigned long bucket_pa, |
| 97 | unsigned int virt_irq) |
| 98 | { |
| 99 | __asm__ __volatile__("stwa %0, [%1] %2" |
| 100 | : /* no outputs */ |
| 101 | : "r" (virt_irq), |
| 102 | "r" (bucket_pa + |
| 103 | offsetof(struct ino_bucket, |
| 104 | __virt_irq)), |
| 105 | "i" (ASI_PHYS_USE_EC)); |
| 106 | } |
| 107 | |
| 108 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
| 109 | |
| 110 | static struct { |
| 111 | unsigned int dev_handle; |
| 112 | unsigned int dev_ino; |
| 113 | unsigned int in_use; |
| 114 | } virt_irq_table[NR_IRQS]; |
| 115 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
| 116 | |
| 117 | unsigned char virt_irq_alloc(unsigned int dev_handle, |
| 118 | unsigned int dev_ino) |
| 119 | { |
| 120 | unsigned long flags; |
| 121 | unsigned char ent; |
| 122 | |
| 123 | BUILD_BUG_ON(NR_IRQS >= 256); |
| 124 | |
| 125 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
| 126 | |
| 127 | for (ent = 1; ent < NR_IRQS; ent++) { |
| 128 | if (!virt_irq_table[ent].in_use) |
| 129 | break; |
| 130 | } |
| 131 | if (ent >= NR_IRQS) { |
| 132 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); |
| 133 | ent = 0; |
| 134 | } else { |
| 135 | virt_irq_table[ent].dev_handle = dev_handle; |
| 136 | virt_irq_table[ent].dev_ino = dev_ino; |
| 137 | virt_irq_table[ent].in_use = 1; |
| 138 | } |
| 139 | |
| 140 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
| 141 | |
| 142 | return ent; |
| 143 | } |
| 144 | |
| 145 | #ifdef CONFIG_PCI_MSI |
| 146 | void virt_irq_free(unsigned int virt_irq) |
| 147 | { |
| 148 | unsigned long flags; |
| 149 | |
| 150 | if (virt_irq >= NR_IRQS) |
| 151 | return; |
| 152 | |
| 153 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
| 154 | |
| 155 | virt_irq_table[virt_irq].in_use = 0; |
| 156 | |
| 157 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
| 158 | } |
| 159 | #endif |
| 160 | |
| 161 | /* |
| 162 | * /proc/interrupts printing: |
| 163 | */ |
| 164 | |
| 165 | int show_interrupts(struct seq_file *p, void *v) |
| 166 | { |
| 167 | int i = *(loff_t *) v, j; |
| 168 | struct irqaction * action; |
| 169 | unsigned long flags; |
| 170 | |
| 171 | if (i == 0) { |
| 172 | seq_printf(p, " "); |
| 173 | for_each_online_cpu(j) |
| 174 | seq_printf(p, "CPU%d ",j); |
| 175 | seq_putc(p, '\n'); |
| 176 | } |
| 177 | |
| 178 | if (i < NR_IRQS) { |
| 179 | spin_lock_irqsave(&irq_desc[i].lock, flags); |
| 180 | action = irq_desc[i].action; |
| 181 | if (!action) |
| 182 | goto skip; |
| 183 | seq_printf(p, "%3d: ",i); |
| 184 | #ifndef CONFIG_SMP |
| 185 | seq_printf(p, "%10u ", kstat_irqs(i)); |
| 186 | #else |
| 187 | for_each_online_cpu(j) |
| 188 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); |
| 189 | #endif |
| 190 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
| 191 | seq_printf(p, " %s", action->name); |
| 192 | |
| 193 | for (action=action->next; action; action = action->next) |
| 194 | seq_printf(p, ", %s", action->name); |
| 195 | |
| 196 | seq_putc(p, '\n'); |
| 197 | skip: |
| 198 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
| 199 | } |
| 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
| 204 | { |
| 205 | unsigned int tid; |
| 206 | |
| 207 | if (this_is_starfire) { |
| 208 | tid = starfire_translate(imap, cpuid); |
| 209 | tid <<= IMAP_TID_SHIFT; |
| 210 | tid &= IMAP_TID_UPA; |
| 211 | } else { |
| 212 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 213 | unsigned long ver; |
| 214 | |
| 215 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); |
| 216 | if ((ver >> 32UL) == __JALAPENO_ID || |
| 217 | (ver >> 32UL) == __SERRANO_ID) { |
| 218 | tid = cpuid << IMAP_TID_SHIFT; |
| 219 | tid &= IMAP_TID_JBUS; |
| 220 | } else { |
| 221 | unsigned int a = cpuid & 0x1f; |
| 222 | unsigned int n = (cpuid >> 5) & 0x1f; |
| 223 | |
| 224 | tid = ((a << IMAP_AID_SHIFT) | |
| 225 | (n << IMAP_NID_SHIFT)); |
| 226 | tid &= (IMAP_AID_SAFARI | |
| 227 | IMAP_NID_SAFARI);; |
| 228 | } |
| 229 | } else { |
| 230 | tid = cpuid << IMAP_TID_SHIFT; |
| 231 | tid &= IMAP_TID_UPA; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | return tid; |
| 236 | } |
| 237 | |
| 238 | struct irq_handler_data { |
| 239 | unsigned long iclr; |
| 240 | unsigned long imap; |
| 241 | |
| 242 | void (*pre_handler)(unsigned int, void *, void *); |
| 243 | void *arg1; |
| 244 | void *arg2; |
| 245 | }; |
| 246 | |
| 247 | #ifdef CONFIG_SMP |
| 248 | static int irq_choose_cpu(unsigned int virt_irq) |
| 249 | { |
| 250 | cpumask_t mask = irq_desc[virt_irq].affinity; |
| 251 | int cpuid; |
| 252 | |
| 253 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
| 254 | static int irq_rover; |
| 255 | static DEFINE_SPINLOCK(irq_rover_lock); |
| 256 | unsigned long flags; |
| 257 | |
| 258 | /* Round-robin distribution... */ |
| 259 | do_round_robin: |
| 260 | spin_lock_irqsave(&irq_rover_lock, flags); |
| 261 | |
| 262 | while (!cpu_online(irq_rover)) { |
| 263 | if (++irq_rover >= NR_CPUS) |
| 264 | irq_rover = 0; |
| 265 | } |
| 266 | cpuid = irq_rover; |
| 267 | do { |
| 268 | if (++irq_rover >= NR_CPUS) |
| 269 | irq_rover = 0; |
| 270 | } while (!cpu_online(irq_rover)); |
| 271 | |
| 272 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
| 273 | } else { |
| 274 | cpumask_t tmp; |
| 275 | |
| 276 | cpus_and(tmp, cpu_online_map, mask); |
| 277 | |
| 278 | if (cpus_empty(tmp)) |
| 279 | goto do_round_robin; |
| 280 | |
| 281 | cpuid = first_cpu(tmp); |
| 282 | } |
| 283 | |
| 284 | return cpuid; |
| 285 | } |
| 286 | #else |
| 287 | static int irq_choose_cpu(unsigned int virt_irq) |
| 288 | { |
| 289 | return real_hard_smp_processor_id(); |
| 290 | } |
| 291 | #endif |
| 292 | |
| 293 | static void sun4u_irq_enable(unsigned int virt_irq) |
| 294 | { |
| 295 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
| 296 | |
| 297 | if (likely(data)) { |
| 298 | unsigned long cpuid, imap, val; |
| 299 | unsigned int tid; |
| 300 | |
| 301 | cpuid = irq_choose_cpu(virt_irq); |
| 302 | imap = data->imap; |
| 303 | |
| 304 | tid = sun4u_compute_tid(imap, cpuid); |
| 305 | |
| 306 | val = upa_readq(imap); |
| 307 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | |
| 308 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); |
| 309 | val |= tid | IMAP_VALID; |
| 310 | upa_writeq(val, imap); |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask) |
| 315 | { |
| 316 | sun4u_irq_enable(virt_irq); |
| 317 | } |
| 318 | |
| 319 | static void sun4u_irq_disable(unsigned int virt_irq) |
| 320 | { |
| 321 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
| 322 | |
| 323 | if (likely(data)) { |
| 324 | unsigned long imap = data->imap; |
| 325 | unsigned long tmp = upa_readq(imap); |
| 326 | |
| 327 | tmp &= ~IMAP_VALID; |
| 328 | upa_writeq(tmp, imap); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | static void sun4u_irq_eoi(unsigned int virt_irq) |
| 333 | { |
| 334 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
| 335 | struct irq_desc *desc = irq_desc + virt_irq; |
| 336 | |
| 337 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 338 | return; |
| 339 | |
| 340 | if (likely(data)) |
| 341 | upa_writeq(ICLR_IDLE, data->iclr); |
| 342 | } |
| 343 | |
| 344 | static void sun4v_irq_enable(unsigned int virt_irq) |
| 345 | { |
| 346 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 347 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
| 348 | int err; |
| 349 | |
| 350 | err = sun4v_intr_settarget(ino, cpuid); |
| 351 | if (err != HV_EOK) |
| 352 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
| 353 | "err(%d)\n", ino, cpuid, err); |
| 354 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
| 355 | if (err != HV_EOK) |
| 356 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
| 357 | "err(%d)\n", ino, err); |
| 358 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
| 359 | if (err != HV_EOK) |
| 360 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", |
| 361 | ino, err); |
| 362 | } |
| 363 | |
| 364 | static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask) |
| 365 | { |
| 366 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 367 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
| 368 | int err; |
| 369 | |
| 370 | err = sun4v_intr_settarget(ino, cpuid); |
| 371 | if (err != HV_EOK) |
| 372 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
| 373 | "err(%d)\n", ino, cpuid, err); |
| 374 | } |
| 375 | |
| 376 | static void sun4v_irq_disable(unsigned int virt_irq) |
| 377 | { |
| 378 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 379 | int err; |
| 380 | |
| 381 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
| 382 | if (err != HV_EOK) |
| 383 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " |
| 384 | "err(%d)\n", ino, err); |
| 385 | } |
| 386 | |
| 387 | static void sun4v_irq_eoi(unsigned int virt_irq) |
| 388 | { |
| 389 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 390 | struct irq_desc *desc = irq_desc + virt_irq; |
| 391 | int err; |
| 392 | |
| 393 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 394 | return; |
| 395 | |
| 396 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
| 397 | if (err != HV_EOK) |
| 398 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
| 399 | "err(%d)\n", ino, err); |
| 400 | } |
| 401 | |
| 402 | static void sun4v_virq_enable(unsigned int virt_irq) |
| 403 | { |
| 404 | unsigned long cpuid, dev_handle, dev_ino; |
| 405 | int err; |
| 406 | |
| 407 | cpuid = irq_choose_cpu(virt_irq); |
| 408 | |
| 409 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
| 410 | dev_ino = virt_irq_table[virt_irq].dev_ino; |
| 411 | |
| 412 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
| 413 | if (err != HV_EOK) |
| 414 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
| 415 | "err(%d)\n", |
| 416 | dev_handle, dev_ino, cpuid, err); |
| 417 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
| 418 | HV_INTR_STATE_IDLE); |
| 419 | if (err != HV_EOK) |
| 420 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
| 421 | "HV_INTR_STATE_IDLE): err(%d)\n", |
| 422 | dev_handle, dev_ino, err); |
| 423 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, |
| 424 | HV_INTR_ENABLED); |
| 425 | if (err != HV_EOK) |
| 426 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
| 427 | "HV_INTR_ENABLED): err(%d)\n", |
| 428 | dev_handle, dev_ino, err); |
| 429 | } |
| 430 | |
| 431 | static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask) |
| 432 | { |
| 433 | unsigned long cpuid, dev_handle, dev_ino; |
| 434 | int err; |
| 435 | |
| 436 | cpuid = irq_choose_cpu(virt_irq); |
| 437 | |
| 438 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
| 439 | dev_ino = virt_irq_table[virt_irq].dev_ino; |
| 440 | |
| 441 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
| 442 | if (err != HV_EOK) |
| 443 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
| 444 | "err(%d)\n", |
| 445 | dev_handle, dev_ino, cpuid, err); |
| 446 | } |
| 447 | |
| 448 | static void sun4v_virq_disable(unsigned int virt_irq) |
| 449 | { |
| 450 | unsigned long dev_handle, dev_ino; |
| 451 | int err; |
| 452 | |
| 453 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
| 454 | dev_ino = virt_irq_table[virt_irq].dev_ino; |
| 455 | |
| 456 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, |
| 457 | HV_INTR_DISABLED); |
| 458 | if (err != HV_EOK) |
| 459 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
| 460 | "HV_INTR_DISABLED): err(%d)\n", |
| 461 | dev_handle, dev_ino, err); |
| 462 | } |
| 463 | |
| 464 | static void sun4v_virq_eoi(unsigned int virt_irq) |
| 465 | { |
| 466 | struct irq_desc *desc = irq_desc + virt_irq; |
| 467 | unsigned long dev_handle, dev_ino; |
| 468 | int err; |
| 469 | |
| 470 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 471 | return; |
| 472 | |
| 473 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
| 474 | dev_ino = virt_irq_table[virt_irq].dev_ino; |
| 475 | |
| 476 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
| 477 | HV_INTR_STATE_IDLE); |
| 478 | if (err != HV_EOK) |
| 479 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
| 480 | "HV_INTR_STATE_IDLE): err(%d)\n", |
| 481 | dev_handle, dev_ino, err); |
| 482 | } |
| 483 | |
| 484 | static struct irq_chip sun4u_irq = { |
| 485 | .typename = "sun4u", |
| 486 | .enable = sun4u_irq_enable, |
| 487 | .disable = sun4u_irq_disable, |
| 488 | .eoi = sun4u_irq_eoi, |
| 489 | .set_affinity = sun4u_set_affinity, |
| 490 | }; |
| 491 | |
| 492 | static struct irq_chip sun4v_irq = { |
| 493 | .typename = "sun4v", |
| 494 | .enable = sun4v_irq_enable, |
| 495 | .disable = sun4v_irq_disable, |
| 496 | .eoi = sun4v_irq_eoi, |
| 497 | .set_affinity = sun4v_set_affinity, |
| 498 | }; |
| 499 | |
| 500 | static struct irq_chip sun4v_virq = { |
| 501 | .typename = "vsun4v", |
| 502 | .enable = sun4v_virq_enable, |
| 503 | .disable = sun4v_virq_disable, |
| 504 | .eoi = sun4v_virq_eoi, |
| 505 | .set_affinity = sun4v_virt_set_affinity, |
| 506 | }; |
| 507 | |
| 508 | static void pre_flow_handler(unsigned int virt_irq, |
| 509 | struct irq_desc *desc) |
| 510 | { |
| 511 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
| 512 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 513 | |
| 514 | data->pre_handler(ino, data->arg1, data->arg2); |
| 515 | |
| 516 | handle_fasteoi_irq(virt_irq, desc); |
| 517 | } |
| 518 | |
| 519 | void irq_install_pre_handler(int virt_irq, |
| 520 | void (*func)(unsigned int, void *, void *), |
| 521 | void *arg1, void *arg2) |
| 522 | { |
| 523 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
| 524 | struct irq_desc *desc = irq_desc + virt_irq; |
| 525 | |
| 526 | data->pre_handler = func; |
| 527 | data->arg1 = arg1; |
| 528 | data->arg2 = arg2; |
| 529 | |
| 530 | desc->handle_irq = pre_flow_handler; |
| 531 | } |
| 532 | |
| 533 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
| 534 | { |
| 535 | struct ino_bucket *bucket; |
| 536 | struct irq_handler_data *data; |
| 537 | unsigned int virt_irq; |
| 538 | int ino; |
| 539 | |
| 540 | BUG_ON(tlb_type == hypervisor); |
| 541 | |
| 542 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
| 543 | bucket = &ivector_table[ino]; |
| 544 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
| 545 | if (!virt_irq) { |
| 546 | virt_irq = virt_irq_alloc(0, ino); |
| 547 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
| 548 | set_irq_chip_and_handler_name(virt_irq, |
| 549 | &sun4u_irq, |
| 550 | handle_fasteoi_irq, |
| 551 | "IVEC"); |
| 552 | } |
| 553 | |
| 554 | data = get_irq_chip_data(virt_irq); |
| 555 | if (unlikely(data)) |
| 556 | goto out; |
| 557 | |
| 558 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
| 559 | if (unlikely(!data)) { |
| 560 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
| 561 | prom_halt(); |
| 562 | } |
| 563 | set_irq_chip_data(virt_irq, data); |
| 564 | |
| 565 | data->imap = imap; |
| 566 | data->iclr = iclr; |
| 567 | |
| 568 | out: |
| 569 | return virt_irq; |
| 570 | } |
| 571 | |
| 572 | static unsigned int sun4v_build_common(unsigned long sysino, |
| 573 | struct irq_chip *chip) |
| 574 | { |
| 575 | struct ino_bucket *bucket; |
| 576 | struct irq_handler_data *data; |
| 577 | unsigned int virt_irq; |
| 578 | |
| 579 | BUG_ON(tlb_type != hypervisor); |
| 580 | |
| 581 | bucket = &ivector_table[sysino]; |
| 582 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
| 583 | if (!virt_irq) { |
| 584 | virt_irq = virt_irq_alloc(0, sysino); |
| 585 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
| 586 | set_irq_chip_and_handler_name(virt_irq, chip, |
| 587 | handle_fasteoi_irq, |
| 588 | "IVEC"); |
| 589 | } |
| 590 | |
| 591 | data = get_irq_chip_data(virt_irq); |
| 592 | if (unlikely(data)) |
| 593 | goto out; |
| 594 | |
| 595 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
| 596 | if (unlikely(!data)) { |
| 597 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
| 598 | prom_halt(); |
| 599 | } |
| 600 | set_irq_chip_data(virt_irq, data); |
| 601 | |
| 602 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
| 603 | * is done by hypervisor calls on sun4v platforms, not by direct |
| 604 | * register accesses. |
| 605 | */ |
| 606 | data->imap = ~0UL; |
| 607 | data->iclr = ~0UL; |
| 608 | |
| 609 | out: |
| 610 | return virt_irq; |
| 611 | } |
| 612 | |
| 613 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
| 614 | { |
| 615 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); |
| 616 | |
| 617 | return sun4v_build_common(sysino, &sun4v_irq); |
| 618 | } |
| 619 | |
| 620 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) |
| 621 | { |
| 622 | struct irq_handler_data *data; |
| 623 | struct ino_bucket *bucket; |
| 624 | unsigned long hv_err, cookie; |
| 625 | unsigned int virt_irq; |
| 626 | |
| 627 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); |
| 628 | if (unlikely(!bucket)) |
| 629 | return 0; |
| 630 | __flush_dcache_range((unsigned long) bucket, |
| 631 | ((unsigned long) bucket + |
| 632 | sizeof(struct ino_bucket))); |
| 633 | |
| 634 | virt_irq = virt_irq_alloc(devhandle, devino); |
| 635 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
| 636 | |
| 637 | set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, |
| 638 | handle_fasteoi_irq, |
| 639 | "IVEC"); |
| 640 | |
| 641 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
| 642 | if (unlikely(!data)) |
| 643 | return 0; |
| 644 | |
| 645 | set_irq_chip_data(virt_irq, data); |
| 646 | |
| 647 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
| 648 | * is done by hypervisor calls on sun4v platforms, not by direct |
| 649 | * register accesses. |
| 650 | */ |
| 651 | data->imap = ~0UL; |
| 652 | data->iclr = ~0UL; |
| 653 | |
| 654 | cookie = ~__pa(bucket); |
| 655 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); |
| 656 | if (hv_err) { |
| 657 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " |
| 658 | "err=%lu\n", devhandle, devino, hv_err); |
| 659 | prom_halt(); |
| 660 | } |
| 661 | |
| 662 | return virt_irq; |
| 663 | } |
| 664 | |
| 665 | void ack_bad_irq(unsigned int virt_irq) |
| 666 | { |
| 667 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
| 668 | |
| 669 | if (!ino) |
| 670 | ino = 0xdeadbeef; |
| 671 | |
| 672 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
| 673 | ino, virt_irq); |
| 674 | } |
| 675 | |
| 676 | void handler_irq(int irq, struct pt_regs *regs) |
| 677 | { |
| 678 | unsigned long pstate, bucket_pa; |
| 679 | struct pt_regs *old_regs; |
| 680 | |
| 681 | clear_softint(1 << irq); |
| 682 | |
| 683 | old_regs = set_irq_regs(regs); |
| 684 | irq_enter(); |
| 685 | |
| 686 | /* Grab an atomic snapshot of the pending IVECs. */ |
| 687 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" |
| 688 | "wrpr %0, %3, %%pstate\n\t" |
| 689 | "ldx [%2], %1\n\t" |
| 690 | "stx %%g0, [%2]\n\t" |
| 691 | "wrpr %0, 0x0, %%pstate\n\t" |
| 692 | : "=&r" (pstate), "=&r" (bucket_pa) |
| 693 | : "r" (irq_work_pa(smp_processor_id())), |
| 694 | "i" (PSTATE_IE) |
| 695 | : "memory"); |
| 696 | |
| 697 | while (bucket_pa) { |
| 698 | struct irq_desc *desc; |
| 699 | unsigned long next_pa; |
| 700 | unsigned int virt_irq; |
| 701 | |
| 702 | next_pa = bucket_get_chain_pa(bucket_pa); |
| 703 | virt_irq = bucket_get_virt_irq(bucket_pa); |
| 704 | bucket_clear_chain_pa(bucket_pa); |
| 705 | |
| 706 | desc = irq_desc + virt_irq; |
| 707 | |
| 708 | desc->handle_irq(virt_irq, desc); |
| 709 | |
| 710 | bucket_pa = next_pa; |
| 711 | } |
| 712 | |
| 713 | irq_exit(); |
| 714 | set_irq_regs(old_regs); |
| 715 | } |
| 716 | |
| 717 | #ifdef CONFIG_HOTPLUG_CPU |
| 718 | void fixup_irqs(void) |
| 719 | { |
| 720 | unsigned int irq; |
| 721 | |
| 722 | for (irq = 0; irq < NR_IRQS; irq++) { |
| 723 | unsigned long flags; |
| 724 | |
| 725 | spin_lock_irqsave(&irq_desc[irq].lock, flags); |
| 726 | if (irq_desc[irq].action && |
| 727 | !(irq_desc[irq].status & IRQ_PER_CPU)) { |
| 728 | if (irq_desc[irq].chip->set_affinity) |
| 729 | irq_desc[irq].chip->set_affinity(irq, |
| 730 | irq_desc[irq].affinity); |
| 731 | } |
| 732 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); |
| 733 | } |
| 734 | } |
| 735 | #endif |
| 736 | |
| 737 | struct sun5_timer { |
| 738 | u64 count0; |
| 739 | u64 limit0; |
| 740 | u64 count1; |
| 741 | u64 limit1; |
| 742 | }; |
| 743 | |
| 744 | static struct sun5_timer *prom_timers; |
| 745 | static u64 prom_limit0, prom_limit1; |
| 746 | |
| 747 | static void map_prom_timers(void) |
| 748 | { |
| 749 | struct device_node *dp; |
| 750 | const unsigned int *addr; |
| 751 | |
| 752 | /* PROM timer node hangs out in the top level of device siblings... */ |
| 753 | dp = of_find_node_by_path("/"); |
| 754 | dp = dp->child; |
| 755 | while (dp) { |
| 756 | if (!strcmp(dp->name, "counter-timer")) |
| 757 | break; |
| 758 | dp = dp->sibling; |
| 759 | } |
| 760 | |
| 761 | /* Assume if node is not present, PROM uses different tick mechanism |
| 762 | * which we should not care about. |
| 763 | */ |
| 764 | if (!dp) { |
| 765 | prom_timers = (struct sun5_timer *) 0; |
| 766 | return; |
| 767 | } |
| 768 | |
| 769 | /* If PROM is really using this, it must be mapped by him. */ |
| 770 | addr = of_get_property(dp, "address", NULL); |
| 771 | if (!addr) { |
| 772 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
| 773 | prom_timers = (struct sun5_timer *) 0; |
| 774 | return; |
| 775 | } |
| 776 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); |
| 777 | } |
| 778 | |
| 779 | static void kill_prom_timer(void) |
| 780 | { |
| 781 | if (!prom_timers) |
| 782 | return; |
| 783 | |
| 784 | /* Save them away for later. */ |
| 785 | prom_limit0 = prom_timers->limit0; |
| 786 | prom_limit1 = prom_timers->limit1; |
| 787 | |
| 788 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. |
| 789 | * We turn both off here just to be paranoid. |
| 790 | */ |
| 791 | prom_timers->limit0 = 0; |
| 792 | prom_timers->limit1 = 0; |
| 793 | |
| 794 | /* Wheee, eat the interrupt packet too... */ |
| 795 | __asm__ __volatile__( |
| 796 | " mov 0x40, %%g2\n" |
| 797 | " ldxa [%%g0] %0, %%g1\n" |
| 798 | " ldxa [%%g2] %1, %%g1\n" |
| 799 | " stxa %%g0, [%%g0] %0\n" |
| 800 | " membar #Sync\n" |
| 801 | : /* no outputs */ |
| 802 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) |
| 803 | : "g1", "g2"); |
| 804 | } |
| 805 | |
| 806 | void init_irqwork_curcpu(void) |
| 807 | { |
| 808 | int cpu = hard_smp_processor_id(); |
| 809 | |
| 810 | trap_block[cpu].irq_worklist_pa = 0UL; |
| 811 | } |
| 812 | |
| 813 | /* Please be very careful with register_one_mondo() and |
| 814 | * sun4v_register_mondo_queues(). |
| 815 | * |
| 816 | * On SMP this gets invoked from the CPU trampoline before |
| 817 | * the cpu has fully taken over the trap table from OBP, |
| 818 | * and it's kernel stack + %g6 thread register state is |
| 819 | * not fully cooked yet. |
| 820 | * |
| 821 | * Therefore you cannot make any OBP calls, not even prom_printf, |
| 822 | * from these two routines. |
| 823 | */ |
| 824 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) |
| 825 | { |
| 826 | unsigned long num_entries = (qmask + 1) / 64; |
| 827 | unsigned long status; |
| 828 | |
| 829 | status = sun4v_cpu_qconf(type, paddr, num_entries); |
| 830 | if (status != HV_EOK) { |
| 831 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " |
| 832 | "err %lu\n", type, paddr, num_entries, status); |
| 833 | prom_halt(); |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
| 838 | { |
| 839 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
| 840 | |
| 841 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
| 842 | tb->cpu_mondo_qmask); |
| 843 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, |
| 844 | tb->dev_mondo_qmask); |
| 845 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, |
| 846 | tb->resum_qmask); |
| 847 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, |
| 848 | tb->nonresum_qmask); |
| 849 | } |
| 850 | |
| 851 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
| 852 | { |
| 853 | unsigned long size = PAGE_ALIGN(qmask + 1); |
| 854 | void *p = __alloc_bootmem(size, size, 0); |
| 855 | if (!p) { |
| 856 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
| 857 | prom_halt(); |
| 858 | } |
| 859 | |
| 860 | *pa_ptr = __pa(p); |
| 861 | } |
| 862 | |
| 863 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
| 864 | { |
| 865 | unsigned long size = PAGE_ALIGN(qmask + 1); |
| 866 | void *p = __alloc_bootmem(size, size, 0); |
| 867 | |
| 868 | if (!p) { |
| 869 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
| 870 | prom_halt(); |
| 871 | } |
| 872 | |
| 873 | *pa_ptr = __pa(p); |
| 874 | } |
| 875 | |
| 876 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
| 877 | { |
| 878 | #ifdef CONFIG_SMP |
| 879 | void *page; |
| 880 | |
| 881 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); |
| 882 | |
| 883 | page = alloc_bootmem_pages(PAGE_SIZE); |
| 884 | if (!page) { |
| 885 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); |
| 886 | prom_halt(); |
| 887 | } |
| 888 | |
| 889 | tb->cpu_mondo_block_pa = __pa(page); |
| 890 | tb->cpu_list_pa = __pa(page + 64); |
| 891 | #endif |
| 892 | } |
| 893 | |
| 894 | /* Allocate mondo and error queues for all possible cpus. */ |
| 895 | static void __init sun4v_init_mondo_queues(void) |
| 896 | { |
| 897 | int cpu; |
| 898 | |
| 899 | for_each_possible_cpu(cpu) { |
| 900 | struct trap_per_cpu *tb = &trap_block[cpu]; |
| 901 | |
| 902 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
| 903 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); |
| 904 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); |
| 905 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); |
| 906 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); |
| 907 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, |
| 908 | tb->nonresum_qmask); |
| 909 | |
| 910 | init_cpu_send_mondo_info(tb); |
| 911 | } |
| 912 | |
| 913 | /* Load up the boot cpu's entries. */ |
| 914 | sun4v_register_mondo_queues(hard_smp_processor_id()); |
| 915 | } |
| 916 | |
| 917 | static struct irqaction timer_irq_action = { |
| 918 | .name = "timer", |
| 919 | }; |
| 920 | |
| 921 | /* Only invoked on boot processor. */ |
| 922 | void __init init_IRQ(void) |
| 923 | { |
| 924 | unsigned long size; |
| 925 | |
| 926 | map_prom_timers(); |
| 927 | kill_prom_timer(); |
| 928 | |
| 929 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
| 930 | ivector_table = alloc_bootmem(size); |
| 931 | if (!ivector_table) { |
| 932 | prom_printf("Fatal error, cannot allocate ivector_table\n"); |
| 933 | prom_halt(); |
| 934 | } |
| 935 | __flush_dcache_range((unsigned long) ivector_table, |
| 936 | ((unsigned long) ivector_table) + size); |
| 937 | |
| 938 | ivector_table_pa = __pa(ivector_table); |
| 939 | |
| 940 | if (tlb_type == hypervisor) |
| 941 | sun4v_init_mondo_queues(); |
| 942 | |
| 943 | /* We need to clear any IRQ's pending in the soft interrupt |
| 944 | * registers, a spurious one could be left around from the |
| 945 | * PROM timer which we just disabled. |
| 946 | */ |
| 947 | clear_softint(get_softint()); |
| 948 | |
| 949 | /* Now that ivector table is initialized, it is safe |
| 950 | * to receive IRQ vector traps. We will normally take |
| 951 | * one or two right now, in case some device PROM used |
| 952 | * to boot us wants to speak to us. We just ignore them. |
| 953 | */ |
| 954 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" |
| 955 | "or %%g1, %0, %%g1\n\t" |
| 956 | "wrpr %%g1, 0x0, %%pstate" |
| 957 | : /* No outputs */ |
| 958 | : "i" (PSTATE_IE) |
| 959 | : "g1"); |
| 960 | |
| 961 | irq_desc[0].action = &timer_irq_action; |
| 962 | } |