| 1 | /* pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
| 2 | * |
| 3 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
| 4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
| 5 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) |
| 6 | */ |
| 7 | |
| 8 | #include <linux/kernel.h> |
| 9 | #include <linux/types.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/slab.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/of_device.h> |
| 15 | |
| 16 | #include <asm/iommu.h> |
| 17 | #include <asm/irq.h> |
| 18 | #include <asm/starfire.h> |
| 19 | #include <asm/prom.h> |
| 20 | |
| 21 | #include "pci_impl.h" |
| 22 | #include "iommu_common.h" |
| 23 | #include "psycho_common.h" |
| 24 | |
| 25 | #define DRIVER_NAME "psycho" |
| 26 | #define PFX DRIVER_NAME ": " |
| 27 | |
| 28 | /* All PSYCHO registers are 64-bits. The following accessor |
| 29 | * routines are how they are accessed. The REG parameter |
| 30 | * is a physical address. |
| 31 | */ |
| 32 | #define psycho_read(__reg) \ |
| 33 | ({ u64 __ret; \ |
| 34 | __asm__ __volatile__("ldxa [%1] %2, %0" \ |
| 35 | : "=r" (__ret) \ |
| 36 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 37 | : "memory"); \ |
| 38 | __ret; \ |
| 39 | }) |
| 40 | #define psycho_write(__reg, __val) \ |
| 41 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
| 42 | : /* no outputs */ \ |
| 43 | : "r" (__val), "r" (__reg), \ |
| 44 | "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 45 | : "memory") |
| 46 | |
| 47 | /* Misc. PSYCHO PCI controller register offsets and definitions. */ |
| 48 | #define PSYCHO_CONTROL 0x0010UL |
| 49 | #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ |
| 50 | #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ |
| 51 | #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ |
| 52 | #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ |
| 53 | #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ |
| 54 | #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ |
| 55 | #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ |
| 56 | #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ |
| 57 | #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ |
| 58 | #define PSYCHO_PCIA_CTRL 0x2000UL |
| 59 | #define PSYCHO_PCIB_CTRL 0x4000UL |
| 60 | #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ |
| 61 | #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ |
| 62 | #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ |
| 63 | #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ |
| 64 | #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ |
| 65 | #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ |
| 66 | #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ |
| 67 | #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ |
| 68 | #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ |
| 69 | #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
| 70 | #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ |
| 71 | #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ |
| 72 | |
| 73 | /* U2P Programmer's Manual, page 13-55, configuration space |
| 74 | * address format: |
| 75 | * |
| 76 | * 32 24 23 16 15 11 10 8 7 2 1 0 |
| 77 | * --------------------------------------------------------- |
| 78 | * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 | |
| 79 | * --------------------------------------------------------- |
| 80 | */ |
| 81 | #define PSYCHO_CONFIG_BASE(PBM) \ |
| 82 | ((PBM)->config_space | (1UL << 24)) |
| 83 | #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ |
| 84 | (((unsigned long)(BUS) << 16) | \ |
| 85 | ((unsigned long)(DEVFN) << 8) | \ |
| 86 | ((unsigned long)(REG))) |
| 87 | |
| 88 | static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm, |
| 89 | unsigned char bus, |
| 90 | unsigned int devfn, |
| 91 | int where) |
| 92 | { |
| 93 | if (!pbm) |
| 94 | return NULL; |
| 95 | return (void *) |
| 96 | (PSYCHO_CONFIG_BASE(pbm) | |
| 97 | PSYCHO_CONFIG_ENCODE(bus, devfn, where)); |
| 98 | } |
| 99 | |
| 100 | /* PSYCHO error handling support. */ |
| 101 | |
| 102 | /* Helper function of IOMMU error checking, which checks out |
| 103 | * the state of the streaming buffers. The IOMMU lock is |
| 104 | * held when this is called. |
| 105 | * |
| 106 | * For the PCI error case we know which PBM (and thus which |
| 107 | * streaming buffer) caused the error, but for the uncorrectable |
| 108 | * error case we do not. So we always check both streaming caches. |
| 109 | */ |
| 110 | #define PSYCHO_STRBUF_CONTROL_A 0x2800UL |
| 111 | #define PSYCHO_STRBUF_CONTROL_B 0x4800UL |
| 112 | #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ |
| 113 | #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ |
| 114 | #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ |
| 115 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
| 116 | #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ |
| 117 | #define PSYCHO_STRBUF_FLUSH_A 0x2808UL |
| 118 | #define PSYCHO_STRBUF_FLUSH_B 0x4808UL |
| 119 | #define PSYCHO_STRBUF_FSYNC_A 0x2810UL |
| 120 | #define PSYCHO_STRBUF_FSYNC_B 0x4810UL |
| 121 | #define PSYCHO_STC_DATA_A 0xb000UL |
| 122 | #define PSYCHO_STC_DATA_B 0xc000UL |
| 123 | #define PSYCHO_STC_ERR_A 0xb400UL |
| 124 | #define PSYCHO_STC_ERR_B 0xc400UL |
| 125 | #define PSYCHO_STC_TAG_A 0xb800UL |
| 126 | #define PSYCHO_STC_TAG_B 0xc800UL |
| 127 | #define PSYCHO_STC_LINE_A 0xb900UL |
| 128 | #define PSYCHO_STC_LINE_B 0xc900UL |
| 129 | |
| 130 | /* When an Uncorrectable Error or a PCI Error happens, we |
| 131 | * interrogate the IOMMU state to see if it is the cause. |
| 132 | */ |
| 133 | #define PSYCHO_IOMMU_CONTROL 0x0200UL |
| 134 | #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ |
| 135 | #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ |
| 136 | #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ |
| 137 | #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ |
| 138 | #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ |
| 139 | #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
| 140 | #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ |
| 141 | #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ |
| 142 | #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ |
| 143 | #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ |
| 144 | #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ |
| 145 | #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ |
| 146 | #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ |
| 147 | #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ |
| 148 | #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ |
| 149 | #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ |
| 150 | #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ |
| 151 | #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
| 152 | #define PSYCHO_IOMMU_TSBBASE 0x0208UL |
| 153 | #define PSYCHO_IOMMU_FLUSH 0x0210UL |
| 154 | #define PSYCHO_IOMMU_TAG 0xa580UL |
| 155 | #define PSYCHO_IOMMU_DATA 0xa600UL |
| 156 | |
| 157 | /* Uncorrectable Errors. Cause of the error and the address are |
| 158 | * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors |
| 159 | * relating to UPA interface transactions. |
| 160 | */ |
| 161 | #define PSYCHO_UE_AFSR 0x0030UL |
| 162 | #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 163 | #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 164 | #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 165 | #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 166 | #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 167 | #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 168 | #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| 169 | #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 170 | #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ |
| 171 | #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 172 | #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 173 | #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 174 | #define PSYCHO_UE_AFAR 0x0038UL |
| 175 | |
| 176 | static irqreturn_t psycho_ue_intr(int irq, void *dev_id) |
| 177 | { |
| 178 | struct pci_pbm_info *pbm = dev_id; |
| 179 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; |
| 180 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; |
| 181 | unsigned long afsr, afar, error_bits; |
| 182 | int reported; |
| 183 | |
| 184 | /* Latch uncorrectable error status. */ |
| 185 | afar = psycho_read(afar_reg); |
| 186 | afsr = psycho_read(afsr_reg); |
| 187 | |
| 188 | /* Clear the primary/secondary error status bits. */ |
| 189 | error_bits = afsr & |
| 190 | (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | |
| 191 | PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); |
| 192 | if (!error_bits) |
| 193 | return IRQ_NONE; |
| 194 | psycho_write(afsr_reg, error_bits); |
| 195 | |
| 196 | /* Log the error. */ |
| 197 | printk("%s: Uncorrectable Error, primary error type[%s]\n", |
| 198 | pbm->name, |
| 199 | (((error_bits & PSYCHO_UEAFSR_PPIO) ? |
| 200 | "PIO" : |
| 201 | ((error_bits & PSYCHO_UEAFSR_PDRD) ? |
| 202 | "DMA Read" : |
| 203 | ((error_bits & PSYCHO_UEAFSR_PDWR) ? |
| 204 | "DMA Write" : "???"))))); |
| 205 | printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
| 206 | pbm->name, |
| 207 | (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
| 208 | (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, |
| 209 | (afsr & PSYCHO_UEAFSR_MID) >> 24UL, |
| 210 | ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); |
| 211 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
| 212 | printk("%s: UE Secondary errors [", pbm->name); |
| 213 | reported = 0; |
| 214 | if (afsr & PSYCHO_UEAFSR_SPIO) { |
| 215 | reported++; |
| 216 | printk("(PIO)"); |
| 217 | } |
| 218 | if (afsr & PSYCHO_UEAFSR_SDRD) { |
| 219 | reported++; |
| 220 | printk("(DMA Read)"); |
| 221 | } |
| 222 | if (afsr & PSYCHO_UEAFSR_SDWR) { |
| 223 | reported++; |
| 224 | printk("(DMA Write)"); |
| 225 | } |
| 226 | if (!reported) |
| 227 | printk("(none)"); |
| 228 | printk("]\n"); |
| 229 | |
| 230 | /* Interrogate both IOMMUs for error status. */ |
| 231 | psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); |
| 232 | if (pbm->sibling) |
| 233 | psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); |
| 234 | |
| 235 | return IRQ_HANDLED; |
| 236 | } |
| 237 | |
| 238 | /* Correctable Errors. */ |
| 239 | #define PSYCHO_CE_AFSR 0x0040UL |
| 240 | #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 241 | #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 242 | #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 243 | #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 244 | #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 245 | #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 246 | #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
| 247 | #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
| 248 | #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 249 | #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ |
| 250 | #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 251 | #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 252 | #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 253 | #define PSYCHO_CE_AFAR 0x0040UL |
| 254 | |
| 255 | static irqreturn_t psycho_ce_intr(int irq, void *dev_id) |
| 256 | { |
| 257 | struct pci_pbm_info *pbm = dev_id; |
| 258 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; |
| 259 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; |
| 260 | unsigned long afsr, afar, error_bits; |
| 261 | int reported; |
| 262 | |
| 263 | /* Latch error status. */ |
| 264 | afar = psycho_read(afar_reg); |
| 265 | afsr = psycho_read(afsr_reg); |
| 266 | |
| 267 | /* Clear primary/secondary error status bits. */ |
| 268 | error_bits = afsr & |
| 269 | (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | |
| 270 | PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); |
| 271 | if (!error_bits) |
| 272 | return IRQ_NONE; |
| 273 | psycho_write(afsr_reg, error_bits); |
| 274 | |
| 275 | /* Log the error. */ |
| 276 | printk("%s: Correctable Error, primary error type[%s]\n", |
| 277 | pbm->name, |
| 278 | (((error_bits & PSYCHO_CEAFSR_PPIO) ? |
| 279 | "PIO" : |
| 280 | ((error_bits & PSYCHO_CEAFSR_PDRD) ? |
| 281 | "DMA Read" : |
| 282 | ((error_bits & PSYCHO_CEAFSR_PDWR) ? |
| 283 | "DMA Write" : "???"))))); |
| 284 | |
| 285 | /* XXX Use syndrome and afar to print out module string just like |
| 286 | * XXX UDB CE trap handler does... -DaveM |
| 287 | */ |
| 288 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
| 289 | "UPA_MID[%02lx] was_block(%d)\n", |
| 290 | pbm->name, |
| 291 | (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
| 292 | (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, |
| 293 | (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, |
| 294 | (afsr & PSYCHO_CEAFSR_MID) >> 24UL, |
| 295 | ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); |
| 296 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
| 297 | printk("%s: CE Secondary errors [", pbm->name); |
| 298 | reported = 0; |
| 299 | if (afsr & PSYCHO_CEAFSR_SPIO) { |
| 300 | reported++; |
| 301 | printk("(PIO)"); |
| 302 | } |
| 303 | if (afsr & PSYCHO_CEAFSR_SDRD) { |
| 304 | reported++; |
| 305 | printk("(DMA Read)"); |
| 306 | } |
| 307 | if (afsr & PSYCHO_CEAFSR_SDWR) { |
| 308 | reported++; |
| 309 | printk("(DMA Write)"); |
| 310 | } |
| 311 | if (!reported) |
| 312 | printk("(none)"); |
| 313 | printk("]\n"); |
| 314 | |
| 315 | return IRQ_HANDLED; |
| 316 | } |
| 317 | |
| 318 | /* PCI Errors. They are signalled by the PCI bus module since they |
| 319 | * are associated with a specific bus segment. |
| 320 | */ |
| 321 | #define PSYCHO_PCI_AFSR_A 0x2010UL |
| 322 | #define PSYCHO_PCI_AFSR_B 0x4010UL |
| 323 | #define PSYCHO_PCI_AFAR_A 0x2018UL |
| 324 | #define PSYCHO_PCI_AFAR_B 0x4018UL |
| 325 | |
| 326 | /* XXX What about PowerFail/PowerManagement??? -DaveM */ |
| 327 | #define PSYCHO_ECC_CTRL 0x0020 |
| 328 | #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ |
| 329 | #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ |
| 330 | #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ |
| 331 | static void psycho_register_error_handlers(struct pci_pbm_info *pbm) |
| 332 | { |
| 333 | struct of_device *op = of_find_device_by_node(pbm->op->node); |
| 334 | unsigned long base = pbm->controller_regs; |
| 335 | u64 tmp; |
| 336 | int err; |
| 337 | |
| 338 | if (!op) |
| 339 | return; |
| 340 | |
| 341 | /* Psycho interrupt property order is: |
| 342 | * 0: PCIERR INO for this PBM |
| 343 | * 1: UE ERR |
| 344 | * 2: CE ERR |
| 345 | * 3: POWER FAIL |
| 346 | * 4: SPARE HARDWARE |
| 347 | * 5: POWER MANAGEMENT |
| 348 | */ |
| 349 | |
| 350 | if (op->num_irqs < 6) |
| 351 | return; |
| 352 | |
| 353 | /* We really mean to ignore the return result here. Two |
| 354 | * PCI controller share the same interrupt numbers and |
| 355 | * drive the same front-end hardware. Whichever of the |
| 356 | * two get in here first will register the IRQ handler |
| 357 | * the second will just error out since we do not pass in |
| 358 | * IRQF_SHARED. |
| 359 | */ |
| 360 | err = request_irq(op->irqs[1], psycho_ue_intr, 0, |
| 361 | "PSYCHO_UE", pbm); |
| 362 | err = request_irq(op->irqs[2], psycho_ce_intr, 0, |
| 363 | "PSYCHO_CE", pbm); |
| 364 | |
| 365 | /* This one, however, ought not to fail. We can just warn |
| 366 | * about it since the system can still operate properly even |
| 367 | * if this fails. |
| 368 | */ |
| 369 | err = request_irq(op->irqs[0], psycho_pcierr_intr, 0, |
| 370 | "PSYCHO_PCIERR", pbm); |
| 371 | if (err) |
| 372 | printk(KERN_WARNING "%s: Could not register PCIERR, " |
| 373 | "err=%d\n", pbm->name, err); |
| 374 | |
| 375 | /* Enable UE and CE interrupts for controller. */ |
| 376 | psycho_write(base + PSYCHO_ECC_CTRL, |
| 377 | (PSYCHO_ECCCTRL_EE | |
| 378 | PSYCHO_ECCCTRL_UE | |
| 379 | PSYCHO_ECCCTRL_CE)); |
| 380 | |
| 381 | /* Enable PCI Error interrupts and clear error |
| 382 | * bits for each PBM. |
| 383 | */ |
| 384 | tmp = psycho_read(base + PSYCHO_PCIA_CTRL); |
| 385 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 386 | PSYCHO_PCICTRL_SBH_ERR | |
| 387 | PSYCHO_PCICTRL_EEN); |
| 388 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
| 389 | psycho_write(base + PSYCHO_PCIA_CTRL, tmp); |
| 390 | |
| 391 | tmp = psycho_read(base + PSYCHO_PCIB_CTRL); |
| 392 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 393 | PSYCHO_PCICTRL_SBH_ERR | |
| 394 | PSYCHO_PCICTRL_EEN); |
| 395 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
| 396 | psycho_write(base + PSYCHO_PCIB_CTRL, tmp); |
| 397 | } |
| 398 | |
| 399 | /* PSYCHO boot time probing and initialization. */ |
| 400 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
| 401 | { |
| 402 | u8 *addr; |
| 403 | |
| 404 | /* Set cache-line size to 64 bytes, this is actually |
| 405 | * a nop but I do it for completeness. |
| 406 | */ |
| 407 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 408 | 0, PCI_CACHE_LINE_SIZE); |
| 409 | pci_config_write8(addr, 64 / sizeof(u32)); |
| 410 | |
| 411 | /* Set PBM latency timer to 64 PCI clocks. */ |
| 412 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 413 | 0, PCI_LATENCY_TIMER); |
| 414 | pci_config_write8(addr, 64); |
| 415 | } |
| 416 | |
| 417 | static void __init psycho_scan_bus(struct pci_pbm_info *pbm, |
| 418 | struct device *parent) |
| 419 | { |
| 420 | pbm_config_busmastering(pbm); |
| 421 | pbm->is_66mhz_capable = 0; |
| 422 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
| 423 | |
| 424 | /* After the PCI bus scan is complete, we can register |
| 425 | * the error interrupt handlers. |
| 426 | */ |
| 427 | psycho_register_error_handlers(pbm); |
| 428 | } |
| 429 | |
| 430 | #define PSYCHO_IRQ_RETRY 0x1a00UL |
| 431 | #define PSYCHO_PCIA_DIAG 0x2020UL |
| 432 | #define PSYCHO_PCIB_DIAG 0x4020UL |
| 433 | #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ |
| 434 | #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ |
| 435 | #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ |
| 436 | #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ |
| 437 | #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ |
| 438 | #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ |
| 439 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ |
| 440 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ |
| 441 | |
| 442 | static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
| 443 | { |
| 444 | u64 tmp; |
| 445 | |
| 446 | psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5); |
| 447 | |
| 448 | /* Enable arbiter for all PCI slots. */ |
| 449 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
| 450 | tmp |= PSYCHO_PCICTRL_AEN; |
| 451 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp); |
| 452 | |
| 453 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
| 454 | tmp |= PSYCHO_PCICTRL_AEN; |
| 455 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp); |
| 456 | |
| 457 | /* Disable DMA write / PIO read synchronization on |
| 458 | * both PCI bus segments. |
| 459 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] |
| 460 | */ |
| 461 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
| 462 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
| 463 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp); |
| 464 | |
| 465 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
| 466 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
| 467 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp); |
| 468 | } |
| 469 | |
| 470 | static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
| 471 | int is_pbm_a) |
| 472 | { |
| 473 | unsigned long base = pbm->controller_regs; |
| 474 | u64 control; |
| 475 | |
| 476 | if (is_pbm_a) { |
| 477 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; |
| 478 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; |
| 479 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; |
| 480 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; |
| 481 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; |
| 482 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; |
| 483 | } else { |
| 484 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; |
| 485 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; |
| 486 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; |
| 487 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; |
| 488 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; |
| 489 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; |
| 490 | } |
| 491 | /* PSYCHO's streaming buffer lacks ctx flushing. */ |
| 492 | pbm->stc.strbuf_ctxflush = 0; |
| 493 | pbm->stc.strbuf_ctxmatch_base = 0; |
| 494 | |
| 495 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) |
| 496 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) |
| 497 | + 63UL) |
| 498 | & ~63UL); |
| 499 | pbm->stc.strbuf_flushflag_pa = (unsigned long) |
| 500 | __pa(pbm->stc.strbuf_flushflag); |
| 501 | |
| 502 | /* Enable the streaming buffer. We have to be careful |
| 503 | * just in case OBP left it with LRU locking enabled. |
| 504 | * |
| 505 | * It is possible to control if PBM will be rerun on |
| 506 | * line misses. Currently I just retain whatever setting |
| 507 | * OBP left us with. All checks so far show it having |
| 508 | * a value of zero. |
| 509 | */ |
| 510 | #undef PSYCHO_STRBUF_RERUN_ENABLE |
| 511 | #undef PSYCHO_STRBUF_RERUN_DISABLE |
| 512 | control = psycho_read(pbm->stc.strbuf_control); |
| 513 | control |= PSYCHO_STRBUF_CTRL_ENAB; |
| 514 | control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); |
| 515 | #ifdef PSYCHO_STRBUF_RERUN_ENABLE |
| 516 | control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); |
| 517 | #else |
| 518 | #ifdef PSYCHO_STRBUF_RERUN_DISABLE |
| 519 | control |= PSYCHO_STRBUF_CTRL_RRDIS; |
| 520 | #endif |
| 521 | #endif |
| 522 | psycho_write(pbm->stc.strbuf_control, control); |
| 523 | |
| 524 | pbm->stc.strbuf_enabled = 1; |
| 525 | } |
| 526 | |
| 527 | #define PSYCHO_IOSPACE_A 0x002000000UL |
| 528 | #define PSYCHO_IOSPACE_B 0x002010000UL |
| 529 | #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL |
| 530 | #define PSYCHO_MEMSPACE_A 0x100000000UL |
| 531 | #define PSYCHO_MEMSPACE_B 0x180000000UL |
| 532 | #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL |
| 533 | |
| 534 | static void __init psycho_pbm_init(struct pci_pbm_info *pbm, |
| 535 | struct of_device *op, int is_pbm_a) |
| 536 | { |
| 537 | psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); |
| 538 | psycho_pbm_strbuf_init(pbm, is_pbm_a); |
| 539 | psycho_scan_bus(pbm, &op->dev); |
| 540 | } |
| 541 | |
| 542 | static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid) |
| 543 | { |
| 544 | struct pci_pbm_info *pbm; |
| 545 | |
| 546 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
| 547 | if (pbm->portid == upa_portid) |
| 548 | return pbm; |
| 549 | } |
| 550 | return NULL; |
| 551 | } |
| 552 | |
| 553 | #define PSYCHO_CONFIGSPACE 0x001000000UL |
| 554 | |
| 555 | static int __devinit psycho_probe(struct of_device *op, |
| 556 | const struct of_device_id *match) |
| 557 | { |
| 558 | const struct linux_prom64_registers *pr_regs; |
| 559 | struct device_node *dp = op->node; |
| 560 | struct pci_pbm_info *pbm; |
| 561 | struct iommu *iommu; |
| 562 | int is_pbm_a, err; |
| 563 | u32 upa_portid; |
| 564 | |
| 565 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
| 566 | |
| 567 | err = -ENOMEM; |
| 568 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
| 569 | if (!pbm) { |
| 570 | printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); |
| 571 | goto out_err; |
| 572 | } |
| 573 | |
| 574 | pbm->sibling = psycho_find_sibling(upa_portid); |
| 575 | if (pbm->sibling) { |
| 576 | iommu = pbm->sibling->iommu; |
| 577 | } else { |
| 578 | iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); |
| 579 | if (!iommu) { |
| 580 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); |
| 581 | goto out_free_controller; |
| 582 | } |
| 583 | } |
| 584 | |
| 585 | pbm->iommu = iommu; |
| 586 | pbm->portid = upa_portid; |
| 587 | |
| 588 | pr_regs = of_get_property(dp, "reg", NULL); |
| 589 | err = -ENODEV; |
| 590 | if (!pr_regs) { |
| 591 | printk(KERN_ERR PFX "No reg property.\n"); |
| 592 | goto out_free_iommu; |
| 593 | } |
| 594 | |
| 595 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
| 596 | |
| 597 | pbm->controller_regs = pr_regs[2].phys_addr; |
| 598 | pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); |
| 599 | |
| 600 | if (is_pbm_a) { |
| 601 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; |
| 602 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; |
| 603 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; |
| 604 | } else { |
| 605 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; |
| 606 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; |
| 607 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; |
| 608 | } |
| 609 | |
| 610 | psycho_controller_hwinit(pbm); |
| 611 | if (!pbm->sibling) { |
| 612 | err = psycho_iommu_init(pbm, 128, 0xc0000000, |
| 613 | 0xffffffff, PSYCHO_CONTROL); |
| 614 | if (err) |
| 615 | goto out_free_iommu; |
| 616 | |
| 617 | /* If necessary, hook us up for starfire IRQ translations. */ |
| 618 | if (this_is_starfire) |
| 619 | starfire_hookup(pbm->portid); |
| 620 | } |
| 621 | |
| 622 | psycho_pbm_init(pbm, op, is_pbm_a); |
| 623 | |
| 624 | pbm->next = pci_pbm_root; |
| 625 | pci_pbm_root = pbm; |
| 626 | |
| 627 | if (pbm->sibling) |
| 628 | pbm->sibling->sibling = pbm; |
| 629 | |
| 630 | dev_set_drvdata(&op->dev, pbm); |
| 631 | |
| 632 | return 0; |
| 633 | |
| 634 | out_free_iommu: |
| 635 | if (!pbm->sibling) |
| 636 | kfree(pbm->iommu); |
| 637 | |
| 638 | out_free_controller: |
| 639 | kfree(pbm); |
| 640 | |
| 641 | out_err: |
| 642 | return err; |
| 643 | } |
| 644 | |
| 645 | static struct of_device_id __initdata psycho_match[] = { |
| 646 | { |
| 647 | .name = "pci", |
| 648 | .compatible = "pci108e,8000", |
| 649 | }, |
| 650 | {}, |
| 651 | }; |
| 652 | |
| 653 | static struct of_platform_driver psycho_driver = { |
| 654 | .name = DRIVER_NAME, |
| 655 | .match_table = psycho_match, |
| 656 | .probe = psycho_probe, |
| 657 | }; |
| 658 | |
| 659 | static int __init psycho_init(void) |
| 660 | { |
| 661 | return of_register_driver(&psycho_driver, &of_bus_type); |
| 662 | } |
| 663 | |
| 664 | subsys_initcall(psycho_init); |